Apparatus comprising phase-locked loop circuit

Abstract

In one embodiment, an apparatus includes a phase-locked loop circuit including: an input configured to receive an oscillating reference signal having a reference period; a current controlled oscillator (CCO) configured to generate an oscillating output signal based on an input signal; an error detector configured to generate one or more error signals based on a phase difference between the reference signal and one or more feedback signals, where the feedback signals are based on the oscillating output signal; and a charge pump circuit configured to receive at least a first one of the error signals, determine a voltage indicative of a duration of the first error signal during a first portion of the reference period, and provide a control current to the CCO for at least a remaining portion of the reference period, wherein the control current comprises at least a portion of the input signal delivered to the CCO and is based on the determined voltage.

Description

Technical Field

[0001] This disclosure relates to an apparatus including a phase-locked loop (PLL) circuit. More specifically, this disclosure relates to an apparatus including a PLL circuit comprising a charge pump circuit for reducing signal spurious signals in the output of the PLL circuit. Background Technology

[0002] A phase-locked loop (PLL) is a circuit that generates an output signal whose phase and frequency are based on the phase of the input signal. Providing a PLL with improved signal performance remains a challenge. Summary of the Invention

[0003] According to a first aspect of this disclosure, an apparatus is provided, comprising:

[0004] Phase-locked loop circuit, the phase-locked loop circuit comprising:

[0005] The input is configured to receive an oscillating reference signal having a reference period;

[0006] A current-controlled oscillator (CCO) configured to generate an oscillating output signal based on an input signal;

[0007] An error detector configured to generate one or more error signals based on a phase difference between the reference signal and at least one of one or more feedback signals, wherein the one or more feedback signals are based on the oscillating output signal; and

[0008] A charge pump circuit configured to receive at least a first error signal from the one or more error signals, determine a voltage indicating the duration of the first error signal during a first portion of the reference period, and provide a control current to the CCO during at least the remaining portion of the reference period, wherein the control current includes at least a portion of the input signal sent to the CCO and is based on the determined voltage.

[0009] In one or more embodiments, the error detector may be a phase-frequency detector, the phase-frequency detector comprising:

[0010] A first proportional component is configured to generate the first error signal among the one or more error signals based on the difference between the reference signal and a first feedback signal based on the oscillation output signal among the one or more feedback signals.

[0011] In one or more embodiments, the phase frequency detector further includes:

[0012] A second integrator is configured to generate a second error signal from the one or more error signals based on the integral of the difference between the reference signal and a second feedback signal based on the oscillation output signal among the one or more feedback signals.

[0013] In one or more embodiments, the charge pump circuit includes a first charge pump circuit, and the control current includes a first control current, wherein the first charge pump circuit is configured to receive the first error signal, determine the voltage indicating the duration of the first error signal during the first portion of the reference period, and provide the CCO with the first control current based on the determined voltage, including at least a portion of the input signal, during at least the remaining portion of the reference period.

[0014] In one or more embodiments, the charge pump circuit further includes:

[0015] A second charge pump circuit, configured to generate a control signal based on the second error signal; and

[0016] A current source configured to generate a second control current based on the control signal.

[0017] In one or more embodiments, the input signal sent to the CCO is based on the first control current and the second control current.

[0018] In one or more embodiments, the charge pump circuit includes a time-voltage circuit configured to convert at least one of the one or more error signals representing the phase difference between the reference signal and the one or more feedback signals into a voltage signal.

[0019] In one or more embodiments, the charge pump circuit further includes a voltage-current circuit configured to receive the voltage signal from the time-voltage circuit and convert the voltage signal into the control current.

[0020] In one or more embodiments, the first charge pump circuit includes: a time-voltage circuit configured to convert the first error signal into a voltage signal; and a voltage-current circuit configured to receive the voltage signal from the time-voltage circuit and convert the voltage signal into the control current.

[0021] In one or more embodiments:

[0022] The time-voltage circuit includes a first capacitor, and the time-voltage circuit is configured such that when the first error signal is provided to the time-voltage circuit, the first capacitor is charged by a current induced by the source voltage.

[0023] In one or more embodiments:

[0024] The time-voltage circuit includes a second capacitor, and wherein the charge pump circuit is configured to sample the error signal via the time-voltage circuit during the first portion of the reference period, the time-voltage circuit being configured to couple the first capacitor to the second capacitor such that the second capacitor is charged by the first capacitor and the voltage on the second capacitor defines the voltage signal.

[0025] In one or more embodiments:

[0026] The voltage-current circuit includes a voltage follower configured to receive the voltage signal from the second capacitor and control the voltage applied to the impedance circuit based on the voltage signal.

[0027] In one or more embodiments:

[0028] The impedance circuit includes a switched capacitor circuit, which includes a third capacitor that switches at the frequency of the oscillation output signal.

[0029] In one or more embodiments:

[0030] The control current is based on the voltage across the impedance circuit.

[0031] In one or more embodiments, the first capacitor and the third capacitor are of the same type, and the capacitance ratio between the first capacitor and the third capacitor is programmable.

[0032] In one or more embodiments, the voltage follower includes a first amplifier and a first transistor.

[0033] In one or more embodiments:

[0034] The output of the first amplifier can be coupled to the gate of the first transistor.

[0035] The non-inverting input of the first amplifier can be coupled to the second capacitor.

[0036] The inverting input of the first amplifier can be coupled to the source terminal of the first transistor.

[0037] The source terminal of the first transistor can be coupled to a first terminal of the impedance circuit.

[0038] The second terminal of the impedance circuit can be configured to be coupled to a reference voltage, and

[0039] The drain terminal of the first transistor may be coupled to receive the second control current.

[0040] In one or more embodiments, the current source includes a second transistor having a source terminal configured to be coupled to a voltage source, a gate terminal configured to receive the control signal based on the second error signal, and a drain terminal configured to provide the second control current for controlling the CCO.

[0041] In one or more embodiments, the source terminal of the second transistor is further coupled to a first terminal of a fourth capacitor, and the gate terminal of the second transistor is further coupled to a second terminal of the fourth capacitor.

[0042] In one or more embodiments, the time-voltage circuit is configured to be coupled to a voltage source via a third transistor having a source terminal configured to be coupled to the voltage source, a gate terminal configured to receive the control signal based on the second error signal, and a drain terminal configured to provide supply current to the first capacitor.

[0043] In one or more embodiments, the source terminal of the third transistor is also coupled to the first terminal of the fourth capacitor, and the gate terminal of the second transistor is also coupled to the second terminal of the fourth capacitor.

[0044] In one or more embodiments, the device further includes a controller configured to provide the first feedback signal to the first proportional component in advance of providing the second feedback signal to the second integral component.

[0045] In one or more embodiments, the advance is based on a predetermined number of oscillations of the oscillating output signal.

[0046] In one or more embodiments, the device further includes a controller configured to generate a reset signal to short-circuit the first capacitor before the controller is configured to generate a sampling signal.

[0047] In one or more embodiments, the first charge pump circuit is configured to sample the determined voltage during the first portion of the reference period based on receiving the sampling signal.

[0048] In one or more embodiments, the device is configured to provide a constant current to the time-voltage circuit.

[0049] In one or more embodiments, the input signal sent to the CCO is based on the second control current minus the first control current.

[0050] In one or more embodiments, the device further includes an additional proportional charge pump configured to supply a third control current to the CCO, wherein the third control current is constant.

[0051] According to a second aspect of this disclosure, an electronic device including the device of the first aspect is provided.

[0052] While this disclosure allows for various modifications and alternatives, details of this disclosure have been illustrated by way of example in the accompanying drawings and will be described in detail. However, it should be understood that other embodiments besides the specific embodiments described are also possible. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are also covered.

[0053] The foregoing discussion is not intended to represent every exemplary embodiment or every implementation within the scope of the present or future claims. Various exemplary embodiments are further illustrated in the figures and the following detailed description. A more comprehensive understanding of the various exemplary embodiments can be achieved by considering the following detailed description in conjunction with the accompanying drawings. Attached Figure Description

[0054] One or more embodiments will now be described with reference to the accompanying drawings, by way of example only, in which:

[0055] Figure 1 An example device according to an embodiment of the present disclosure is shown; and

[0056] Figure 2 A signal diagram representing multiple signals within the example device is shown. Detailed Implementation

[0057] Phase-locked loop (PLL) circuits can suffer from reference clock feedthrough, which manifests as spurious noise. This spurious noise may be due to phase errors at the input of an error detector that is part of the PLL. Spurious noise can limit the phase noise performance of the PLL. Phase errors can have different underlying causes, such as mismatch or leakage, but in some cases, they can also be intentionally introduced, such as for linearization in fractional PLLs. Reference clock feedthrough can be reduced by filtering, but further improvements are needed.

[0058] Figure 1An example device according to an embodiment of the present disclosure is shown. The device includes a PLL circuit 100, the PLL circuit 100 including components configured to receive an oscillating reference signal F having a reference period. ref Input 108. The PLL circuit 100 further includes a current-controlled oscillator CCO 101, which is configured to generate an oscillating output signal F based on input signals provided to it by other components of the PLL circuit 100, as described below. CCO The PLL circuit 100 also includes an error detector 110, which is configured to base its signal on a reference signal F provided at a first input terminal 111A. ref With at least one of one or more feedback signals provided at the second input terminal 111B (e.g., feedback signal FB) PROP The error detector 110 generates one or more error signals by using the phase difference between the phase difference and the frequency difference. In this embodiment, the error detector 110 is a phase-frequency detector, and will be referred to so in the remainder of this disclosure for ease of understanding. However, it should be understood that other error detectors, such as subsamplers, may be used alternatively.

[0059] One or more feedback signals are based on the oscillation output signal F CCO For example, one or more feedback signals may include an oscillating output signal F. CCO , or oscillation output signal F CCO The frequency division (or frequency multiplication) version, or the oscillation output signal F CCO The filtered version. One or more feedback signals can also be relative to the oscillation output signal F. CCO Phase shift. Device 100 also includes charge pump circuits 120, 130, and 140, which are configured to receive at least one of one or more error signals and sample the source voltage based on the error signals during a first portion of a reference period. In some embodiments, the first portion of the reference period is the initial portion of the reference period. In other embodiments, the first portion of the reference period is a different portion of the reference period, such as the final portion of the reference period. Therefore, the voltage indicates the duration of the error signal. The charge pump circuits are further configured to provide a control current to CCO 101 for at least the remaining portion of the reference period. In some examples, the control current is provided to CCO 101 until a new value is available. That is, until the source voltage is sampled again. The control current based on the sampled source voltage includes the input signal to CCO 101 or at least a portion of the input signal to CCO 101.

[0060] In this example embodiment, PLL circuit 100 includes a Type II dual charge pump PLL, and the oscillator of the PLL is CCO 101. However, it should be understood that any suitable alternative PLL circuit configuration can be used, such as PLL circuit 100 including a Type I charge pump. Here, the term "Type II dual charge pump PLL" refers to a PLL having two separate charge pumps 120, 130, and 140, wherein the phase frequency detector 110 includes a proportional component and an integral component. As those skilled in the art will understand, the proportional component determines the instantaneous difference between a reference signal and one or more feedback signals, and the integral component determines an integral or time average value based on the difference between the reference signal and one or more feedback signals over a certain time period.

[0061] In this example embodiment, the first proportional component 111 is configured based on the reference signal F ref With the first feedback signal FB PROP The difference between them generates a first error signal at the output terminal 111C, and the first feedback signal FB PROP Based on the oscillation output signal F CCO The second integrator 112 is configured to be based on the reference signal F. ref With the second feedback signal FB INT The second error signal is generated by integrating the difference between the two error signals. The second feedback signal is based on the oscillation output signal F. CCO In this example, as those skilled in the art will understand, the second error signal includes a first component or "downward" signal and a second component or "upward" signal provided at outputs 112A and 112B, respectively. The first and second error signals are provided for controlling the charge pump circuit.

[0062] In this embodiment, the oscillation output signal F CCO The second feedback signal FB is generated by dividing the frequency by 106 in the controller. INT However, any other suitable method can be used to generate the second feedback signal FB. INT In an alternative embodiment, PLL circuit 100 may include a Type I PLL that applies only a bias current instead of using the integration component 112 of phase frequency detector 110. Any other suitable phase frequency detector may be used, such as a subsampled digital phase frequency detector.

[0063] In some embodiments, charge pump circuits 120, 130 include a time-voltage circuit 120 connected to voltage-current circuit 130 for converting an error signal into a current applied to the CCO. In this example, the time-voltage circuit 120 is configured to convert a reference signal F... ref With one or more feedback signals FBPROP At least one of one or more error signals of phase difference between the two phases is converted into a voltage signal. The voltage-current circuit 130 is configured to receive the voltage signal from the time-voltage circuit 120 and convert the voltage signal into a control current for CCO 101.

[0064] However, in this example embodiment, the charge pump circuit includes a first charge pump circuit that outputs a first control current (provided by the time-voltage circuit 120 and the voltage-current circuit 130). Therefore, the first charge pump circuits 120 and 130 are configured to receive a first error signal PROP. dn The first error signal is sampled during the first part of the reference period, and a first control current is provided to CCO 101 during at least the remaining part of the reference period.

[0065] Additionally, in this example embodiment, the device includes a second charge pump circuit 140 provided by switching current sources 141 and 142, which are controlled by a component signal of a second error signal. The second charge pump circuit 140 is configured to generate a second charge pump current, which is used to generate a second charge pump current based on the second error signal INT. up INT dn A second control current is generated to control the CCO, as will be discussed below. Therefore, in this example, the input signal sent to the CCO 101 is based on the first and second control currents.

[0066] This embodiment illustrates a first error signal PROP, which includes a single "downward" pulse component as its output. dn The first charge pump circuit is controlled, as those skilled in the art will understand. Therefore, the proportional component 111 of the phase frequency detector 110 is a standard PFD, where only the downward output is utilized. In other embodiments, the first charge pump circuit may be configured to be controlled only by an "up" pulse or by both up and down pulses.

[0067] The time-voltage circuit 120 includes a first capacitor 121, and the time-voltage circuit 120 is configured such that the first capacitor 121 is based on a first error signal PROP. dnThe capacitor is charged to a certain voltage. The time-voltage circuit also includes a second capacitor 122. The charge pump circuit samples the error signal through the time-voltage circuit 120 during the first portion of the reference period. The time-voltage circuit 120 is configured to couple the first capacitor 121 to the second capacitor 122, such that the second capacitor 122 is charged by the first capacitor 121. It should be understood that other suitable methods for converting phase error time into voltage can be used, and other sampling methods can also be used. In this embodiment, the voltage-current circuit 130 includes voltage followers 131, 132, which are configured to receive the voltage of the second capacitor 122 and control the voltage applied to the impedance circuit based on the voltage of the second capacitor 122. The impedance circuit is formed by a third capacitor 133 and a pair of oscillating switches 134, 135. Current is supplied to the impedance circuit by a second transistor, as discussed below. The oscillating switches 134, 135 output an oscillating signal F. CCO Switch. The first control current is provided by the voltage across the third capacitor 133. Advantageously, because the third capacitor 133 oscillates at the output signal frequency F... CCO The switch is closed, so the voltage-current circuit 130 does not generate stray current. The use of the third capacitor 133 also allows the bandwidth to be independent of the first order of processing, supply voltage, and temperature (PVT). Alternatively, standard resistors can be used to replace impedance circuits 133, 134, and 135. Using resistors will not consume any power due to timing, but when combined with... Figure 1 Compared to the impedance circuits 133, 134, and 135 shown, it will lose the advantage of PVT independence.

[0068] In some embodiments, the first capacitor 121 and the third capacitor 133 are of the same type. Therefore, the first capacitor 121 and the third capacitor 133 respond to any changes in circuit conditions in the same way. Advantageously, this means that the oscillator control current is related to the master oscillator current and further depends only on the time error (master function), thus the bandwidth becomes almost independent of the PVT. This is because the current supplied by the second transistor 102 (which provides current to CCO 101, as discussed below) and the current supplied by the third transistor 105 (which provides current to the first capacitor) are the same, or supplied in a ratio, and depend on the oscillation output signal F. CCOThe frequency. Furthermore, it has been found that an intentional offset between the reference frequency and the oscillation output frequency does not lead to the generation of spurious signals. This is suitable for linearization purposes. The capacitance ratio between the first capacitor 121 and the third capacitor 133 can be predetermined or programmable to achieve the desired bandwidth of the PLL circuit 100. In embodiments where the current supplied by the second transistor 102 and the current supplied by the third transistor 105 are provided according to a ratio, the current ratio can be predetermined or programmable to achieve the desired bandwidth of the PLL circuit 100. The capacitance ratio and the current ratio can be the same or different.

[0069] exist Figure 1 In the illustrated embodiment, voltage followers 131, 132 include a first amplifier 131 (e.g., an operational transconductance amplifier) ​​and a first (e.g., an NMOS) transistor 132, wherein the output of the first amplifier 131 is coupled to the gate of the first transistor 132, the non-inverting input of the first amplifier 131 is coupled to a second capacitor 122, the inverting input of the first amplifier 131 is coupled to the source terminal of the first transistor 132, and the source terminal of the first transistor 132 is coupled to a first end of an impedance formed by a third capacitor 133 and oscillating switches 134, 135. A second end of the third capacitor 133 is configured to be coupled to a reference voltage terminal 107, and the drain terminal of the first transistor 132 is coupled to receive a portion of a second control current. The reference voltage terminal 107 may be ground, or it may be configured to provide a non-zero reference voltage. Although the first transistor 132 is described using language typically associated with a metal-oxide-semiconductor field-effect transistor (MOSFET), any other type of transistor may be used. This also applies to all other transistors described herein, and may require relevant circuit adjustments as understood by those skilled in the art.

[0070] In this embodiment, the second charge pump circuit 140 includes a first current source 141 and a second current source 142 coupled between the voltage source 103 and the reference voltage terminal. A second charge pump terminal 143 is connected between the first current source 141 and the second current source 142 and is configured to provide a control signal. A first switch is connected between the first current source 141 and the second charge pump terminal 143, and the first switch is controlled by a first component ("downward" signal) of a second error signal. A second switch is connected between the second current source 142 and the second charge pump terminal 143, and the second switch is controlled by a first component ("downward" signal) of the second error signal. Therefore, the second charge pump circuit 140 is configured based on the second error signal INT at the second charge pump terminal 143. dn INT up Provide control signals.

[0071] In this embodiment, the PLL circuit 100 further includes a second transistor 102, the second transistor 102 having a source terminal configured to be coupled to the voltage source 103 and configured to receive a second error signal INT. dn INT up The control signal gate terminal and the drain terminal of CCO 101 are configured to provide a second control current for controlling CCO 101. In this embodiment, CCO 101 is connected between the drain terminal of the second transistor 102 and the reference terminal 107; however, in other embodiments, CCO 101 may be connected between the drain terminal of the second transistor 102 and the voltage supply terminal 103, wherein the source terminal of the second transistor 102 is alternatively connected to the reference terminal 107. It should be understood that in these other embodiments, one or more other suitable adjustments may be made to the PLL circuit 100 to accommodate CCO 101 connected to the voltage supply terminal 103.

[0072] In this embodiment, the source terminal of the second transistor 102 is also coupled to the first terminal of the fourth capacitor 104, and the gate terminal of the second transistor 102 is also coupled to the second terminal of the fourth capacitor 104. Therefore, the fourth capacitor is coupled in parallel with the source and gate terminals of the second transistor 102, and the second error signal INT... dn INT up The integral is applied to the fourth capacitor 104. This integral error signal is used to control the output current provided by the second transistor 102 and the third transistor 105.

[0073] In this embodiment, the time-voltage circuit 120 is configured to be coupled to the voltage source 103 via a third transistor 105, the third transistor 105 having a source terminal configured to be coupled to the voltage source 103 and configured to receive a second error signal INT. dn INT up The time-voltage circuit 120 includes a gate terminal for the control signal and a drain terminal configured to provide supply current to the first capacitor 121. In this embodiment, the time-voltage circuit 120 also includes a demultiplexer 126 configured to provide supply current to the first capacitor 121 or a reference voltage terminal 124 (e.g., ground). The demultiplexer 126 is controlled by a first error signal PROP. dn Control, so that when the first error signal PROP dn When the voltage is low, the charge from voltage source 103 is guided through third transistor 105 and demultiplexer 126 to the reference voltage terminal 124. When the first error signal PROP... dnWhen the voltage is high, the charge from voltage source 103 is directed through third transistor 105 and demultiplexer 126 to first capacitor 121. The source terminal of third transistor 105 is also coupled to a first terminal of fourth capacitor 104, and the gate terminal of second transistor 102 is also coupled to a second terminal of fourth capacitor 104. This arrangement is advantageous because fourth capacitor 104 acts as an integrator to convert the second error signal INT... up INT dn The voltage is integrated into an approximately constant voltage, which then controls the current supplied by the second transistor 102 and the third transistor 105. Controlling the current of the second transistor 102 (and thus the CCO current) using this voltage automatically generates the correct bias current for the CCO 101. By causing the third transistor 105 to generate a relative current of this CCO current for the time-voltage circuit 120, the bandwidth of the PLL circuit 100 becomes independent of the bias conditions of the CCO 101 (and therefore independent of the PVT). In some other embodiments, a constant current is supplied to the fourth capacitor 104 and / or a bias current is used to supply current to the first capacitor 121.

[0074] exist Figure 1 In the embodiment shown, the device further includes a controller 106 configured to respond to the first feedback signal FB. PROP The second feedback signal FB is provided to the first proportional component 111 and delayed. INT Provided to the second integrator 112. The delay may be based on the oscillating output signal F. CCO The predetermined number of oscillations or any other suitable time period.

[0075] The operation of device 100 and the signals generated by controller 106 will now be described. A frequency divider (or multiplier) applied to generate a feedback signal can be applied by the circuitry of controller 106. Therefore, the block labeled controller 106 can be considered as both a controller and a frequency divider, but for the sake of brevity, it will be referred to herein as a controller.

[0076] In some embodiments, for example Figure 1 In the illustrated embodiment, controller 106 may be configured to generate a reset signal to short-circuit the first capacitor 121 before controller 106 is configured to generate a sampling signal. In this embodiment, this is achieved by closing a reset switch 123 that connects the first capacitor to the reference voltage terminal 124. The sampling signal includes instructions for sampling an error signal, wherein the first charge pump circuit is configured, based on the received sampling signal, to sample the first error signal PROP during a first portion of the reference period. dnSampling is performed, as will be discussed below. In this embodiment, the sampling signal is used to close the sampling switch 125 to connect the second capacitor 122 to the first capacitor 121, thereby transferring the voltage on the first capacitor 122 to the second capacitor 122.

[0077] Following this, in the first error signal PROP dn During the pulse period, voltage source 103 is connected to first capacitor 121, and therefore the voltage of first capacitor 121 starts to rise from the reference voltage. As previously mentioned, the first error signal PROP dn Based on reference signal F ref With the first feedback signal FB PROP The difference between them, the first feedback signal FB PROP Based on the oscillation output signal F CCO In this embodiment, the first error signal PROP dn The pulse width represents this difference, and therefore the first error signal PROP dn The voltage across the first capacitor 121 at termination also represents this difference. In other embodiments, the first error signal PROP dn Some other suitable characteristics can represent the reference signal F ref With the first feedback signal FB PROP The difference between them, the first feedback signal FB PROP It is based on the oscillation output signal F CCO .

[0078] First error signal PROP dn After the pulse terminates, the voltage on the first capacitor 121 can be transferred to the second capacitor 122 by closing the sampling switch 125, thereby controlling the first error signal PROP. dn Sampling is performed. The sampled signal remains high for the remainder of the reference period until the first capacitor 121 is reset again by closing the reset switch 123. In this way, the sampled voltage on the second capacitor 122 can remain in a stable state until the first error signal PROP is sampled again. dn Sampling is performed to provide a uniform large current throughout the entire reference period.

[0079] In this embodiment, the input signal sent to CCO 101 is based on a first control current minus a second control current. It should be understood that, with relevant adjustments to the circuit topology, the input signal sent to CCO 101 can also be based on a first control current plus a second control current, or a second control current minus a first control current. For example, the second control current can alternatively be provided to CCO 101 in parallel with the second transistor 102, thereby contributing a small portion of the current to CCO 101. This alternative embodiment can provide reduced power consumption.

[0080] In this embodiment, the bandwidth of the PLL circuit 100 is proportionally operated and therefore fed (through the third transistor 105) to a scaled version of the first control current of the CCO 101 and C sc With C p The ratio between them is limited. Therefore, PLL circuit 100 is independent of first-order PVT.

[0081] In some embodiments, one or more additional charge pumps may be used. The additional charge pumps may be similar to... Figure 1 The charge pump may have different offsets and / or internal gains. For example, an additional charge pump may prolong the time error of measurable and subsequently control actions.

[0082] In some embodiments, the PLL circuit 100 may further include an additional capacitor 160 connected in parallel between the first end of the impedance circuits 133, 134, 135 and the second end of the impedance circuits 133, 134, 135.

[0083] Reference Figure 1 and Figure 2 Explanation throughout a single reference period Figure 1 The operation of the embodiment shown.

[0084] Figure 2 An example signal diagram representing multiple signals within a circuit according to an embodiment of the present invention is shown. In this embodiment, the reference voltage terminal 124 is grounded (zero volts). In this example, at F ref 244 and FB PROP Generate an intentional constant offset between 245 to generate PROP dn The pulse is 246, always greater than zero, and controls the proportional current in both directions. In other examples, the offset can be generated alternatively by adding a constant current to the fourth capacitor 104. Intentionally generating the offset not only simplifies the circuit but also provides linearization of the fractional PLL (by generating only an up or down pulse instead of both) without generating any reference penetration spurious.

[0085] During the initial portion of the reference cycle, as indicated herein, controller 106 sends a high reset signal 247 to reset switch 123, thereby closing reset switch 123 to short-circuit the first capacitor 121, thus setting the voltage Vp 250 on the first capacitor 121 to zero volts. Simultaneously, controller 106 sends a low sampling signal 248 to sampling switch 125, thereby opening sampling switch 125 and disconnecting the first capacitor 121 from the second capacitor 122.

[0086] After the voltage Vp 250 on the first capacitor 121 reaches zero volts, the controller sets the reset signal 247 low, which re-opens the reset switch 123 in the time-voltage circuit 120, preventing the first capacitor 121 from being short-circuited. The termination of the reset pulse can be triggered by any suitable means, such as after sufficient time has elapsed to set the voltage on the first capacitor 121 to zero volts, or by measuring the voltage on the first capacitor 121 to zero volts.

[0087] Next, the first proportional component 111 of the phase frequency detector 110 generates a first error signal PROP. dn 246, and the first error signal PROP dn 246 is supplied to the time-voltage circuit 120. See below for reference. Figure 2 In the described steady-state example, with FB INT Compared to 243, by using FB PROP 245 advances two clock cycles (in) Figure 2 The output signal F is generated by oscillation. CCO The two loops (251) are used to generate the phase shift. In this example, FB... PROP 245 is advanced by two clock cycles 251, but it should be understood that other advance lengths are possible, including zero. In other examples, a reference signal F is provided. ref Two versions of 244 are used, and these two versions are delayed relative to each other. In these examples, the same feedback signal can be used for both phase frequency detectors. That is, FB INT With Facebook PROP same.

[0088] Reference signal F ref The rising edge of the 244 defines the first error signal PROP. DN The falling edge of 246, and therefore PROP dn The pulse width of 246 represents the reference signal F. ref 244 and the first feedback signal FB PROP The difference between 245 and 245.

[0089] The time-voltage circuit 120 uses the first error signal PROP dn 246 directs charge from voltage source 103 through third transistor 105 and demultiplexer 126 to first capacitor 121. When the first error signal PROP... dn When 246 is high, the first capacitor 121 charges, so that when the first error signal PROP... dn 246 returns to low (i.e., at the first error signal PROP) dn After pulse 246 terminates, the voltage V on the first capacitor 121... p250 represents the reference signal F ref 244 and the first feedback signal FB PROP The difference between 245 and 245.

[0090] First error signal PROP dn After pulse 246 terminates, controller 106 sets sampling signal 248 high, which within the closed-time voltage circuit 120 connects the second capacitor 122 to the switch 125 of the first capacitor 121. Therefore, the voltage V across the second capacitor 122... s 249 becomes equal to (or, in other examples, based on) the voltage Vp250 across the first capacitor 121. Therefore, the voltage Vp250 across the second capacitor 122... s 249 represents the reference signal F ref 244 and the first feedback signal FB PROP The difference between 245 and 245. The voltage V across the second capacitor 122. s 249 can be referred to as a voltage signal and is supplied to the voltage-current circuit 130. In this embodiment, the sampling signal 248 remains high until the start of the next reference cycle initiated by the reset signal 247, but in other embodiments, the sampling signal 248 may remain high only long enough to provide a voltage signal to the voltage-current circuit 130.

[0091] Meanwhile, after two clock cycles, the reference signal F ref 244 and the second feedback signal FB INT 243 is provided to the second integrating component 112. It should be understood that, in other embodiments, a reference signal F may be provided. ref Two versions of 244 (one version for each component of phase frequency detector 110).

[0092] The second integrating element 112 of the phase-frequency detector 110 is based on the reference signal F ref 244 and the second feedback signal FB INT Integral of the difference between 243 to generate a component INT dn 241 and INT up The second error signal of 242. The second integration unit 112 of the phase frequency detector 110 will input the second error signal INT. dn 241, INT up 242 is provided to the gate of the second transistor 102, which, together with the fourth capacitor 104, controls the source voltage from the voltage source 103 to provide a first control current.

[0093] Voltage-current circuit 130 uses voltage followers 131 and 132 and a third capacitor 133 to convert the voltage signal into a second control current, which is subtracted from the first control current through circuit topology. The resulting current is supplied to CCO 101, which generates a tracking reference signal F. ref 244 oscillation output signal F CCO 251.

[0094] CCO 101 will oscillate and output signal F CCO 251 is provided to controller 106, which controls oscillation switches 134 and 135 for oscillating the connection of the third capacitor 133. Controller 106 generates a first feedback signal FB to be used in subsequent reference cycles. PROP 245 and second feedback signal FB INT 243.

[0095] In some embodiments, the PLL circuit 100 further includes an additional conventional proportional charge pump (not shown) configured to supply a third control current to the CCO 101. In these embodiments, the third control current is constant. Therefore, the input error range of the phase frequency detector is increased.

[0096] The PLL circuit 100 can be implemented in radio transceivers, computers, vehicles, inverters, or any other suitable electronic devices.

[0097] Unless a specific order is explicitly stated, the instructions and / or flowchart steps in the above figure can be executed in any order. Furthermore, those skilled in the art will recognize that while an example set of instructions / methods has been discussed, the material in this specification can be combined in various ways to generate other examples, and should be understood within the context provided in this specific embodiment.

[0098] In some example embodiments, the instruction set / method steps described above are implemented as functional and software instructions embodied in an executable instruction set implemented on a computer or a machine programmed and controlled with said executable instructions. Such instructions are loaded for execution on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, microcontroller, processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing device. A processor may refer to a single component or multiple components.

[0099] In other examples, the instruction sets / methods illustrated herein, along with their associated data and instructions, are stored in appropriate storage devices, which are implemented as one or more non-transitory machine- or computer-readable or computer-usable storage media. Such computer-readable or computer-usable storage media are considered part of an article (or article of manufacture). An article or article of manufacture may refer to any single or multiple components manufactured. One or more non-transitory machine- or computer-usable media as defined herein do not include signals, but such one or more media are capable of receiving and processing information from signals and / or other transient media.

[0100] Example embodiments of the materials discussed in this specification may be implemented, in whole or in part, via networks, computers, or data-based devices and / or services. These may include cloud, internet, intranet, mobile devices, desktop computers, processors, lookup tables, microcontrollers, consumer devices, information infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive limitations are provided.

[0101] In one example, one or more instructions or steps discussed herein are automated. The terms automation or automaticity (and similar variations) mean the use of computers and / or mechanical / electrical devices to control the operation of equipment, systems, and / or processes without human intervention, observation, effort, and / or decision-making.

[0102] It should be understood that any components that are alleged to be coupled may be directly or indirectly coupled or connected. In the case of indirect coupling, an additional component may be placed between the two components that are alleged to be coupled.

[0103] In this specification, exemplary embodiments have been presented based on a selected set of details. However, those skilled in the art will understand that many other exemplary embodiments, including different sets of these details, can be practiced. The appended claims are intended to cover all possible exemplary embodiments.

Claims

1. An apparatus, comprising: comprises: a phase-locked loop circuit, the phase-locked loop circuit comprising: input configured to receive an oscillating reference signal F having a reference period ref ; a current-controlled oscillator (CCO) configured to generate an oscillating output signal based on an input signal; an error detector configured to generate one or more error signals based on a phase difference between the reference signal and at least one of one or more feedback signals, wherein the one or more feedback signals are based on the oscillation output signal F CCO ; and a charge pump circuit configured to receive at least a first error signal of the one or more error signals, determine a voltage indicative of a duration of the first error signal during a first portion of the reference period, and provide a control current to the CCO for at least a remaining portion of the reference period, wherein the control current comprises at least a portion of the input signal to the CCO and is based on the determined voltage.

2. The apparatus of claim 1, wherein, the error detector is a phase frequency detector, the phase frequency detector comprising: a first proportional component configured to generate the first error signal of the one or more error signals based on the difference between the reference signal and a first feedback signal of the one or more feedback signals that is based on the oscillating output signal; and a second integral component configured to generate a second error signal of the one or more error signals based on an integral of the difference between the reference signal and a second feedback signal of the one or more feedback signals that is based on the oscillating output signal.

3. The apparatus of claim 2, wherein, the charge pump circuit comprises a first charge pump circuit and the control current comprises a first control current, and whereby the first charge pump circuit is configured to receive the first error signal, determine the voltage indicative of the duration of the first error signal during the first portion of the reference period, and provide the first control current comprising at least a portion of the input signal to the CCO for at least the remaining portion of the reference period based on the determined voltage; and wherein the charge pump circuit additionally comprises: a second charge pump circuit configured to generate a control signal based on the second error signal; and a current source configured to generate a second control current based on the control signal; wherein the input signal to the CCO is based on the first control current and the second control current.

4. The apparatus of any preceding claim, wherein, the charge pump circuit comprises: a time-to-voltage circuit configured to convert at least one error signal of the one or more error signals representing the phase difference between the reference signal and the one or more feedback signals to a voltage signal; and a voltage-to-current circuit configured to receive the voltage signal from the time-to-voltage circuit and convert the voltage signal to the control current.

5. The apparatus of claim 3, wherein, the first charge pump circuit comprises: a time-to-voltage circuit configured to convert the first error signal to a voltage signal; and a voltage-to-current circuit configured to receive the voltage signal from the time-to-voltage circuit and convert the voltage signal to the control current; wherein: The time-to-voltage circuit includes a first capacitor, and the time-to-voltage circuit is configured such that, upon providing the first error signal to the time-to-voltage circuit, the first capacitor is charged by a current induced by a source voltage; The time-to-voltage circuit includes a second capacitor, and wherein the charge pump circuit is configured to sample the error signal during the first portion of the reference period through the time-to-voltage circuit, the time-to-voltage circuit configured to couple the first capacitor to the second capacitor such that the second capacitor is charged by the first capacitor and a voltage on the second capacitor defines the voltage signal; The voltage-to-current circuit includes a voltage follower configured to receive the voltage signal from the second capacitor and control a voltage applied to an impedance circuit based on the voltage signal, The impedance circuit includes a switched capacitor circuit including a third capacitor that switches at a frequency of the oscillating output signal, and The control current is based on a voltage on the impedance circuit.

6. The apparatus of claim 5, wherein, The first capacitor and the third capacitor are of the same type, and a ratio of capacitances between the first capacitor and the third capacitor is programmable.

7. The apparatus of claim 5 or claim 6, wherein, The voltage follower includes a first amplifier and a first transistor, wherein an output of the first amplifier is coupled to a gate of the first transistor, a non-inverting input of the first amplifier is coupled to the second capacitor, an inverting input of the first amplifier is coupled to a source terminal of the first transistor, the source terminal of the first transistor is coupled to a first terminal of the impedance circuit, a second terminal of the impedance circuit is configured to be coupled to a reference voltage, and wherein a drain terminal of the first transistor is coupled to receive a portion of the second control current.

8. The apparatus of claim 7, wherein, The current source includes a second transistor having a source terminal configured to be coupled to a voltage source, a gate terminal configured to receive the control signal based on the second error signal, and a drain terminal configured to provide the second control current for controlling the CCO; wherein the source terminal of the second transistor is also coupled to a first terminal of a fourth capacitor, and the gate terminal of the second transistor is also coupled to a second terminal of the fourth capacitor; and wherein the time-to-voltage circuit is configured to be coupled to the voltage source via a third transistor having a source terminal configured to be coupled to the voltage source, a gate terminal configured to receive the control signal based on the second error signal, and a drain terminal configured to provide a supply current to the first capacitor, wherein the source terminal of the third transistor is also coupled to the first terminal of the fourth capacitor, and the gate terminal of the second transistor is also coupled to the second terminal of the fourth capacitor.

9. The apparatus of claim 2, wherein, Further comprising a controller configured to advance providing the first feedback signal to the first proportional component relative to providing the second feedback signal to the second integrating component.

10. An electronic device, comprising: The device according to any one of the preceding claims. The device according to any one of the preceding claims. The device according to any one of the preceding claims

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