Preparation method of semiconductor device

Abstract

The invention relates to a preparation method of a semiconductor device. According to the method, the patterned oxide layer comprising the silicon dioxide layer and the boron phosphosilicate glass layer is subjected to reflux treatment, so that the corner at the position of the contact hole becomes smooth, the geometric obstacle of metal layer deposition is eliminated, and a foundation is laid for uniform deposition of the metal layer. Meanwhile, reverse sputtering and circular treatment of the primary metal layer are adopted, uniform deposition of the metal layer along the hole wall is promoted, the problem that holes and gaps exist in the metal layer due to the fact that the contact hole with the high aspect ratio is sealed in advance is effectively solved, and then the thickness uniformity of the metal layer is effectively improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor device. Background Technology

[0002] In semiconductor devices, an isolation dielectric (such as an oxide layer) is typically fabricated on the surface of a semiconductor substrate and then patterned to form a patterned isolation dielectric with contact holes. A metal layer is then deposited on the surface of the patterned isolation dielectric. During this process, because the patterned isolation dielectric often has near-90° corners at the contact hole locations, conventional methods struggle to achieve a uniform metal layer thickness at these corners, thus affecting device performance. For example… Figure 1 As shown, this is a metal layer obtained by a conventional method, in which the patterned insulating medium has a near 90° corner at the contact hole location, resulting in poor uniformity of the metal layer thickness. Summary of the Invention

[0003] Based on this, this application provides a method for fabricating a semiconductor device that can improve the uniformity of the metal layer thickness at the contact hole location.

[0004] A method for fabricating a semiconductor device includes the following steps:

[0005] S1: An oxide layer is prepared on the surface of a substrate, the oxide layer comprising a silicon dioxide layer and a borosilicate glass layer sequentially stacked on the surface of the substrate;

[0006] S2: The oxide layer is etched to form a patterned oxide layer with contact holes;

[0007] S3: The patterned oxide layer is refluxed under a protective gas atmosphere to prepare a reflux product; the reflux temperature is 800℃~1000℃ and the reflux time is 20min~40min.

[0008] S4: Perform backsputtering treatment on the patterned oxide layer surface of the reflow product to prepare a backsputtered product; the power of the backsputtering treatment is 400W~600W, and the time of the backsputtering treatment is 4min~6min;

[0009] S5: Prepare a primary metal layer on the patterned oxide layer surface of the anti-sputtered product; the thickness of the primary metal layer is 800 nm to 1000 nm;

[0010] S6: Repeat S4 and S5 to thicken the primary metal layer in order to prepare a target metal layer with a target thickness on the patterned oxide layer surface of the anti-sputtered product.

[0011] In some embodiments, the thickness of the silicon dioxide layer is 100 nm to 500 nm.

[0012] In some embodiments, the thickness of the borophosphosilicate glass layer is 800 nm to 1200 nm.

[0013] In some embodiments, the substrate includes a silicon carbide substrate.

[0014] In some implementations, S1 and S2 may also include:

[0015] S11: Under a protective gas atmosphere, the oxide layer is densified at a temperature of 800℃~1000℃ for a time of 20min~40min.

[0016] In some embodiments, the oxide layer is prepared on the substrate surface using plasma-enhanced chemical vapor deposition in S1.

[0017] In some embodiments, photolithography is used to etch the oxide layer in S2.

[0018] In some implementations, S3 and S4 may also include:

[0019] S31: Rinse the reflux product with deionized water to remove residual metal ions from the surface of the reflux product.

[0020] In some implementations, S4 and S5 are repeated 2 to 4 times.

[0021] In some embodiments, the target thickness of the target metal layer is 2000 nm to 4000 nm.

[0022] In the aforementioned semiconductor device fabrication method, reflowing the patterned oxide layer, including a silicon dioxide layer and a borosilicate glass layer, smooths the corners at the contact hole locations, eliminating geometric obstacles to metal layer deposition and laying the foundation for uniform metal layer deposition. Simultaneously, reverse sputtering and primary metal layer recycling promote uniform metal layer deposition along the hole walls, effectively addressing the issue of voids and gaps in the metal layer of high aspect ratio contact holes caused by premature sealing, thereby significantly improving the uniformity of the metal layer thickness. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application and to more completely understand this application and its beneficial effects, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a metal layer obtained using traditional techniques.

[0025] Figure 2 This is a schematic diagram of the product structure in one step of the semiconductor device fabrication method according to an embodiment of this application.

[0026] Figure 3 This is a schematic diagram of the product structure in another step of the semiconductor device fabrication method according to one embodiment of this application.

[0027] Figure 4 This is a schematic diagram of the product structure in another step of the semiconductor device fabrication method according to one embodiment of this application.

[0028] Figure 5 This is a schematic diagram of the product structure in another step of the semiconductor device fabrication method according to one embodiment of this application.

[0029] Figure 6 This is a schematic diagram of the product structure in another step of the semiconductor device fabrication method according to one embodiment of this application.

[0030] Figure 7 This is a schematic diagram of the product structure in another step of the semiconductor device fabrication method according to one embodiment of this application.

[0031] Figure 8 This is a schematic diagram of the product structure in another step of the semiconductor device fabrication method according to one embodiment of this application.

[0032] Figure 9 This is a deposition diagram of the primary metal layer during the fabrication of the semiconductor device in Example 1 of this application.

[0033] Explanation of markings in the diagram:

[0034] 10. Substrate; 20. Oxide layer; 201. Contact hole; 30. Photoresist; 40. Target metal layer. Detailed Implementation

[0035] The present application will be further described in detail below with reference to the embodiments and examples. It should be understood that these embodiments and examples are only used to illustrate the present application and are not intended to limit the scope of the present application. The purpose of providing these embodiments and examples is to make the disclosure of the present application more thorough and comprehensive.

[0036] It should also be understood that this application can be implemented in many different forms and is not limited to the embodiments and examples described herein. Those skilled in the art can make various alterations or modifications without departing from the spirit of this application, and the resulting equivalent forms also fall within the protection scope of this application. For example, features described or illustrated as part of one embodiment can be combined in a suitable manner in another embodiment to produce new embodiments. Furthermore, numerous specific details are set forth in the following description to provide a fuller understanding of this application; it should be understood that this application can be implemented without one or more of these details.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for descriptive purposes only and is not intended to be limiting of the application.

[0038] Unless otherwise stated or in case of contradiction, the terms or phrases used herein shall have the following meanings:

[0039] In this application, the terms "multiple", "various", "multiple times", etc., unless otherwise specified, refer to a quantity greater than or equal to 2. For example, "one or more" means one or more than or equal to two.

[0040] The terms “combinations of,” “any combination of,” and “any combination of” used in this article include all suitable combinations of any two or more of the listed items.

[0041] In this document, the term "suitable" as used in "suitable combination", "suitable method", "any suitable method", etc., refers to the ability to implement the technical solution of this application, solve the technical problem of this application, and achieve the expected technical effect of this application.

[0042] In this document, terms such as "preferred," "better," "more suitable," and "ideal" are merely descriptions of more effective implementation methods or embodiments, and should be understood not to limit the scope of protection of this application. If multiple "preferred" terms appear in a technical solution, unless otherwise specified and there are no contradictions or mutual constraints, each "preferred" term shall be independent.

[0043] In this application, terms such as "further," "even further," and "particularly" are used to describe purposes and indicate differences in content, but should not be construed as limiting the scope of protection of this application.

[0044] In this application, "optionally," "optionally," and "optional" mean that something is optional, that is, it means that it is selected from either "with" or "without." If there are multiple "optional" entries in a technical solution, unless otherwise specified, and there are no contradictions or mutual constraints, each "optional" entry shall be independent.

[0045] In this application, the terms "first aspect," "second aspect," "third aspect," "fourth aspect," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or quantity, nor should they be construed as implicitly indicating the importance or quantity of the indicated technical features. Moreover, "first," "second," "third," "fourth," etc., serve only as a non-exhaustive enumeration and should be understood not to constitute a closed limitation on quantity.

[0046] In this application, the technical features described in an open-ended manner include both closed technical solutions consisting of the listed features and open technical solutions that include the listed features.

[0047] In this application, when numerical intervals (i.e., numerical ranges) are mentioned, unless otherwise specified, the distribution of selectable numerical values ​​within the numerical interval is considered continuous, and includes the two endpoints of the numerical interval (i.e., the minimum and maximum values), as well as every numerical value between these two endpoints. Unless otherwise specified, when a numerical interval refers only to integers within that numerical interval, it includes the two endpoint integers of the numerical range, as well as every integer between the two endpoints, which is equivalent to directly listing every integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical ranges disclosed herein should be understood to include any and all subranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, percentage, ratio, etc. The term "numerical interval" can be broadly included to include numerical interval types such as percentage intervals, ratio intervals, and proportion intervals.

[0048] Unless otherwise specified, the temperature parameters in this application are permitted to be either constant-temperature treatment or variations within a certain temperature range. It should be understood that the constant-temperature treatment allows temperature fluctuations within the precision range of the instrument control, such as ±5℃, ±4℃, ±3℃, ±2℃, or ±1℃.

[0049] In this application, the terms "room temperature" or "normal temperature" generally refer to 4℃ to 35℃, for example, 20℃ ± 5℃. In some embodiments of this application, "room temperature" or "normal temperature" refers to 10℃ to 30℃. In some embodiments of this application, "room temperature" or "normal temperature" refers to 20℃ to 30℃.

[0050] In this application, if the unit of a data range is only followed by the right endpoint, it indicates that the units of the left and right endpoints are the same. For example, 3~5 h means that the units of the left endpoint "3" and the right endpoint "5" are both h (hours).

[0051] The mass or weight of the relevant components mentioned in the embodiments of this application can refer not only to the specific content of each component, but also to the proportional relationship of mass or weight between the components. Therefore, any scaling up or down of the content of the relevant components according to the embodiments of this application is within the scope disclosed in the embodiments of this application. Specifically, the mass or weight mentioned in the embodiments of this application can be units known in the chemical industry, such as μg, mg, g, and kg.

[0052] One embodiment of this application provides a method for fabricating a semiconductor device, comprising the following steps:

[0053] S0: Clean the substrate.

[0054] Optionally, the substrate surface is cleaned using solution No. 3, solution No. 1, and hydrofluoric acid, respectively. The substrate 10 obtained after cleaning is shown in Figure 10. Figure 2 As shown.

[0055] It is understandable that solutions No. 3 and No. 1 are conventional cleaning solutions in this field.

[0056] In some embodiments, the substrate includes a wafer.

[0057] In some embodiments, the substrate includes a silicon carbide substrate.

[0058] S1: An oxide layer is prepared on the surface of a substrate. The oxide layer comprises a silicon dioxide layer and a borosilicate glass layer sequentially stacked on the substrate surface. The product structure after the oxide layer is prepared is as follows. Figure 3 As shown. Figure 3 In this product, there is a substrate 10 and an oxide layer 20 located on the surface of the substrate 10.

[0059] Optionally, the silicon dioxide layer is an undoped silicon dioxide layer.

[0060] In some embodiments, plasma-enhanced chemical vapor deposition (PECVD) is used in S1 to prepare an oxide layer on the substrate surface. A uniformly thick oxide layer can be obtained through PCVD.

[0061] Optionally, in S1, a silicon dioxide layer and a borosilicate glass layer are sequentially deposited on the substrate surface by plasma-enhanced chemical vapor deposition.

[0062] In some embodiments, the thickness of the silicon dioxide layer is 100nm to 500nm. For example, the thickness of the silicon dioxide layer can be 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, or any value within the range of any two of the above values.

[0063] In some embodiments, the thickness of the borophosphosilicate glass layer is 800 nm to 1200 nm. For example, the thickness of the borophosphosilicate glass layer can be 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, 1050 nm, 1100 nm, 1150 nm, 1200 nm, or any value within the range of any two of the above values.

[0064] S11: Under a protective gas atmosphere, the oxide layer is densified at a temperature of 800℃~1000℃ for a time of 20min~40min.

[0065] Optionally, the densification process is carried out in the furnace tube.

[0066] In some implementations, during the densification process, the protective gas atmosphere is in the nitrogen range.

[0067] Furthermore, during the densification process, nitrogen is used for purging.

[0068] As an example of a densification temperature, it can be 800℃, 820℃, 850℃, 880℃, 900℃, 900℃, 920℃, 950℃, 980℃, 1000℃, or any value within the range of any two of the above values.

[0069] As an example of the densification time, it can be 20 min, 22 min, 25 min, 28 min, 30 min, 30 min, 32 min, 35 min, 38 min, 40 min, or any value within the range of any two of the above values.

[0070] S2: The oxide layer is etched to form a patterned oxide layer with contact holes.

[0071] In some embodiments, photolithography is used to etch the oxide layer in S2.

[0072] Optionally, an etching mask is formed on the oxide layer surface using photolithography. Mask fabrication begins with a photoresist coating process, where a uniformly thick photoresist layer is coated onto the oxide layer surface. Then, the photoresist is exposed and developed using photolithography to obtain the corresponding mask pattern. Before the photoresist coating process, a hexamethyldisilazane (HMDS) tackifier can be coated onto the oxide layer surface to enhance the adhesion between the photoresist and the oxide layer interface. After coating, the wafer is baked in an oven, followed by exposure using a stepper lithography machine. The exposed wafer is then developed using a photoresist coating and developing equipment to obtain the corresponding mask pattern. The resulting product structure is as follows: Figure 4 As shown. Figure 4 In this process, a mask pattern is formed on the surface of the oxide layer 20 by photoresist 30.

[0073] Under the protection of the mask pattern, the oxide layer is dry-etched to transfer the mask pattern to the substrate surface, thereby forming a patterned oxide layer with contact holes. Optionally, during etching, the borosilicate glass layer and the silicon dioxide layer are etched sequentially. The product structure after etching is as follows. Figure 5 A patterned oxide layer 20 with contact holes 201 is formed through etching.

[0074] In some embodiments, after photolithography, residual photoresist is removed by sequentially cleaning with solution No. 3 and solution No. 1. Optionally, a semi-automatic acid pickling machine is used to remove the photoresist. The product structure after photoresist removal is as follows. Figure 6 As shown.

[0075] S3: The patterned oxide layer is reflowed under a protective gas atmosphere to prepare a reflow product. The reflow temperature is 800℃~1000℃, and the reflow time is 20min~40min. Reflow treatment changes the near 90° angle between the bottom of the contact hole and the top of the oxide layer into a rounded corner, creating a smoother path for uniform metal deposition and fundamentally improving the metal layer's filling ability. The product structure after reflow treatment is as follows... Figure 7 As shown. By Figure 6 and Figure 7 It can be seen that the reflow process can change the near 90° corner of the connection between the bottom of the contact hole 201 and the top of the oxide layer 20 into a smooth arc corner.

[0076] Optionally, a nitrogen atmosphere is used as the protective gas atmosphere for the reflux treatment. During the reflux treatment process, the system is kept under nitrogen purging.

[0077] Optionally, the reflux temperature can be 800℃, 820℃, 850℃, 880℃, 900℃, 900℃, 920℃, 950℃, 980℃, 1000℃, or any value within the range of any two of the above values.

[0078] Optionally, the reflux processing time can be 20 min, 22 min, 25 min, 28 min, 30 min, 30 min, 32 min, 35 min, 38 min, 40 min, or any value within the range of any two of the above values.

[0079] In some embodiments, S3 and S4 further include: S31: rinsing the reflux product with deionized water to remove residual metal ions on the surface of the reflux product.

[0080] S4: The patterned oxide layer surface of the reflow product is subjected to backsputtering treatment to prepare a backsputtered product. The backsputtering power is 400W~600W, and the backsputtering time is 4min~6min. Backsputtering not only cleans the interface but also increases the surface energy through ion bombardment, enabling subsequently deposited metal atoms to form a stronger bond, greatly enhancing the adhesion of the metal layer. By ensuring a clean, fully filled, and firmly adhered contact interface, various potential failure mechanisms can be effectively eliminated. The resulting device has more consistent electrical parameters, lower thermal resistance, and longer lifespan, thus significantly improving device yield and long-term reliability.

[0081] In some embodiments, the gas atmosphere for the backsputtering process is an argon atmosphere. Optionally, the argon flow rate is 50 sccm-300 sccm. For example, the argon flow rate can be 50 sccm, 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, or any value within the range of any two of the above values.

[0082] In some implementations, the power of the anti-sputtering process can be 400W, 450W, 500W, 550W, 600W, or any value within the range of any two of the above values.

[0083] In some implementations, the anti-sputtering process time can be 4 min, 5 min, 6 min, or any value within the range of any two of the above values.

[0084] S5: Prepare a primary metal layer on the patterned oxide layer surface of the anti-sputtered product; the thickness of the primary metal layer is 800nm~1000nm. Understandably, a primary metal layer is also formed on the bottom and walls of the contact holes.

[0085] Alternatively, the primary metal layer can be prepared by sputtering or vapor deposition.

[0086] Optionally, the thickness of the primary metal layer can be 800nm, 850nm, 900nm, 950nm, 1000nm, or any value within the range of any two of the above values.

[0087] S6: Repeat S4 and S5 to thicken the primary metal layer, thus preparing a target metal layer of the desired thickness on the patterned oxide layer surface of the anti-sputtered product. Cyclic anti-sputtering bombardment of the primary metal layer allows for minor etching of the bottom and walls of the contact holes, preventing premature sealing above the contact holes and creating a smoother path for uniform metal deposition. Simultaneously, the rounded design of the oxide layer fundamentally improves the metal filling capability of the contact holes. The resulting product structure is as follows: Figure 8 As shown. By Figure 8 It can be seen that the target metal layer 7 is uniformly attached to the surface of the oxide layer 20.

[0088] In some implementations, S4 and S5 are repeated 2 to 4 times. For example, S4 and S5 can be repeated 2, 3, or 4 times.

[0089] It is understandable that repeating S4 and S5 once means that S4 and S5 are each repeated once. Repeating S4 and S5 twice means that S4 and S5 are each repeated twice. The meaning of the number of repetitions of S4 and S5 can be deduced similarly.

[0090] In some implementations, the target thickness of the target metal layer is 2000 nm to 4000 nm. For example, the target thickness of the target metal layer can be 2000 nm, 2500 nm, 3000 nm, 3500 nm, 4000 nm, or any value within the range of any two of the above values.

[0091] In some implementations, the target metal layer is a Ti layer.

[0092] In the aforementioned semiconductor device fabrication method, reflowing the patterned oxide layer, including a silicon dioxide layer and a borosilicate glass layer, smooths the corners at the contact hole locations, eliminating geometric obstacles to metal layer deposition and laying the foundation for uniform metal layer deposition. Simultaneously, reverse sputtering and primary metal layer recycling promote uniform metal layer deposition along the hole walls, effectively addressing the issue of voids and gaps in the metal layer of high aspect ratio contact holes caused by premature sealing, thereby significantly improving the uniformity of the metal layer thickness.

[0093] Another embodiment of this application provides a semiconductor device. This semiconductor device is prepared by the method described above.

[0094] Example 1

[0095] The method for fabricating the semiconductor device in this embodiment includes the following steps:

[0096] S0: The surface of the silicon carbide substrate was cleaned using liquid No. 3, liquid No. 1, and hydrofluoric acid, respectively.

[0097] S1: An oxide layer is obtained by sequentially depositing a silicon dioxide layer and a borosilicate glass layer on the substrate surface using plasma-enhanced chemical vapor deposition. The oxide layer comprises a silicon dioxide layer and a borosilicate glass layer sequentially stacked on the substrate surface. The thickness of the silicon dioxide layer is 300 nm. The thickness of the borosilicate glass layer is 1000 nm.

[0098] S11: Under a protective gas atmosphere of nitrogen purging, the oxide layer is densified at a temperature of 900℃ for 30 minutes.

[0099] S2: The oxide layer is etched using photolithography to form a patterned oxide layer with contact holes. After photolithography, a semi-automatic acid cleaning machine is used to sequentially clean and remove residual photoresist using solution No. 3 and solution No. 1.

[0100] S3: The patterned oxide layer is refluxed under a protective gas atmosphere of nitrogen purging to prepare a reflux product; the reflux temperature is 900℃ and the reflux time is 30min.

[0101] S31: Use deionized water to rinse the returned product to remove residual metal ions from the surface of the returned product.

[0102] S4: The patterned oxide layer surface of the reflow product is subjected to backsputtering treatment to prepare a backsputtered product; the gas atmosphere for backsputtering treatment is argon atmosphere, and the argon flow rate is 150 sccm. The power of backsputtering treatment is 500W, and the backsputtering treatment time is 5min.

[0103] S5: A primary metal layer is fabricated on the patterned oxide layer surface of the anti-sputtered product by sputtering. The primary metal layer is a Ti layer. The thickness of the primary metal layer is approximately 1000 nm. The primary metal layer is as follows... Figure 9 As shown. By Figure 9 It can be seen that the connection between the bottom of the contact hole and the top of the oxide layer is a rounded corner, and the thickness of the primary metal layer is relatively uniform.

[0104] S6: Repeat steps S4 and S5 four times to thicken the primary metal layer, thereby preparing a target metal layer with the target thickness on the patterned oxide layer surface of the anti-sputtered product. The target thickness of the target metal layer is approximately 4000 nm.

[0105] Depend on Figure 9 As can be seen, the primary metal layer in this embodiment has a uniform thickness. By repeating S4 and S5, a target metal layer with uniform thickness can be obtained.

[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The embodiments described above are merely illustrative of several implementation methods of this application, intended to facilitate a detailed understanding of the technical solutions of this application, but should not be construed as limiting the scope of protection of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. It should be understood that technical solutions obtained by those skilled in the art based on the technical solutions provided in this application through logical analysis, reasoning, or limited experimentation are all within the scope of protection of the appended claims. Therefore, the scope of protection of this patent application should be determined by the content of the appended claims, and the specification can be used to interpret the content of the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: S1: An oxide layer is prepared on the surface of a substrate, the oxide layer comprising a silicon dioxide layer and a borosilicate glass layer sequentially stacked on the surface of the substrate; S2: The oxide layer is etched to form a patterned oxide layer with contact holes; S3: The patterned oxide layer is refluxed under a protective gas atmosphere to prepare a reflux product; the reflux temperature is 800℃~1000℃ and the reflux time is 20min~40min. S4: Perform backsputtering treatment on the patterned oxide layer surface of the reflow product to prepare a backsputtered product; the power of the backsputtering treatment is 400W~600W, and the time of the backsputtering treatment is 4min~6min; S5: Prepare a primary metal layer on the patterned oxide layer surface of the anti-sputtered product; the thickness of the primary metal layer is 800 nm to 1000 nm; S6: Repeat S4 and S5 to thicken the primary metal layer in order to prepare a target metal layer with a target thickness on the patterned oxide layer surface of the anti-sputtered product.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thickness of the silicon dioxide layer is 100nm~500nm.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thickness of the borophosphosilicate glass layer is 800nm~1200nm.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The substrate includes a silicon carbide substrate.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, Between S1 and S2, there is also: S11: Under a protective gas atmosphere, the oxide layer is densified at a temperature of 800℃~1000℃ for a time of 20min~40min.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, In S1, the oxide layer is prepared on the surface of the substrate using plasma-enhanced chemical vapor deposition.

7. The method for fabricating a semiconductor device according to any one of claims 1 to 6, characterized in that, In S2, the oxide layer is etched using photolithography.

8. The method for fabricating a semiconductor device according to any one of claims 1 to 6, characterized in that, Between S3 and S4, there is also: S31: Rinse the reflux product with deionized water to remove residual metal ions from the surface of the reflux product.

9. The method for fabricating a semiconductor device according to any one of claims 1 to 6, characterized in that, S4 and S5 are repeated 2 to 4 times.

10. The method for fabricating a semiconductor device according to any one of claims 1 to 6, characterized in that, The target thickness of the target metal layer is 2000nm~4000nm.

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