A high-precision low-delay on-chip ripple compensation circuit

Abstract

The application discloses a high-precision low-delay on-chip ripple compensation circuit and belongs to the technical field of integrated circuit design.The on-chip ripple compensation circuit comprises PMOS tubes P1-P9, NMOS tubes N1-N5, resistors R1-R6 and capacitors C1-C3.In the on-chip ripple compensation circuit, one end of the resistor R1 is connected to a node SW, the other end of the resistor R1 is connected to one end of the resistor R2 and R3, and the connection position is a node vs10;the other end of the resistor R2 is connected to the ground VSS, the other end of the resistor R3 is connected to one end of the capacitor C1 and the gate of the PMOS tube P9, and the connection position is a node vlpf;the other end of the capacitor C1 is connected to the ground VSS, the drain of the PMOS tube P9 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the ground VSS.The link path of the on-chip ripple compensation circuit has only four levels, and the phase delay is shortened;two-stage filtering is performed in the last stage, the alternating current is extracted in the output stage, flows into the resistor and is converted into voltage, all the MOS tubes can work in the saturation region, zero DC error is achieved, and the precision of the ripple compensation is improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically relating to a high-precision, low-latency on-chip ripple compensation circuit. Background Technology

[0002] Constant on-time control mode is widely used in BUCK converters due to its fast transient response and simple loop compensation. However, in applications with low equivalent series resistance, such as ceramic output capacitors, the phase of the output ripple voltage will lag significantly, leading to loop instability. Therefore, an on-chip ripple compensation circuit is needed to inject a ripple signal in phase with the inductor current into the feedback voltage.

[0003] Traditional COT (constant on time) BUCK on-chip ripple compensation circuits all have phase delay and residual DC error problems.

[0004] Therefore, there is a need to provide a new on-chip ripple compensation circuit that can achieve zero DC error and improve the accuracy of ripple compensation, so as to solve the problems existing in the traditional COT BUCK on-chip ripple compensation circuit. Summary of the Invention

[0005] The purpose of this invention is to provide a high-precision, low-delay on-chip ripple compensation circuit. The AC quantity is extracted only at the output stage, and all MOSFETs have relatively large bias currents, making it easy for them to operate in the saturation region. Therefore, current mismatch is small, improving accuracy. Furthermore, it does not need to retain the DC deviation of the AC current, so no DC error is introduced into the output, further improving output voltage accuracy and solving the problems mentioned in the background section.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a high-precision, low-delay on-chip ripple compensation circuit, wherein the on-chip ripple compensation circuit includes PMOS transistors P1~P9, NMOS transistors N1~N5, resistors R1~R6, and capacitors C1~C3;

[0007] In the ripple compensation circuit of this chip, one end of resistor R1 is connected to node SW, and the other end is connected to one end of resistors R2 and R3, with the connection point being node vs10; the other end of resistor R2 is grounded to VSS, and the other end of resistor R3 is connected to one end of capacitor C1 and the gate of PMOS transistor P9, with the connection point being node vlpf; the other end of capacitor C1 is grounded to VSS, and the drain of PMOS transistor P9 is connected to one end of resistor R4, with the other end of resistor R4 grounded to VSS.

[0008] The source of PMOS transistor P9 is connected to the gate of NMOS transistor N1 and the drain of PMOS transistor P2; the gate of PMOS transistor P2 is connected to the gate and drain of PMOS transistor P1 and is connected to the bias current ibias; the source of NMOS transistor N1 is connected to one end of resistor R6, and the other end of resistor R6 is grounded to VSS; the drain of NMOS transistor N1 is connected to one end of resistor R5 and the gates of PMOS transistors P4, P6, and P8; the other end of resistor R5 is connected to the drain of PMOS transistor P4 and the gates of PMOS transistors P3, P5, and P7.

[0009] The source of PMOS transistor P4 is connected to the drain of PMOS transistor P3; the source of PMOS transistor P6 is connected to the drain of PMOS transistor P5; the drain of PMOS transistor P6 is connected to one end of resistor R7, the gates of NMOS transistors N2 and N4, and one end of capacitor C3, forming node V2; the other end of resistor R7 is connected to the drain of NMOS transistor N2, the gates of NMOS transistors N3 and N5, and one end of capacitor C2, forming node V1; the sources of NMOS transistors N3 and N5 are grounded to VSS; the other ends of capacitors C2 and C3 are grounded to VSS.

[0010] The source of NMOS transistor N2 is connected to the drain of NMOS transistor N3, the source of NMOS transistor N4, and the drain of NMOS transistor N5. The drain of NMOS transistor N4 is connected to the drain of PMOS transistor P8 and one end of resistor Rac, forming node vsum. The drain of PMOS transistor P8 is connected to the source of PMOS transistor P7. The other end of resistor Rac is connected to one end of output feedback resistors Rf1 and Rf2, forming feedback node vfb. The other end of output feedback resistor Rf2 is grounded, and the other end of output feedback resistor Rf1 is connected to the output VOUT of BUCK.

[0011] Preferably, the sources of the PMOS transistors P1, P2, P3, P5, and P7 are connected to the power supply voltage VDD.

[0012] Preferably, the on-chip ripple compensation circuit includes an AC current source i1, a DC current source i2, a resistor Rac, and output feedback resistors Rf1 and Rf2;

[0013] One end of AC current source i1 is connected to the power supply voltage VDD, and the other end of AC current source i1 is connected to one end of DC current source i2 and one end of resistor Rac, with the connection node being vsum. The other end of DC current source i2 is grounded to VSS.

[0014] The other end of resistor Rac is connected to one end of output feedback resistors Rf1 and Rf2, with the connection node being vfb; the other end of output feedback resistor Rf1 is connected to the output VOUT of BUCK, and the other end of output feedback resistor Rf2 is grounded to VSS.

[0015] Meanwhile, this invention proposes a COT BUCK circuit, which includes an input VIN, a node SW, a feedback node vfb, a comparator, an output VOUT, and a high-precision, low-delay on-chip ripple compensation circuit.

[0016] Preferably, the on-chip ripple compensation circuit includes a ripple compensation circuit and a summing circuit; wherein, the input of the ripple compensation circuit is connected to node SW, and the output is connected to one input of the summing circuit; the other input of the summing circuit is connected to feedback node vfb, and the output is node vsum, which is connected to the inverting input of the comparator.

[0017] Compared with the prior art, the beneficial effects of the present invention are:

[0018] The present invention provides a low-latency, high-precision ripple compensation circuit with only four stages in its link path, which shortens the phase delay. The two-stage filtering in the last stage extracts the AC current from the output stage, which flows into the resistor and is converted into voltage. All MOSFETs can easily operate in the saturation region, achieving zero DC error and improving the accuracy of ripple compensation. Attached Figure Description

[0019] Figure 1 This is the overall COT BUCK circuit block diagram.

[0020] Figure 2 This is the equivalent model circuit diagram of the on-chip ripple compensation circuit.

[0021] Figure 3 This is a circuit diagram of the on-chip ripple compensation circuit of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0023] The traditional method of extracting alternating current and then converting it to voltage results in a large current mismatch because the extracted alternating current is relatively small, usually in the hundreds of nanoamps range, and the MOSFET typically operates in the threshold region.

[0024] Furthermore, if a large two-stage filter or a three-stage filter is used to obtain pure DC current, the extracted AC current will be both positive and negative, leading to a greater mismatch in the MOSFET. To avoid obtaining both positive and negative AC current, the two-stage filter retains a certain amount of AC current and DC bias, ensuring the extracted AC current is positive. However, this introduces DC error into the output. Moreover, traditional methods involve long paths and significant current mirror mismatch, further contributing to DC error.

[0025] In this invention, the AC quantity is extracted only at the output stage, resulting in a large bias current for all MOSFETs, making it easy for them to operate in the saturation region. Therefore, the current mismatch is small, improving accuracy. Furthermore, since there is no need to retain the DC deviation of the AC current, no DC error is introduced into the output, further improving the output voltage accuracy.

[0026] Furthermore, the circuit from SW to vsum only involves four stages, resulting in a short path and small phase delay, thus achieving low-latency on-chip ripple compensation.

[0027] Figure 1 This is the overall block diagram of the COT BUCK circuit. VIN is the power input voltage, and VOUT is the BUCK output voltage. The PMOS is the upper power transistor, and the NMOS is the lower power transistor. The PMOS source and substrate are connected to VIN, and the NMOS source and substrate are grounded. Their drains are connected together as SW, which is connected to one end of inductor L. The other end of inductor L is connected to the load capacitor C and the load resistor Rload, serving as the output VOUT. Rf1 and Rf2 are feedback resistors. One end of Rf1 is connected to VOUT, and the other end is connected to Rf2, forming Vfb. The other end of Rf2 is grounded. Vfb is connected to the inverting input of the error amplifier and one end of the summing circuit. The other end of the error amplifier is connected to the reference voltage VREF, and the output is VCOM and the non-inverting input of the comparator. Cc is the compensation capacitor for the error amplifier, connected between VCOM and ground. The entire dashed box contains the on-chip ripple compensation circuit, with inputs SW and Vfb, and an output Vsum, which is connected to the inverting input of the comparator. The comparator output is vpulse, which is connected to the adaptive on-time transmitter. The output of the adaptive on-time generator is connected to the driver input, and the driver output is connected to the gate of the power transistors PMOS and NMOS.

[0028] Figure 2 This is the equivalent circuit diagram of the on-chip ripple compensation circuit. The power supply voltage VDD is connected to one end of the AC current source i1. The other end of i1 is connected to one end of the DC current source and one end of Rac, this end being vsum. The other end of i2 is grounded to VSS. The other end of Rac is connected to one end of Rf1 and Rf2, this end being vfb. The other end of Rf1 is connected to the output terminal VOUT of buck, and the other end of Rf2 is grounded to VSS.

[0029] In the diagram, i1 and i2 are the AC current source and DC current source, respectively, and the average value of i1 is equal to that of i2. VOUT is the output voltage of the buck, Rf1 and Rf2 are the output feedback resistors of the buck, and Rac is a resistor.

[0030] i1 = idc + iac,

[0031] i2 = idc, and the mean of i1 is equal to that of i2.

[0032] Since the current source is high-resistance, and current always flows to the low-resistance path, the difference between i1 and i2 will flow to the low-resistance path on the right, and the magnitude of this difference is iac.

[0033] Therefore, the alternating current iac flows to the right Rac, and is connected in parallel with Rf1 to Rf2.

[0034] Therefore, vsum = vfb + iac*(Rac + Rf1 / / Rf2), and iac*(Rac + Rf1 / / Rf2) is the ripple compensation amount, and the DC value remains vfb, which remains unchanged.

[0035] Figure 3 This is the circuit diagram for the on-chip ripple compensation of the invention. SW is connected to one end of resistor R1. The other end of R1 is connected to one end of R2 and R3, this point being vs10. The other end of R2 is grounded (VSS). The other end of R3 is connected to one end of capacitor C1 and the gate of P9, this point being vlpf. The other end of C1 is grounded. The drain of P9 is connected to one end of R4, the other end of R4 is grounded. The source of P9 is connected to the gate of N1 and the drain of P2. The gate of P2 is connected to the gate and drain of P1, and is connected to the bias current ibias. The sources of P1, P2, P3, P5, and P7 are connected to the power supply voltage VDD. The source of N1 is connected to one end of R6, the other end of R6 is grounded. The drain of N1 is connected to one end of R5 and the gates of P4, P6, and P8. The other end of R5 is connected to the drain of P4 and the gates of P3, P5, and P7. The source of P4 is connected to the drain of P3. The source of P6 is connected to the drain of P5. The drain of P6 and one end of R7, the gates of N2 and N4, and one end of C3 are connected; this point is V2. The other end of R7 is connected to the drain of N2, the gates of N3 and N5, and one end of C2; this point is V1. The sources of N3 and N5 are grounded (VSS), and the gates of C2 and C3 are grounded (VSS). The source of N2 and the drain of N3, and the source of N4 and the drain of N5 are connected. The drain of N4 and the drain of P8 are connected to one end of Rac; this point is vsum. The drain of P8 is connected to the source of P7. The other end of Rac is connected to one end of Rf1 and Rf2; this point is vfb. The other end of Rf2 is grounded, and the other end of Rf1 is connected to the BUCK output VOUT.

[0036] Working principle:

[0037] Vs10 = vsw / 10, the resistance of R1 is 9 times that of R2, which can reduce the size of the filter capacitor.

[0038] R3 and C1 form the first-stage low-pass filter circuit, generating a ripple voltage vlpf; and in the frequency domain, a compensated zero ωz=1 / R3*C1 is generated.

[0039] Assume that the threshold voltage vthn of all NMOS transistors is equal to the threshold voltage vthp of all PMOS transistors, which is vth. R6=Rac=R; the width-to-length ratios of P3, P5, and P7 are equal, the width-to-length ratios of P4, P6, and P8 are equal, the width-to-length ratios of N2 and N4 are equal, and the width-to-length ratios of N3 and N5 are equal.

[0040] The current flowing through N1, P3, and P4 is i1 = (vlpf + vthp - vthn) / R6 = vlpf / R6; and the current flowing through P5, P6, P7, and P8 is also equal to i1; define i1 = idc + iac, and the average value of i1 is idc.

[0041] Capacitors C2 and C3 form the second-stage filter. After filtering by V1 and V2, the voltage becomes a DC bias voltage. Therefore, the current flowing through N2, N3, N4, and N5 is the average value of i1, which is its DC value, and equal to idc. Therefore, according to... Figure 2 The theoretical derivation of the equivalent model of the on-chip ripple compensation circuit, the current flowing through Rac and the parallel connection of Rf1 and Rf2 is iac.

[0042] Therefore: the final ripple compensation voltage:

[0043] vsum=vfb+iac*(Rac+Rf1 / / Rf2), where iac*(Rac+Rf1 / / Rf2) is the wave compensation amount, and the DC value remains unchanged as vfb.

[0044] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0045] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A high-precision, low-delay on-chip ripple compensation circuit, characterized in that, The on-chip ripple compensation circuit includes PMOS transistors P1~P9, NMOS transistors N1~N5, resistors R1~R6, and capacitors C1~C3; In the ripple compensation circuit of this chip, one end of resistor R1 is connected to node SW, and the other end is connected to one end of resistors R2 and R3, with the connection point being node vs10; the other end of resistor R2 is grounded to VSS, and the other end of resistor R3 is connected to one end of capacitor C1 and the gate of PMOS transistor P9, with the connection point being node vlpf; the other end of capacitor C1 is grounded to VSS, and the drain of PMOS transistor P9 is connected to one end of resistor R4, with the other end of resistor R4 grounded to VSS. The source of PMOS transistor P9 is connected to the gate of NMOS transistor N1 and the drain of PMOS transistor P2; the gate of PMOS transistor P2 is connected to the gate and drain of PMOS transistor P1 and is connected to the bias current ibias; the source of NMOS transistor N1 is connected to one end of resistor R6, and the other end of resistor R6 is grounded to VSS; the drain of NMOS transistor N1 is connected to one end of resistor R5 and the gates of PMOS transistors P4, P6, and P8; the other end of resistor R5 is connected to the drain of PMOS transistor P4 and the gates of PMOS transistors P3, P5, and P7. The source of PMOS transistor P4 is connected to the drain of PMOS transistor P3; the source of PMOS transistor P6 is connected to the drain of PMOS transistor P5; the drain of PMOS transistor P6 is connected to one end of resistor R7, the gates of NMOS transistors N2 and N4, and one end of capacitor C3, forming node V2; the other end of resistor R7 is connected to the drain of NMOS transistor N2, the gates of NMOS transistors N3 and N5, and one end of capacitor C2, forming node V1; the sources of NMOS transistors N3 and N5 are grounded to VSS; the other ends of capacitors C2 and C3 are grounded to VSS. The source of NMOS transistor N2 is connected to the drain of NMOS transistor N3, the source of NMOS transistor N4, and the drain of NMOS transistor N5. The drain of NMOS transistor N4 is connected to the drain of PMOS transistor P8 and one end of resistor Rac, forming node vsum. The drain of PMOS transistor P8 is connected to the source of PMOS transistor P7. The other end of resistor Rac is connected to one end of output feedback resistors Rf1 and Rf2, forming feedback node vfb. The other end of output feedback resistor Rf2 is grounded, and the other end of output feedback resistor Rf1 is connected to the output VOUT of BUCK.

2. The high-precision, low-delay on-chip ripple compensation circuit according to claim 1, characterized in that, The sources of the PMOS transistors P1, P2, P3, P5, and P7 are connected to the power supply voltage VDD.

3. The high-precision, low-delay on-chip ripple compensation circuit according to claim 1, characterized in that, The on-chip ripple compensation circuit includes an AC current source i1, a DC current source i2, a resistor Rac, and output feedback resistors Rf1 and Rf2. One end of AC current source i1 is connected to the power supply voltage VDD, and the other end of AC current source i1 is connected to one end of DC current source i2 and one end of resistor Rac, with the connection node being vsum. The other end of DC current source i2 is grounded to VSS. The other end of resistor Rac is connected to one end of output feedback resistors Rf1 and Rf2, with the connection node being vfb; the other end of output feedback resistor Rf1 is connected to the output VOUT of BUCK, and the other end of output feedback resistor Rf2 is grounded to VSS.

4. A COT BUCK circuit, characterized in that, The COT BUCK circuit includes an input VIN, a node SW, a feedback node vfb, a comparator, an output VOUT, and a high-precision, low-delay on-chip ripple compensation circuit as described in any one of claims 1-3.

5. A COT BUCK circuit according to claim 4, characterized in that, The on-chip ripple compensation circuit includes a ripple compensation circuit and a summing circuit; wherein, the input of the ripple compensation circuit is connected to node SW, and the output is connected to one input of the summing circuit; the other input of the summing circuit is connected to the feedback node vfb, and the output is node vsum, which is connected to the inverting input of the comparator.

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