RHS-14t-sram circuit and its storage circuit, chip against single event upset

Abstract

The present application relates to the field of integrated circuits, in particular to a single event upset resistant RHS-14T-SRAM circuit and a storage circuit and a chip thereof. The present application reconstructs the original latch structure on the basis of a 6T-SRAM, and then uses the newly added four NMOS to realize polarity reinforcement of the main storage node to enhance the anti-upset capability of the circuit. A set of redundant storage nodes using source isolation reinforcement is provided by using the newly added four PMOS tubes in cooperation with the NMOS tubes, thereby improving the stability of the redundant storage nodes. The new SRAM circuit provided by the present application not only reduces the power consumption of the circuit, but also improves the single event upset resistance of the circuit, and can realize single node upset recovery of all nodes. The problem of performance balance of the traditional circuit is solved, and the present application has a wide application prospect in the field of aerospace.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to an RHS-14T-SRAM circuit resistant to single-event upsets, and its corresponding radiation-resistant memory circuit and radiation-resistant memory chip. Background Technology

[0002] The space environment is filled with a large number of high-energy radiation particles, which can cause malfunctions in aerospace devices. Among these, the Single Event Effect (SEE) poses a significant threat to the operation of integrated circuits in the space environment, making radiation hardening technology for integrated circuits increasingly important. Single Node Upset (SNU) is a form of SEE. When high-energy particles in space incident on semiconductor materials, they deposit charges along their incident path. These charges are collected in sensitive areas, causing node voltage fluctuations and data flipping in memory cells. Ultimately, this can lead to soft errors in the integrated circuit system, with consequences that are unacceptable. SRAM cells, as a large portion of the memory chip's surface area, have a significant impact on the overall performance of the memory chip. Therefore, radiation hardening design for SRAM memory cells is of great practical significance.

[0003] The existing technologies for SRAM memory cell resistance to SNU and DNU (Double Node Upset) mainly include the following typical solutions:

[0004] In 1996, Michael Nicolaidis proposed the DICE structure, which can achieve single-node flip self-recovery, such as... Figure 1 As shown, this structure employs a redundant node hardening method, consisting of four dual-input inverters connected end-to-end. When a SNU occurs in one node, it will only affect one adjacent node at most, and the other two nodes can restore the circuit to its original correct state. Due to its excellent radiation immunity and relatively small number of transistors, DICE has become a classic latch structure.

[0005] In 2019, Kumar C.I. proposed an RHD-12T-SRAM cell, such as... Figure 2 As shown, this structure has four transmission transistors and four storage nodes Q, QB, A, and B. Due to the presence of the four transmission transistors, this structure not only has fast read and write speeds but also resists two-node flipping caused by single-event events. However, the read and write margins of this circuit are relatively poor.

[0006] The RHBD-14T-SRAM cell proposed by NagaRaghuramCH in 2021, such as Figure 3As shown. This circuit uses polarity hardening technology, which reduces the number of sensitive nodes, but results in greater read / write latency and a lower noise margin (SNM) value.

[0007] In 2023, Cai Shuo proposed a CC-18T-SRAM cell, such as... Figure 4 As shown, this circuit has six memory nodes and four redundant nodes. Four NMOS transistors are used for transmission, improving read / write capabilities. To resist single-event upsets, polarity hardening is applied to memory nodes Q and QB to harden redundant nodes. Layout hardening also solves the charge sharing problem. However, this circuit has a large number of transistors, resulting in a larger circuit area and higher power consumption.

[0008] In 2024, Soumya Sengupta proposed an RTSC-14T-SRAM cell, such as... Figure 5 As shown, the cell consists of 14 transistors and uses polar hardening technology. Nodes Q and QB are completely surrounded by three NMOS transistors, forming a polar hardening structure. Therefore, the node can only be flipped from 1 to 0. So when the data stored in the node is 0, it is not a sensitive node. This allows the cell storage node to flip and recover under the single event effect. However, this structure also has great disadvantages, such as consuming a large area and poor read stability.

[0009] In 2025, Pramod Kumar Bharti et al. proposed the DTQ-16T radiation-resistant SRAM cell structure based on polar hardening technology, such as... Figure 6 As shown, this unit has four transmission transistors, but only two transistors are in the on state during both read and write operations, thus reducing power consumption. This structure has a total of four nodes, and nodes A, B, C, and D are completely surrounded by three NMOS or PMOS transistors, forming a polarity-hardened structure. This reduces the number of sensitive nodes, and the structure allows for complete recovery of SNU events occurring on sensitive nodes. Furthermore, the number of sensitive nodes has been reduced from four to two, essentially achieving dual-node recovery. However, this unit has relatively poor performance in maintaining basic circuit performance and read stability. Summary of the Invention

[0010] To improve the balance between radiation resistance, power consumption, and speed in existing SRAM memory circuits, this invention provides an RHS-14T-SRAM circuit resistant to single-event upsets, and its corresponding radiation-resistant memory circuit and radiation-resistant memory chip.

[0011] The technical solution provided by this invention is as follows:

[0012] A single-event upset resistant RHS-14T-SRAM circuit includes eight NMOS transistors N1-N8 and six PMOS transistors P1-P6. The SRAM circuit connections are as follows: the sources of P1-P4 are connected to VDD; the sources of N3-N6 are connected to VSS. The drain of P2 is connected to the source of P6; the drain of P1 is connected to the source of P5. The gates of P2, P3, N4, and N5 are connected to the source of N2 and the drain of N6, forming the master memory node Q; the gates of P1, P4, N3, and N6 are connected to the source of N1 and the drain of N5, forming the master memory node QB; the voltage levels of memory nodes Q and QB are inverted. P4 is connected to the drain of N2; P3 is connected to the drain of N1. The gates of P6 and N2 are connected to the drains of P5 and N3, forming a redundant memory node S1; the gates of P5 and N1 are connected to the drains of P6 and N4, forming a redundant memory node S0; the voltage levels of memory nodes S0 and S1 are also inverted. N8 serves as the transmission transistor between the main memory node Q and the bit line BL; N7 serves as the transmission transistor between the main memory node QB and the bit line BLB; the gates of N7 and N8 are connected to the word line WL.

[0013] In the RHS-14T-SRAM circuit for resisting single-event upsets provided by this invention, the main memory nodes Q and QB are surrounded by NMOS transistors N2, N4, N6, N8 and N1, N3, N5, N7, thereby forming polarity hardening; the redundant memory nodes S0 and S1 are source-isolated hardened by PMOS transistors P5 and P6.

[0014] In the RHS-14T-SRAM circuit for resisting single-event upsets provided by the present invention, when the stored data is "1", the sensitive nodes include Q and S1; when the stored data is "0", the sensitive nodes include QB and S0; when any sensitive node is bombarded by a single event, it can achieve self-recovery from the upset.

[0015] In the RHS-14T-SRAM circuit for resisting single-event upsets provided by this invention, when WL is set to a low level, the circuit is in a hold state. At this time, storage nodes Q and QB are disconnected from bit lines BL and BLB, respectively; the level states of redundant storage nodes S1 and S0 are the same as the level states of Q and QB, respectively; and the level states of each storage node remain unchanged from the previous cycle.

[0016] In the RHS-14T-SRAM circuit for resisting single-event upsets provided by this invention, when Q and S1 are high and QB and S0 are low, it indicates that the stored data is "1"; when Q and S1 are low and QB and S0 are high, it indicates that the stored data is "0".

[0017] In the single-event upset resistant RHS-14T-SRAM circuit provided by this invention, the data reading operation strategy is as follows:

[0018] First, set WL to low level and precharge BL and BLB to high level; then set WL to high level; at this time, if BL drops from high level to low level and BLB remains high level, it means that the original stored data read is "0"; if BL remains high level and BLB drops from high level to low level, it means that the original stored data read is "1".

[0019] In the RHS-14T-SRAM circuit with anti-single-event upset provided by this invention, the data writing operation strategy is as follows:

[0020] If you need to write the data "1", first set BL to high level, BLB to low level, and then set WL to high level; then Q is set to high level and QB is set to low level, thus completing the writing of the data "1".

[0021] If you need to write the data "0", first set BL to low level, BLB to high level, and then set WL to high level; then Q is set to low level and QB is set to high level, thus completing the writing of the data "0".

[0022] The present invention also includes a radiation-resistant memory circuit, comprising a memory array and its peripheral circuitry. The memory array is composed of RHS-14T-SRAM circuitry with single-event upset resistance as described above, arranged as a memory cell array. Memory cells in the same row share a word line WL, and memory cells in the same column share bit lines BL and BLB.

[0023] The present invention also includes a radiation-resistant memory chip, which is packaged from the radiation-resistant memory circuit as described above; in the layout of the radiation-resistant memory chip, each memory cell is symmetrically arranged, and the memory nodes Q and S1 contained therein are located at the two diagonal positions of the corresponding areas in the layout.

[0024] As a further improvement of the present invention, the gate width of N1~N8 and P1~P6 in each memory cell is 100nm and the gate length is 30nm.

[0025] The present invention has the following beneficial effects:

[0026] The RHS-14T-SRAM circuit for single-event upset resistance provided by this invention improves the latch structure based on the classic 6T-SRAM circuit. It utilizes newly added NMOS transistors to harden the polarity of the original memory nodes Q and QB, and adds redundant memory nodes hardened with source isolation. This circuit achieves both polarity hardening and source isolation hardening in a single-event upset SRAM circuit using only 14 transistors, reducing the number of sensitive nodes, fully realizing SNU self-recovery, and improving noise tolerance. Furthermore, this invention uses layout design to separate the only two sensitive nodes in the circuit, thereby reducing the probability of single-event upsets and further improving the circuit's radiation resistance. Attached Figure Description

[0027] Figure 1 This is a circuit diagram of the DICE circuit described in the background section.

[0028] Figure 2 The circuit diagram is for the RHD-12T circuit described in the background section.

[0029] Figure 3 The circuit diagram is for the RHBD-14T circuit described in the background section.

[0030] Figure 4 The circuit diagram is for the CC-18T circuit described in the background section.

[0031] Figure 5 The circuit diagram is for the RTSC-14T circuit described in the background section.

[0032] Figure 6 The circuit diagram is for the DTQ-16T circuit described in the background section.

[0033] Figure 7 The circuit diagram of the RHS-14T-SRAM circuit for resisting single-event upsets provided in Embodiment 1 of the present invention.

[0034] Figure 8 The timing waveform diagram for the data storage operation of the RHS-14T-SRAM circuit of the present invention in the test experiment is shown (simulation conditions: Corner: TT; Temperature: 27℃; VDD: 0.9V).

[0035] Figure 9 The transient waveform simulation diagram of each storage node in the RHS-14T-SRAM circuit of the present invention after being injected with a double exponential current source pulse in the test experiment (simulation conditions: Corner: TT; Temperature: 27℃; VDD: 0.9V). Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0038] Example 1

[0039] This embodiment provides an RHS-14T-SRAM circuit resistant to single-event upsets, which includes eight NMOS transistors N1~N8 and six PMOS transistors P1~P6. For example... Figure 7 As shown, the SRAM circuit connections are as follows: the sources of P1~P4 are connected to VDD; the sources of N3~N6 are connected to VSS. The drain of P2 is connected to the source of P6; the drain of P1 is connected to the source of P5. The gates of P2, P3, N4, and N5 are connected to the source of N2 and the drain of N6, forming the master memory node Q; the gates of P1, P4, N3, and N6 are connected to the source of N1 and the drain of N5, forming the master memory node QB; the voltage levels of memory nodes Q and QB are inverted. P4 is connected to the drain of N2; P3 is connected to the drain of N1. The gates of P6 and N2 are connected to the drains of P5 and N3, forming the redundant memory node S1; the gates of P5 and N1 are connected to the drains of P6 and N4, forming the redundant memory node S0; the voltage levels of memory nodes S0 and S1 are also inverted. N8 serves as the transmission transistor between the main memory node Q and the bit line BL; N7 serves as the transmission transistor between the main memory node QB and the bit line BLB; the gate word lines WL are for N7 and N8.

[0040] exist Figure 7In the RHS-14T-SRAM circuit shown, PMOS transistor P4 and NMOS transistor N6 form an inverter, and PMOS transistor P3 and NMOS transistor N5 form another inverter, which are cross-coupled. NMOS transistor N2 is connected between the drains of PMOS transistors P4 and NMOS transistor N6, forming a main memory node Q. NMOS transistor N1 is connected between the drains of PMOS transistors P3 and NMOS transistor N5, forming another main memory node QB. Therefore, P3, P4, N1, N2, N5, and N6 form an anti-phase cross-coupled latch structure, providing two anti-phase main memory nodes Q and QB. Based on this, this embodiment further provides a source-isolated hardened redundant memory node. Specifically, redundant memory nodes S0 and S1 are cross-coupled by PMOS transistors P5 and PMOS transistor P6. PMOS transistors P2 and P1 serve as pull-up transistors for the new redundant memory node, and NMOS transistors N4 and NMOS transistor N3 serve as pull-down transistors for the new redundant memory node.

[0041] In the RHS-14T-SRAM circuit with single-event upset resistance provided in this embodiment, the data storage function includes a hold state, data writing, and data reading. When WL is set low, the circuit is in a hold state. At this time, NMOS transistors N7 and N8 are off; storage nodes Q and QB are disconnected from bit lines BL and BLB, respectively. Since the level state of node Q is always opposite to that of node QB, one of the NMOS transistors N5 and N6 is turned on while the other is turned off. Furthermore, due to the cross-coupled circuit structure of N5 and N6, the pull-down transistors corresponding to nodes storing high levels in the main storage nodes Q and QB are turned off, while the pull-down transistors corresponding to nodes storing low levels are turned on, thus maintaining the level state of nodes Q and QB. Simultaneously, the level states of redundant storage nodes S1 and S0 are the same as those of Q and QB, respectively. In the hold state, the level state of each storage node is the state corresponding to the data written in the previous cycle and remains unchanged. Specifically, when Q and S1 are high and QB and S0 are low, it indicates that the stored data is "1"; when Q and S1 are low and QB and S0 are high, it indicates that the stored data is "0".

[0042] In the single-event upset resistant RHS-14T-SRAM circuit provided in this embodiment, the data reading operation strategy is as follows:

[0043] First, set WL to low level to disconnect the electrical connection between the main storage node and the bit lines on both sides; then precharge BL and BLB to high level. Next, set WL to high level; at this time, storage nodes Q and QB are electrically connected to bit lines BL and BLB respectively. In this state, if the original stored data is 0, then Q is low and QB is high, so BL forms a discharge path through storage node Q, causing the bit line voltage of BL to drop; while BLB and node QB have the same level state, so no discharge path is formed, and the bit line voltage of BLB remains high. That is: if BL drops from high level to low level and BLB remains high level, it means that the original stored data read is "0". Similarly, if BL remains high level and BLB drops from high level to low level, it means that the original stored data read is "1".

[0044] Accordingly, the data writing strategy of the RHS-14T-SRAM circuit with anti-single-event upset provided in this embodiment is as follows: If data "1" needs to be written, BL is first set to high level, BLB is set to low level, and then WL is set to high level; then Q is set to high level and QB is set to low level, thus completing the writing of data "1". If data "0" needs to be written, BL is first set to low level, BLB is set to high level, and then WL is set to high level; then Q is set to low level and QB is set to high level, thus completing the writing of data "0".

[0045] Further observation Figure 7 As can be seen, in the RHS-14T-SRAM circuit for resisting single-event upsets provided in this embodiment, the main memory nodes Q and QB are polarized hardened by being surrounded by NMOS transistors N2, N4, N6, N8 and N1, N3, N5, N7; the redundant memory nodes S0 and S1 are source-isolated hardened by PMOS transistors P5 and P6. Since Q and QB are surrounded by three NMOS transistors, they form a polarized hardened structure. According to the principle of polarized hardening, when these nodes experience a SEU (Self-Effective Unstable) event, they only generate voltage pulses of "1→0" and "0→0", that is, only negative pulses. Therefore, when the voltage level of these nodes is low when storing data, they are not sensitive nodes, and the voltage logic remains unchanged after an SEU. The S0 and S1 nodes are laid out using source isolation technology. By replacing the pull-up PMOS transistors of the traditional inverter with two PMOS transistors connected in series and adding an STI layer, the charge collection of the transistors is effectively suppressed. When a SEU occurs at these nodes, the voltage pulse generated is insufficient to flip the nodes from low to high. Therefore, when these nodes store data, the corresponding level state is low, and they can be considered as not sensitive nodes.

[0046] This embodiment provides an RHS-14T-SRAM circuit with excellent anti-single-node flip-over characteristics. The following details the circuit principle of the RHS-14T-SRAM circuit in achieving self-recovery from single-particle bombardment flip-over under different conditions:

[0047] Because nodes Q and QB in this embodiment employ polarity hardening technology, and nodes S0 and S1 employ source isolation technology, there are only two sensitive nodes when the stored data is "1" (i.e., Q and S1 are high, QB and S0 are low): nodes Q and S1. Since the circuit has only two sensitive nodes, the SNU accordingly includes two cases:

[0048] Case 1: When node Q experiences SNU

[0049] In this state, when SNU occurs in Q, the state of Q flips from high to low. NMOS transistors N4 and N5 are turned off, and PMOS transistors P2 and P3 are turned on. Since the states of PMOS transistors P5 and P6 do not change, S0 and QB are in a high-impedance state, maintaining their original voltages. Because the states of S1 (high) and QB (low) remain unchanged, node Q will be restored to its initial state by transistors P4, N2, and N6, which is the high level representing the original stored data "1".

[0050] Case 2: When node S1 experiences SNU

[0051] In this state, when S1 experiences an SNU, the state of S1 flips from high to low. NMOS transistor N2 turns off, and PMOS transistor P6 turns on. Since the states of PMOS transistors P4 and N6, as well as transistors P2 and N4, remain unchanged, Q and S0 are in a high-impedance state, maintaining their original voltages. Because nodes S0 and QB remain in a low-level state, node S1 will be restored to the high-level state representing the original stored data "1" by P1, P5, and N3.

[0052] In summary, external bombardment typically occurs in hold mode. The circuit in this embodiment can achieve complete SNU self-recovery when the storage node is bombarded by a single particle.

[0053] Example 2

[0054] Based on the single-event upset (SOME) resistant RHS-14T-SRAM circuit provided in Embodiment 1, this embodiment further provides a radiation-resistant memory circuit, which includes a memory array and its peripheral circuitry. Similar to conventional SRAM memory circuits, the peripheral circuitry mainly includes word line driver circuits, bit line driver circuits, and comparator arrays related to data retrieval. Specifically, the memory array in the radiation-resistant memory circuit provided in this embodiment is formed by arranging the SOME resistant RHS-14T-SRAM circuit as described in Embodiment 1 as a memory cell array. Each memory cell in a row shares the word line WL, and each memory cell in a column shares the bit lines BL and BLB.

[0055] Accordingly, in practical applications, this embodiment also provides a radiation-hardened memory chip, which is packaged from the aforementioned radiation-hardened memory circuit. In the layout of the radiation-hardened memory chip, each memory cell is symmetrically arranged, and the memory nodes Q and S1 contained therein are located on the two diagonal positions of the corresponding areas in the layout. This effectively separates the only two sensitive nodes in each memory cell, reducing the probability of single-event upsets and further improving the radiation resistance of the circuit. In addition, in the RHS-14T-SRAM circuit for single-event upsets provided in this embodiment, the gate width of N1~N8 and P1~P6 is preferably 100nm, and the gate length is preferably 30nm.

[0056] Performance testing

[0057] 1. Read and write functions

[0058] This experiment first tested the circuit's read / write capabilities. The timing signal streams of the key signals in this process are as follows: Figure 8 As shown, the specific simulation conditions are: Corner: TT; Temperature: 27℃; VDD: 0.9V.

[0059] Depend on Figure 8 It can be seen that: before the word line WL is turned on, the bit lines BL and BLB are kept at a high level, so that the bit line precharge signal is kept at a high level; after the word line WL is turned on, if BL and BLB are both at a high level, the storage circuit performs a read operation; if BL and BLB are one high and one low, the storage circuit performs a write operation; when WL is kept at a low level, the storage circuit is in a hold state.

[0060] 2. Anti-single-node flipping

[0061] This experiment verifies the data recovery performance of the circuit under single-node flip (SNU) state. Due to the use of polarity hardening and source isolation hardening techniques, only storage nodes Q and S1 are sensitive nodes when the stored data is "1". Correspondingly, only storage nodes QB and S0 are sensitive nodes when the stored data is "0". Figure 9The figure shows the transient waveform simulation diagram of the circuit provided by the present invention at different times and at different nodes when it is injected by a double exponential current source pulse. The specific simulation conditions are: Corner: TT; Temperature: 27℃; VDD: 0.9V.

[0062] analyze Figure 9 The signal indicates that the read / write operation settings are... Figure 8 With consistent settings, double exponential current source pulses were used to inject errors into storage nodes Q, S1, QB, and S0 at 7ns, 8ns, 16ns, and 18ns respectively. It was observed that when a negative pulse was injected into node Q at 7ns, node Q quickly recovered to its original initial state. The same operation was performed at 8ns, 16ns, and 18ns, and it could still resist the interference of bombardment current. Furthermore, during each of the four bombardments, the stored information of the other three nodes did not leak or flip. Therefore, it can be concluded that the RHS-14T-SRAM circuit based on polarity hardening technology and source isolation technology provided by this invention can achieve complete resistance to single-event upsets.

[0063] 3. Performance Comparison

[0064] This experiment uses the four circuit schemes (RHD-12T, RHBD-14T, CC-18T, and RHS-14T) introduced in the background technology as control groups, and compares them with the circuit scheme of this invention (denoted as RHS-14T). The average power consumption, read delay, write delay, and critical charge of the five circuits are tested, and the performance comparison table is shown in Table 1:

[0065] Table 1: Performance Comparison Table of the Invention Circuit and the Control Circuit

[0066]

[0067] Analysis of the data in the table above reveals that the average power consumption of the RHS-14T cell provided by this invention is only 1.696mW, which is significantly lower than the other four comparative circuits. The write latency of the RHS-14T circuit is 4.3ps, slightly longer than the CC-18 cell (4.14ps) and the RTSC-14T cell (4.21ps); the read latency of the RHS-14T circuit is 46.8ps, with only a small difference compared to the other four comparative circuits. Regarding critical charge, compared to existing SRAM memory cells, the critical charge of the RHS-14T circuit is relatively high, exhibiting better radiation resistance. In summary, the RHS-14T-SRAM circuit of this invention uses fewer transistors, yet achieves good power consumption, write latency, and radiation resistance.

[0068] The above-described embodiments are merely one implementation of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A single-event upset resistant RHS-14T-SRAM circuit, characterized in that, It includes 8 NMOS transistors N1~N8 and 6 PMOS transistors P1~P6; wherein, the sources of P1~P4 are connected to VDD; the drain of P2 is connected to the source of P6; the drain of P1 is connected to the source of P5; the gates of P2, P3, N4, and N5 are connected to the source of N2 and the drain of N6, and serve as the main memory node Q; the gates of P1, P4, N3, and N6 are connected to the source of N1 and the drain of N5, and serve as the main memory node QB; P4 and N2 The drains of P3 and N1 are connected; the gates of P6 and N2 are both connected to the drains of P5 and N3, and serve as redundant memory node S1; the gates of P5 and N1 are both connected to the drains of P6 and N4, and serve as redundant memory node S0; the sources of N3 to N6 are connected to VSS; N8 serves as the transmission transistor between the main memory node Q and the bit line BL; N7 serves as the transmission transistor between the main memory node QB and the bit line BLB; the gates of N7 and N8 are connected to the word line WL. Among them, the primary storage node Q is surrounded by N2, N4, N6, and N8, and the primary storage node QB is surrounded by N1, N3, N5, and N7, thus forming polarity hardening; the redundant storage nodes S0 and S1 are hardened by source isolation through P5 and P6.

2. The RHS-14T-SRAM circuit resistant to single-event upsets according to claim 1, characterized in that: When the stored data is "1", the sensitive nodes include Q and S1; when the stored data is "0", the sensitive nodes include QB and S0. When any sensitive node is bombarded by a single particle, it can achieve flip-over self-recovery.

3. The RHS-14T-SRAM circuit resistant to single-event upsets according to claim 1, characterized in that: When WL is set to low, the circuit is in a hold state. At this time, storage nodes Q and QB are disconnected from bit lines BL and BLB, respectively. The level states of redundant storage nodes S1 and S0 are the same as the level states of Q and QB, respectively, and the level states of each storage node remain unchanged from the previous cycle.

4. The RHS-14T-SRAM circuit resistant to single-event upsets according to claim 3, characterized in that: When Q and S1 are high and QB and S0 are low, the stored data is "1"; when Q and S1 are low and QB and S0 are high, the stored data is "0".

5. The RHS-14T-SRAM circuit resistant to single-event upsets according to claim 1, characterized in that: The data reading operation strategy is as follows: First, set WL to low level and precharge BL and BLB to high level; then set WL to high level. At this time, if BL drops from high level to low level and BLB remains high level, it means that the original stored data "0" has been read; if BL remains high level and BLB drops from high level to low level, it means that the original stored data "1" has been read.

6. The RHS-14T-SRAM circuit resistant to single-event upsets according to claim 1, characterized in that: The data writing operation strategy is as follows: If the data "1" needs to be written, first set BL to high level, BLB to low level, and then set WL to high level; then Q is set to high level and QB is set to low level, thus completing the writing of the data "1". If you need to write the data "0", first set BL to low level, BLB to high level, and then set WL to high level; then Q is set to low level and QB is set to high level, thus completing the writing of the data "0".

7. A radiation-resistant storage circuit, comprising a storage array and peripheral circuitry, characterized in that: The memory array is formed by arranging the RHS-14T-SRAM circuit with anti-single-event-flip capability as described in any one of claims 1-6 as memory cells; in the memory array, each memory cell in the same row shares the word line WL, and each memory cell in the same column shares the bit lines BL and BLB.

8. A radiation-resistant memory chip, characterized in that: It is packaged from the radiation-resistant storage circuit as described in claim 7.

9. The radiation-resistant memory chip according to claim 8, characterized in that: In the layout of the radiation-resistant memory chip, each memory cell is symmetrically arranged, and the memory nodes Q and S1 contained therein are located on the two diagonal positions of the area where the corresponding memory cell is located in the layout.

10. The radiation-resistant memory chip according to claim 8, characterized in that: Each memory cell has a gate width of 100nm for N1~N8 and a gate length of 30nm for P1~P6.

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