PCIe link monitoring and self-repair system for FPGA acceleration card

Abstract

The application provides a PCIe link monitoring and self-repair system for an FPGA acceleration card, and the system comprises: a signal acquisition module having a main sampler anchored at a central sampling point and an offset sampler capable of biased sampling; a monitoring point calibration module for controlling the offset sampler to scan along a voltage axis and a time axis after the link is ready, determining an eye diagram boundary and calculating a monitoring sampling point; an online monitoring module for polling each monitoring point and interrupting when an error code exceeds a limit, and outputting a repair trigger signal; a repair decision module for determining a distortion type according to an abnormal point position and outputting a coding signal; and a parameter adjustment module for selecting a target equalizer according to the coding signal, and performing adaptive iterative adjustment with the monitoring result as feedback until the link returns to normal. The application realizes real-time monitoring, rapid diagnosis and closed-loop self-repair of the PCIe link signal under the premise of uninterrupted service, and significantly improves the stability and reliability of the system.

Description

Technical Field

[0001] This invention belongs to the field of high-speed data transmission technology, specifically relating to a PCIe link monitoring and self-repair system for FPGA accelerator cards. Background Technology

[0002] In scenarios such as data centers, high-frequency trading, artificial intelligence training, and high-performance computing, the requirements for bandwidth and latency in computing tasks are becoming increasingly stringent. As a key device carrying core acceleration tasks, FPGA accelerator cards installed in servers exchange data with the host via a high-speed PCIe bus. The signal integrity of its link has become a critical bottleneck to ensure the continuous and stable output of the overall system's computing power. As the PCIe protocol continues to evolve to the fifth generation and above, the single-channel data transmission rate has reached and exceeded 32 GT / s, and is moving towards 64 GT / s (Gen6). The exponential increase in transmission rate has drastically worsened the signal integrity challenges faced by signals when traversing physical media such as printed circuit boards, connectors, and packages: on the one hand, the high-frequency components of the signal are severely attenuated during transmission, while the effects of electromagnetic interference, power supply noise, and inter-symbol interference are significantly amplified, causing a sharp contraction in the "eye diagram" opening at the receiving end; on the other hand, link performance has become extremely sensitive to operating temperature, power supply voltage fluctuations, equipment aging, and minor mechanical stress and vibration. These time-varying factors can cause dynamic degradation of signal quality on a time scale of milliseconds to seconds.

[0003] Currently, the industry's health maintenance and fault recovery mechanisms for FPGA accelerator card PCIe links still face the following critical challenges: First, the fault response is passive, resulting in high service interruption costs. Existing PCIe links lack online early warning and rapid compensation capabilities when physical layer degradation occurs. Systems typically must passively wait for bit errors to accumulate until a link layer error or protocol layer timeout is triggered, forcing the link training and state machine to exit the efficient L0 working state and enter a time-consuming recovery process. This process causes microsecond to millisecond-level interruptions in service data flow. For latency-sensitive applications, the service loss and performance jitter caused by such interruptions are unacceptable. Second, monitoring methods are outdated and cumbersome, failing to provide real-time early warning. Current assessments of link signal quality heavily rely on expensive, offline testing equipment such as external high-speed oscilloscopes and bit error rate testers, making real-time monitoring during equipment operation impossible. Although some high-end FPGAs integrate basic on-chip signal diagnostic functions, their implementation typically relies on embedded soft-core processors and employs a "full matrix two-dimensional traversal" scanning method. This method requires massive storage resources, with a single complete eye diagram scan taking several seconds or even minutes, resulting in huge resource overhead and slow response speed. Essentially, it remains a "post-event diagnostic" tool, unable to achieve millisecond-level capture and early warning of transient signal degradation, let alone meet the needs of 24 / 7, low-overhead online health monitoring. Finally, the lack of closed-loop adaptive capability leads to insufficient long-term system robustness. Faced with persistent physical layer parameter drift caused by factors such as changes in ambient temperature and device aging, existing hardware systems generally lack a closed-loop self-repair mechanism that can automatically diagnose the root cause of degradation (e.g., distinguish between signal amplitude attenuation and timing jitter) and adjust the physical layer equalizer parameters in real time and accurately without interrupting business operations. The lack of this capability leaves high-value FPGA accelerators stuck in complex real-world deployment environments, posing a severe challenge to their long-term stability, reliability, and performance maintenance capabilities, resulting in high maintenance costs.

[0004] Therefore, there is an urgent need in this field for an innovative PCIe link monitoring and self-healing system. This system must be able to achieve real-time monitoring of link signal quality with extremely low hardware overhead while ensuring uninterrupted service. Upon detecting signal degradation, it should be able to quickly and automatically complete fault diagnosis and parameter adjustment, thereby achieving online, closed-loop self-healing of the link. Ultimately, this will significantly improve the long-term operational stability, reliability, and service continuity of FPGA accelerator cards in high-speed data transmission scenarios. Summary of the Invention

[0005] The purpose of this invention is to provide a PCIe link monitoring and self-repair method for FPGA accelerator cards that is completely independent of the CPU, enabling real-time health monitoring, rapid fault diagnosis, and adaptive parameter adjustment of the PCIe link without interrupting services.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] The first aspect of this invention provides a PCIe link monitoring and self-repair system for FPGA accelerator cards, comprising a signal acquisition module, a monitoring point calibration module, an online monitoring module, a repair decision module, and a parameter adjustment module. The signal acquisition module includes a main sampler and an offset sampler, configured to perform parallel sampling of signals from the same PCIe physical channel. The main sampler is configured to continuously sample from a center sampling point locked by a clock data recovery circuit. The offset sampler is configured to perform programmable offset sampling relative to the center sampling point in a voltage and time two-dimensional coordinate system. The monitoring point calibration module is connected to the signal acquisition module and is configured to, after the link enters the working state, control the offset sampler to scan along the voltage and time axes passing through the center sampling point. It determines the eye diagram boundary based on the sampling comparison results of the offset sampler and the main sampler, and calculates multiple monitoring sampling points based on a preset safety margin. The online monitoring module is connected to the monitoring point calibration module and the main sampler... The acquisition module is connected to the main monitoring module and configured to control the offset sampler to perform polling sampling at multiple monitoring sampling points. During the dwell monitoring period of a single monitoring sampling point, when the number of bit errors generated by the sampling comparison between the offset sampler and the main sampler exceeds the warning threshold, the link status is determined to be abnormal, the polling sampling is interrupted and paused, and a repair trigger signal containing the current monitoring sampling point location information is output. The repair decision module is connected to the online monitoring module and configured to receive the repair trigger signal, determine the physical layer distortion type according to the current monitoring sampling point location information, and output the corresponding distortion type encoding signal. The parameter adjustment module is connected to the repair decision module, the online monitoring module, and the physical layer transceiver and configured to receive the distortion type encoding signal, determine the target equalizer based on the physical layer distortion type, use the monitoring results output by the online monitoring module as feedback, and iteratively adjust the parameters of the target equalizer through the physical layer transceiver until the online monitoring module continuously determines that the link status is normal.

[0008] The PCIe link monitoring and self-repair system of this invention abandons the traditional thinking of "graphical rendering". After the PCIe link is initialized, it initiates an on-chip eye diagram sampling. After anchoring the main sampler to the center origin, the offset sampler scans only along the voltage axis (signal amplitude dimension) and the time axis (signal timing / phase dimension) to find the eye width and eye height boundaries, compressing the complex traversal of thousands of sampling points into lightweight linear calculations. It fixes the detection sampling points at the safety boundary and breaks the physical hardware quantity limitation through the polling sampling mechanism of a single offset sampler, realizing closed-loop monitoring in an uninterrupted (L0) state. Through the repair decision module and parameter adjustment module, it maps the physical layer distortion type according to the location information of the monitoring sampling points detected by the link anomaly and adaptively modifies the physical layer parameters until the online monitoring module continuously determines that the link status is normal again. Thus, the PCIe link monitoring and self-repair system of this invention achieves lightweight design and realizes a closed-loop process from online monitoring to autonomous repair without relying on the CPU, significantly improving the long-term stability and service continuity of high-speed links under complex operating conditions.

[0009] In some embodiments, the monitoring point calibration module includes an error detection unit and a monitoring sampling point calibration unit. The error detection unit is configured to perform real-time bit-by-bit comparison of the output data of the offset sampler and the main sampler using XOR logic when the offset sampler is located at each scanning coordinate point, and count any inconsistencies to obtain the number of bit errors for a single scanning coordinate point within the dwell monitoring period. The monitoring sampling point calibration unit is configured to compare the number of bit errors for a single scanning coordinate point within the dwell monitoring period with a preset boundary judgment threshold. When the number of bit errors reaches or exceeds the boundary judgment threshold, the scanning coordinate point is determined to be an eye diagram limit boundary coordinate. For the determined eye diagram limit boundary coordinate, a preset voltage safety margin or time safety margin is shrunk inward to calculate the corresponding monitoring sampling point.

[0010] According to some specific implementations, the boundary determination threshold is configured to correspond to a local bit error rate of 10. -3 The number of bit errors on the order of magnitude.

[0011] According to some specific implementations, the voltage safety margin is 15~25mV, and the time safety margin is 0.04~0.06UI.

[0012] In some embodiments, the monitoring point calibration module includes a voltage regulation module and a phase regulation module. The voltage regulation module includes a programmable digital-to-analog converter for providing a dynamically adjustable voltage bias to the offset sampler. The phase regulation module includes a programmable phase interpolator for providing a dynamically adjustable phase bias to the offset sampler.

[0013] Furthermore, the monitoring point calibration module includes a scanning control unit, which is configured to control the offset sampler to perform step scanning along the voltage axis and the time axis with a preset step size, with the center sampling point as the origin.

[0014] Furthermore, the scanning control unit is configured to control the offset sampler to perform adaptive step scanning, the adaptive step scanning including: dynamically adjusting the scanning step size according to the comparison result of the detected number of bit errors and a preset threshold: if the number of bit errors is lower than the preset threshold, a first scanning step size is used; if the number of bit errors reaches or exceeds the preset threshold, a second scanning step size smaller than the first scanning step size is used.

[0015] In some preferred embodiments, the preset threshold is 8, 9, 10, 11, 12, 13, 14, or 15 bit errors.

[0016] According to some specific implementations, the voltage step size in the first scan step size is configured to be 4 LSB and the time step size is configured to be 1 / 16 UI; the voltage step size in the second scan step size is configured to be 1 LSB and the time step size is configured to be 1 / 128 UI.

[0017] In other embodiments, the adaptive step scanning further includes: dynamically adjusting the scanning period according to the scanning step size: when using a first scanning step size, a first dwell listening period is used; when using a second scanning step size, a second dwell listening period longer than the first dwell listening period is used. This captures low-probability bit error events (e.g., probe 10). -9 (Level of deep error profile), ensuring high confidence in boundary test data.

[0018] Through the aforementioned adaptive dynamic scanning and step size adjustment mechanism, the system can intelligently identify the error-free inner circle region and the outer edge region of the eye diagram. While ensuring the measurement accuracy of key gradient data such as eye width, eye height, and bathtub curve, it significantly reduces invalid waiting and redundant sampling in non-critical areas, exponentially reducing the total time required for traditional full matrix traversal scanning, and greatly improving the efficiency of chip internal link diagnosis and equalizer (such as DFE / FFE) tap adaptive convergence.

[0019] Furthermore, both the voltage regulation module and the phase regulation module include clamping circuits in their control logic to prevent control commands from going out of bounds and causing control code wrap-around (e.g., from a sudden change from the maximum positive voltage to the maximum negative voltage), thereby avoiding serious errors in the scan data and potential system crashes, and ensuring the reliability of the hardware circuit under extreme scan conditions.

[0020] In some implementations, the monitoring point calibration module includes a dwell listening period control unit configured to dynamically control the configurable sampling duration of the offset sampler at a single scan coordinate point based on a statistical confidence requirement of the target bit error rate.

[0021] In some specific implementations, the dwell monitoring period for a single scan coordinate point is configured to be 10. 5 One bit cycle.

[0022] In some implementations, zero-point calibration is performed on the voltage bias path of the offset sampler before the scan begins to eliminate the comparator's inherent offset voltage.

[0023] In some implementations, the online monitoring module includes a probe coordinate register unit and a polling control unit. The probe coordinate register unit stores the coordinates of the plurality of monitoring sampling points, and the polling control unit is configured to control the offset sampler to sequentially poll the monitoring sampling points in a time-division multiplexing manner. By using a time-division multiplexing (TDM) workflow based on a single offset sampler, the hardware limitation on the number of underlying physical samplers is broken, and all-weather closed-loop monitoring is achieved without interrupting the core business data flow (L0 state).

[0024] Furthermore, the polling control unit includes a timer configured to control the dwell period of the offset sampler at a single monitoring sampling point. The polling control unit is configured to perform real-time bit-by-bit comparison of the outputs of the offset sampler and the main sampler using XOR logic within the dwell period of a single monitoring sampling point, and count any inconsistencies to obtain the number of bit errors at a single monitoring sampling point within that dwell period. The online monitoring module includes a comparison unit configured to compare the number of bit errors at a single monitoring sampling point within that dwell period with a warning threshold at the end of the dwell period. The polling control unit is configured to: when the number of bit errors is less than the warning threshold, control the offset sampler to poll to the next monitoring sampling point; when the number of bit errors reaches or exceeds the warning threshold, interrupt polling and generate the repair trigger signal.

[0025] In some specific implementations, the dwell time for a single monitoring sampling point is configured to be 1ms.

[0026] In some specific implementations, the warning threshold is configured to correspond to a local bit error rate of 10. -3 The number of bit errors is on the order of magnitude; for example, within a single monitoring period at a single monitoring point, the cumulative sampling is 10. 5 The warning threshold is configured to 100 errors.

[0027] Furthermore, the polling control unit is also configured to pause polling sampling and enter a waiting state after generating the repair trigger signal, until a re-evaluation trigger signal is received from the parameter adjustment module.

[0028] Furthermore, the probe coordinate register unit stores four monitoring sampling points, which correspond to the upper and lower boundaries of the eye diagram in the voltage direction and the left and right boundaries in the time direction, respectively, and the coordinates of each monitoring sampling point have been reduced inward by a preset safety margin.

[0029] In some specific embodiments, the monitoring sampling point includes: top voltage coordinate P top (0, V) top Bottom voltage coordinate P bot (0, V) bot ), left phase coordinate P left (T) left ,0) and the right-side phase coordinate P right (T) right ,0).

[0030] In some implementations, the repair decision module is a combinational logic circuit configured to determine the coordinate axis to which the current monitoring sampling point belongs based on the location information of the current monitoring sampling point in the repair trigger signal, and map the coordinate axis to the corresponding physical layer distortion type: if it belongs to the voltage axis, it is determined to be amplitude attenuation; if it belongs to the time axis, it is determined to be phase jitter. The distortion type encoding signal output by the repair decision module is a multi-bit code used to identify either amplitude attenuation or phase jitter distortion. The repair decision module can diagnose probe faults through combinational gate logic, without requiring a state machine or consuming a clock, thus achieving lightweight design.

[0031] Furthermore, the repair decision module is also configured to output an adjustment enable signal to the parameter adjustment module simultaneously with the output of the distortion type encoded signal. This adjustment enable signal contains a direction instruction indicating whether to increment or decrement the register value of the target equalizer. Because the single compensation amount is fixed to one least significant bit (1 LSB, such as one gain level of CTLE or the first-order weight of the DFE tap) in the target equalizer's register, this extremely simple single-step triggering mechanism avoids the introduction of complex hardware multipliers, accumulators, or floating-point units, thus perfectly meeting the extreme resource and power consumption requirements of the FPGA accelerator card for lightweight monitoring and adjustment IP.

[0032] In some implementations, the parameter adjustment module includes an address mapping unit and a read-modify-write state machine. The address mapping unit is configured to receive the distortion type encoding signal and, based on the determined physical layer distortion type, output the corresponding target equalizer address: when the distortion type encoding signal indicates amplitude attenuation, it outputs the address of the continuous-time linear equalizer control register; when the distortion type encoding signal indicates phase jitter, it outputs the address of the decision feedback equalizer control register. The read-modify-write state machine is configured to perform read, modify, and write operations on the register value of the target equalizer based on the target equalizer register address through the dynamic reconfiguration interface of the physical layer transceiver. After each write operation, it sends a re-evaluation trigger signal to the online monitoring module to trigger it to re-evaluate the same monitoring sampling point.

[0033] In this invention, the parameter adjustment module further achieves self-repair of underlying parameters through a blind tuning optimization logic of "detection-modification-verification-direction discrimination".

[0034] Specifically, the read-modify-write state machine is configured to increment or decrement the register value of the target equalizer by 1 according to the direction instruction contained in the adjustment enable signal.

[0035] Furthermore, the read-modify-write state machine is configured to perform an increment operation by default when performing the first modification operation on the register value of the target equalizer.

[0036] Furthermore, the read-modify-write state machine is configured to: record the current link error count as a first reference value before each modification operation; after performing the modification operation and triggering the online monitoring module to re-evaluate, obtain a new link error count as a second reference value; and based on the comparison result between the first reference value and the second reference value, determine whether the adjustment direction is correct, and decide the direction command for the next adjustment accordingly.

[0037] Furthermore, the read-modify-write state machine is configured such that: if the second reference value is less than the first reference value, the adjustment direction is determined to be correct, and subsequent adjustments continue to receive the direction instructions from the self-repair decision module; if the second reference value is greater than or equal to the first reference value, the adjustment direction is determined to be incorrect, and subsequent adjustments will reverse to receive the direction instructions from the self-repair decision module.

[0038] Furthermore, the read-modify-write state machine is configured to: when the second reference value is lower than a preset repair completion threshold, determine that the repair is complete and stop the adjustment operation; and after determining that the repair is complete, send an instruction to the online monitoring module to resume polling monitoring.

[0039] According to some specific implementations, the repair completion threshold is set to correspond to a local bit error rate of 10.-3 The number of bit errors is on the order of magnitude.

[0040] A second aspect of the present invention provides an FPGA accelerator card, which includes the PCIe link monitoring and self-repair system for FPGA accelerator cards described above.

[0041] A third aspect of this invention provides a PCIe link monitoring and self-repair method for FPGA accelerator cards, comprising the following steps:

[0042] The signals of the same PCIe physical channel are sampled in parallel, wherein the main sampler is anchored to the center sampling point locked by the clock data recovery circuit for continuous sampling, and the offset sampler performs programmable offset sampling relative to the center sampling point in a two-dimensional voltage and time coordinate system.

[0043] After the link enters the working state, the offset sampler is controlled to scan along the voltage axis and time axis passing through the center sampling point, and the eye diagram boundary is determined according to the sampling comparison result between the offset sampler and the main sampler.

[0044] Multiple monitoring sampling points are calculated based on a preset safety margin;

[0045] The offset sampler is controlled to perform polling sampling at the multiple monitoring sampling points;

[0046] During the dwell monitoring period of a single monitoring sampling point, when the number of bit errors generated by the sampling comparison between the offset sampler and the main sampler exceeds the warning threshold, the link status is determined to be abnormal, the polling sampling is interrupted and suspended, and a repair trigger signal containing the location information of the current abnormal monitoring sampling point is generated.

[0047] The physical layer distortion type is determined based on the current monitoring sampling point location information in the repair trigger signal, and a corresponding distortion type encoding signal is generated.

[0048] The target equalizer is determined based on the distortion type encoded signal;

[0049] Using the monitoring results from polling sampling as feedback, the parameters of the target equalizer are iteratively adjusted through the physical layer transceiver until the monitoring results continuously determine that the link status is normal.

[0050] In some implementations, determining the eye diagram boundary based on the sampling comparison result between the offset sampler and the main sampler includes:

[0051] When the offset sampler is located at each scan coordinate point, the output data of the offset sampler and the main sampler are compared bit by bit in real time and the bit error is accumulated to obtain the number of bit errors of a single scan coordinate point in the resident monitoring period.

[0052] The number of bit errors is compared with a preset boundary determination threshold. If the number of bit errors reaches or exceeds the boundary determination threshold, the scan coordinate point is determined to be the eye diagram limit boundary coordinate.

[0053] Based on the determined eye diagram limit boundary coordinates, a preset voltage safety margin or time safety margin is shrunk inward to calculate the corresponding monitoring sampling points.

[0054] In some implementations, controlling the offset sampler to perform a scan includes:

[0055] A dynamically adjustable voltage bias is provided to the offset sampler via a programmable voltage bias circuit;

[0056] A dynamically adjustable phase bias is provided to the offset sampler via a programmable phase bias circuit.

[0057] Furthermore, the offset sampler is controlled to perform step scanning along the voltage axis and the time axis with preset step sizes, with the center sampling point as the origin.

[0058] Furthermore, the step scan is an adaptive step scan, including:

[0059] The scanning step size is dynamically adjusted based on the comparison between the detected number of bit errors and a preset threshold: if the number of bit errors is lower than the preset threshold, a first scanning step size is used; if the number of bit errors reaches or exceeds the preset threshold, a second scanning step size smaller than the first scanning step size is used.

[0060] In some implementations, the dwell time of the offset sampler at a single scan coordinate point is dynamically controlled based on the statistical confidence requirement of the target bit error rate.

[0061] And / or, before the scan begins, perform zero-point calibration on the voltage bias path of the offset sampler.

[0062] In some implementations, controlling the offset sampler to perform polling sampling at the plurality of monitoring sampling points includes controlling the offset sampler to perform sampling at the monitoring sampling points sequentially in a time-division multiplexing manner.

[0063] Furthermore, within the dwell time monitoring period of a single monitoring sampling point, including:

[0064] The outputs of the offset sampler and the main sampler are compared bit by bit in real time and the bit error is accumulated to obtain the bit error count of the monitoring sampling point.

[0065] At the end of the resident monitoring period, the number of bit errors is compared with the warning threshold:

[0066] If the number of bit errors is less than the warning threshold, then the offset sampler is controlled to poll the next monitoring sampling point;

[0067] If the number of bit errors reaches or exceeds the warning threshold, the polling is interrupted and the repair trigger signal is generated.

[0068] Furthermore, it also includes: after generating the repair trigger signal, pausing polling sampling and entering a waiting state until a re-evaluation trigger signal is received.

[0069] In some implementations, the plurality of monitoring sampling points includes four, which correspond to the upper and lower boundaries of the eye diagram in the voltage direction and the left and right boundaries in the time direction, respectively, and the coordinates of each monitoring sampling point have been reduced inward by a preset safety margin.

[0070] In some implementations, determining the physical layer distortion type based on the repair trigger signal includes:

[0071] Based on the monitoring sampling point location information in the repair trigger signal, determine the coordinate axis to which the current abnormal monitoring sampling point belongs;

[0072] The coordinate axes are mapped to the corresponding physical layer distortion types, where the voltage axis is mapped to amplitude attenuation and the time axis is mapped to phase jitter.

[0073] Generate a distortion type coded signal for identifying the amplitude attenuation or phase jitter using a multi-bit code.

[0074] Furthermore, it also includes: generating an adjustment enable signal while generating the distortion type encoded signal, the adjustment enable signal containing a direction instruction indicating to perform an increment or decrement operation on the register value of the target equalizer.

[0075] Further, determining the target equalizer based on the distortion type encoded signal includes:

[0076] The target equalizer register address is mapped according to the distortion type encoded signal, wherein amplitude attenuation is mapped to the address of the continuous-time linear equalizer control register, and phase jitter is mapped to the address of the decision feedback equalizer control register.

[0077] Furthermore, iteratively adjusting the parameters of the target equalizer includes:

[0078] Based on the target equalizer register address obtained through mapping, an adjustment loop consisting of the following steps is executed through the dynamic reconfiguration interface of the physical layer transceiver:

[0079] Read the current register value of the target equalizer;

[0080] Based on the direction command, the read register value is modified by incrementing or decrementing by 1;

[0081] Write the modified value back to the target equalizer register;

[0082] Send a reassessment trigger signal to trigger a reassessment of the same monitoring sampling point.

[0083] Furthermore, the adjustment loop is an adaptive adjustment loop, and also includes:

[0084] Before each modification operation, record the current link error count as the first reference value;

[0085] After triggering a reassessment, the new link error count is obtained as a second reference value;

[0086] The first reference value is compared with the second reference value to determine whether the adjustment direction is correct, and the direction command for the next adjustment is decided accordingly.

[0087] Specifically, determining whether the adjustment direction is correct includes:

[0088] If the second reference value is less than the first reference value, the adjustment direction is determined to be correct, and the direction command for subsequent adjustments is maintained;

[0089] If the second reference value is greater than or equal to the first reference value, the adjustment direction is determined to be incorrect, and the subsequent adjustment direction command is reversed.

[0090] More specifically, the exit condition of the adaptive adjustment cycle is: the second reference value is lower than the preset repair completion threshold; when the exit condition is met, the repair is determined to be completed and the adjustment is stopped, and the polling monitoring of multiple monitoring sampling points is resumed.

[0091] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:

[0092] This invention's PCIe link monitoring and self-repair system abandons traditional two-dimensional traversal imaging, achieving rapid eye diagram boundary detection through a dual-sampler architecture and linear scanning, significantly reducing resource overhead. It utilizes a single sampler to poll multiple fixed key monitoring points, enabling 24 / 7 online health monitoring without service interruption. Adaptive repair is achieved through a repair decision module and a parameter adjustment module. This invention constructs a complete "perception-diagnosis-repair" autonomous system within the FPGA accelerator card, independent of the CPU and external software, realizing a closed-loop process from online monitoring to autonomous repair, significantly improving the long-term stability and service continuity of high-speed links under complex operating conditions. Attached Figure Description

[0093] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0094] Figure 1 This is a schematic diagram of the PCIe link monitoring and self-healing system provided in Example 1;

[0095] Figure 2 This is a schematic diagram of the workflow of the PCIe link monitoring and self-healing system provided in Example 1. Detailed Implementation

[0096] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0097] It should be noted that the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product or device.

[0098] Example 1: This example provides a PCIe link monitoring and self-repair system for FPGA accelerator cards, which performs PCIe link monitoring and self-repair methods for FPGA accelerator cards.

[0099] like Figure 1 As shown, the PCIe link monitoring and self-repair system for FPGA accelerator cards in this embodiment includes a signal acquisition module, a monitoring point calibration module, an online monitoring module, a repair decision module, and a parameter adjustment module.

[0100] The signal acquisition module includes a main sampler and an offset sampler, which are configured to sample signals from the same PCIe physical channel in parallel. The main sampler is configured to continuously sample from a center sampling point locked by a clock data recovery circuit, and the offset sampler is configured to perform programmable offset sampling relative to the center sampling point in a voltage and time two-dimensional coordinate system.

[0101] The monitoring point calibration module is connected to the signal acquisition module. After the link enters the working state, it controls the offset sampler to scan along the voltage axis and time axis passing through the center sampling point. The eye diagram boundary is determined based on the sampling comparison results between the offset sampler and the main sampler, and multiple monitoring sampling points are calculated based on the preset safety margin.

[0102] The repair decision module is connected to the online monitoring module and is configured to receive repair trigger signals, determine the physical layer distortion type based on the current monitoring sampling point location information, and output the corresponding distortion type encoding signal.

[0103] The parameter adjustment module, connected to the repair decision module, the online monitoring module, and the physical layer transceiver, is configured to receive distortion type encoded signals, determine the target equalizer based on the physical layer distortion type, use the monitoring results output by the online monitoring module as feedback, and iteratively adjust the parameters of the target equalizer through the physical layer transceiver until the online monitoring module continuously determines that the link status is normal.

[0104] like Figure 2 As shown, the PCIe link monitoring and self-healing method for FPGA accelerator cards in this embodiment includes the following steps:

[0105] The signals of the same PCIe physical channel are sampled in parallel. The main sampler is anchored to the center sampling point locked by the clock data recovery circuit for continuous sampling, and the offset sampler performs programmable offset sampling relative to the center sampling point in a two-dimensional voltage and time coordinate system.

[0106] After the link enters the working state, the control offset sampler scans along the voltage axis and time axis passing through the center sampling point, and determines the eye diagram boundary based on the sampling comparison results between the offset sampler and the main sampler;

[0107] Multiple monitoring sampling points are calculated based on a preset safety margin;

[0108] The control offset sampler performs polling sampling at multiple monitoring sampling points;

[0109] During the dwell monitoring period of a single monitoring sampling point, when the number of bit errors generated by the sampling comparison between the offset sampler and the main sampler exceeds the warning threshold, the link status is determined to be abnormal, the polling sampling is interrupted and paused, and a repair trigger signal containing the location information of the current abnormal monitoring sampling point is generated.

[0110] The physical layer distortion type is determined based on the current monitoring sampling point location information in the repair trigger signal, and the corresponding distortion type encoding signal is generated.

[0111] Determine the target equalizer based on the distortion type coded signal;

[0112] Using the monitoring results from polling sampling as feedback, the parameters of the target equalizer are iteratively adjusted through the physical layer transceiver until the monitoring results continuously determine that the link status is normal.

[0113] The following provides a more detailed description of the module settings and operating methods of the PCIe link monitoring and self-healing system in this embodiment.

[0114] Specifically, in the signal acquisition module, the determination of the center origin depends on the state of the physical layer (PHY), which is automatically found and locked by the underlying hardware circuit—the Clock Data Recovery (CDR). When the PCIe device completes the link training (LTSSM process), the signal quality reaches the communication standard, and enters the L0 state, the physical layer sets the link ready signal (user_lnk_up == 1), and the main sampler is directly fixed at the current locked value of the CDR. This position is defined by the logic layer as coordinates (0,0), i.e., the center sampling point. The offset sampler can be implemented using RTL code to perform step scans on the time axis and voltage axis (or simply horizontal and vertical scans), which will be explained in detail below.

[0115] Specifically, the monitoring point calibration module includes an error detection unit and a monitoring sampling point calibration unit. The error detection unit is configured to use XOR logic to perform real-time bit-by-bit comparison of the output data of the offset sampler and the main sampler when the offset sampler is located at each scanning coordinate point, and count the inconsistencies to obtain the number of bit errors of a single scanning coordinate point within the dwell listening period. The monitoring sampling point calibration unit is configured to compare the number of bit errors of a single scanning coordinate point within the dwell listening period with a preset boundary judgment threshold. When the number of bit errors reaches or exceeds the boundary judgment threshold, the scanning coordinate point is determined to be the eye diagram limit boundary coordinate. For the determined eye diagram limit boundary coordinate, a preset voltage safety margin or time safety margin is shrunk inward to calculate the corresponding monitoring sampling point.

[0116] The monitoring point calibration module includes a voltage regulation module, a phase regulation module, a scan control unit, and a dwell time monitoring period control unit. The voltage regulation module includes a programmable digital-to-analog converter for providing a dynamically adjustable voltage bias to the offset sampler. The phase regulation module includes a programmable phase interpolator for providing a dynamically adjustable phase bias to the offset sampler. The scan control unit is configured to control the offset sampler to perform step scans along the voltage axis and time axis with preset step sizes, with the center sampling point as the origin. The dwell time monitoring period control unit is configured to dynamically control the dwell time monitoring duration of the offset sampler at a single scan coordinate point based on the statistical confidence requirement of the target bit error rate.

[0117] In an embodiment, the scanning control unit is configured to control the offset sampler to perform adaptive step scanning. The adaptive step scanning includes: dynamically adjusting the scanning step size based on the comparison result of the detected number of bit errors and a preset threshold: if the number of bit errors is lower than the preset threshold, a first scanning step size is used; if the number of bit errors reaches or exceeds the preset threshold, a second scanning step size smaller than the first scanning step size is used.

[0118] In this embodiment, the scanning control unit controls the offset sampler to perform step scanning in a predetermined order, starting from the center sampling point, along the voltage increase direction, voltage decrease direction, phase delay direction, and phase advance direction, based on a preset scanning trajectory plan, thereby systematically completing the detection of the four boundaries of the eye diagram: upper, lower, left, and right.

[0119] In the embodiment, both the voltage regulation module and the phase regulation module include clamping circuits in their control logic to prevent control commands from going out of bounds and causing control codes to wrap around.

[0120] In this embodiment, the specific scanning parameters of the offset sampler in the time and voltage two-dimensional coordinate system and the mechanisms and operations involved in the calibration of monitoring points are as follows:

[0121] (1) Scan range

[0122] In the vertical direction (voltage scan control), the voltage regulation module includes a multi-bit high-precision digital-to-analog converter (DAC, specifically an N-bit current-controlled DAC), whose output is coupled to the reference voltage input of the offset sampler, configured to provide a dynamically adjustable comparison threshold voltage to the offset sampler. The voltage scan range is configured to cover a preset dynamic reception range of the input signal; that is, the most significant bit (MSB) of the DAC is configured as a polarity control bit to indicate a positive or negative voltage offset; the remaining N-1 bits are configured as amplitude control bits. In this embodiment, the absolute physical scan range of the comparison threshold voltage can reach ±(2π / 4)π / 4. N-1 -1)*V LSB ,in VLSB This is the base physical voltage corresponding to the least significant bit of the digital-to-analog converter. In this embodiment, the voltage regulation module is also coupled with an offset calibration logic. Before starting the eye diagram scan cycle, the offset calibration logic is configured to inject compensation control codes into the digital-to-analog converter to eliminate the inherent offset voltage of the comparator, ensuring that when the control code is zero, the comparison threshold voltage is strictly aligned with the true zero level of the input signal. The step size of the voltage scan can be dynamically programmed by the system firmware to K LSBs (where K>1) to achieve a balance between scan accuracy and scan time.

[0123] In the horizontal direction (time scan control), the phase adjustment module includes a high-precision phase interpolator (PI), coupled to the clock input of the offset sampler, configured to dynamically adjust the phase offset of the offset sampling clock. The time scan range is configured to cover at least one complete unit interval (UI). The phase interpolator employs a quadrant-segmented control architecture, dividing a single unit interval into M phase steps (M=64 in this embodiment). Starting from the phase of the center sampling point (i.e., 0 UI), a full-cycle phase traversal from -0.5 UI to +0.5 UI is achieved by sequentially incrementing or decrementing digital control codes into the phase interpolator. The absolute time step of the phase adjustment module is inversely proportional to the current high-speed link's operating baud rate. In high-speed communication mode, the physical time step corresponding to a single control code step (1 LSB) can reach the picosecond (ps) level. This configuration enables the offset sampler to capture high-resolution monitoring capabilities for high-frequency jitter and minute phase shifts.

[0124] (2) Sampling residency and monitoring mechanism

[0125] The dwell time control unit includes a programmable dwell counter or a configurable timer. When the offset sampler steps to any target coordinate point (i.e., a "step") in a two-dimensional scan grid consisting of time and voltage dimensions, the dwell time control unit is configured to control the offset sampler to maintain a preset dwell time at that target coordinate point.

[0126] This embodiment configures the number of samples based on confidence level: the resident monitoring period control unit is determined by the number of sampling bits N during system operation. To meet the confidence level requirements of the target bit error rate (BER) in different test scenarios, the value of N is dynamically adjustable. Specifically, the system provides a configuration register that allows external main control logic or firmware to adjust the total number of samples within a single-point monitoring time (e.g., configured as 10 in the fast contour scan mode in this embodiment). 5 One bit period; configured as 10 in deep error detection mode. 9 (more than one bit cycle). This configuration allows the system to make flexible trade-offs between scanning accuracy and overall scanning time.

[0127] (3) Real-time error comparison and accumulation mechanism

[0128] The outputs of the offset sampler and the main sampler are coupled to the error detection unit. A bit-by-bit XOR comparison is used: within a preset dwell listening period, the XOR logic unit in the error detection module is configured to receive and compare the decision output data of the offset sampler under the current bias condition with the unbiased decision output data of the main sampler at the sampling origin. This comparison process is performed bit-by-bit in real time at the hardware level of the data stream. Error counting: The error detection unit further includes a hardware error counter, whose trigger is coupled to the output of the XOR logic unit. The XOR logic unit outputs a valid pulse only when the decision output of the offset sampler is inconsistent with the output of the main sampler, triggering the error counter to increment by one. Thus, at the end of a single dwell listening period, the accumulated value in the error counter represents the number of errors at the target coordinate point. In this embodiment, to ensure the effectiveness of data comparison, the XOR judgment logic for the sampling results of the main sampler and the offset sampler is as follows: the main sampler and the offset sampler are connected in parallel to the physical layer analog front-end (AFE) to jointly receive the same known high-speed input code stream. The main sampler uses the center-optimal clock locked by the Clock Data Recovery (CDR) circuit for decision-making and outputs standard reference data; the offset sampler makes decisions on the same bit under a set voltage step or phase offset. After the digital sampling outputs of both are clocked in the internal clock domain, they are synchronously input to the hardware XOR gate. If the decision results for the same bit are consistent, the XOR output is 0, indicating that the offset coordinate is still within the safe area of ​​the open eye diagram, and the system instructs the offset sampler to continue scanning outwards; if the decision results are inconsistent, the XOR output is 1, and the internal hardware counter records a bit error.

[0129] In this embodiment, to automate the scanning process and ensure reliable data extraction, the scanning control unit integrates a Scan FiniteState Machine (FSM) that communicates with the resident monitoring cycle control unit and the error detection unit. This FSM features latch enable triggering: when the resident monitoring cycle control unit determines that the preset sampling bit count N for the current target coordinate point has been exhausted (i.e., the monitoring time for the current step has ended), the FSM is configured to generate an internal latch enable signal. Data reading and reset: Based on the latch enable signal, the data latch or pass-through memory interface within the system is triggered to read and save the currently registered bit error count of the error counter. After data latching is completed, the FSM is further configured to send a reset signal to the error counter to reset its count value. Stepping drive: After confirming that the counter is cleared and the data has been safely latched, the scanning state machine, according to the preset two-dimensional scanning trajectory plan, synchronously sends a step update command to the voltage regulation module (such as DAC control logic) and / or phase adjustment module (such as PI control logic) in the system, driving the offset sampler to step to the next two-dimensional coordinate point and starting a new round of resident monitoring and bit error statistics cycle.

[0130] (4) Adaptive dynamic scanning and step size adjustment mechanism

[0131] In this embodiment, the scanning control unit includes an adaptive scanning controller, which works in conjunction with the scanning state machine to control the scanning process. The adaptive scanning controller is configured with two scanning states: coarse adjustment scanning mode (using the first scanning step size) and fine adjustment scanning mode (using the second scanning step size).

[0132] In coarse scan mode, the adaptive scan controller sends a large first preset step size command to the voltage adjustment module or phase adjustment module (e.g., in this embodiment, the voltage step size is configured as 4 LSB and the time step size as 1 / 16 UI) to drive the offset sampler to perform rapid leapfrog steps in the two-dimensional coordinate system. Simultaneously, the dwell listening period control unit is configured to use a shorter first dwell listening period (10 in this embodiment). 5 (bit cycles) to accelerate the traversal of error-free regions.

[0133] In fine-tuned scanning mode, the scanning strategy is dynamically reconfigured: the adaptive scanning controller instructs the voltage adjustment module or phase adjustment module to reduce the scanning step size to a second preset step size (typically the minimum resolution supported by the hardware; in this embodiment, it is a voltage step of 1 LSB and a phase step of 1 / 128 UI), thereby performing point-by-point dense scanning at the eye diagram edge. Simultaneously, the dwell time monitoring control unit extends the dwell time at the current coordinate point to a second preset monitoring time (where the second preset monitoring time is significantly longer than the first preset monitoring time) to capture low-probability bit error events (10 in this embodiment). 9 One bit period to detect 10 -9 (Level of deep error profile), ensuring high confidence in boundary test data.

[0134] In this embodiment, the adaptive scan controller includes a hardware or firmware-implemented threshold comparison logic unit with edge band detection: after the dwell listening cycle at each scan coordinate point ends, the threshold comparison logic unit reads the number of errors latched by the error counter in real time and compares it with a pre-programmed error threshold (e.g., set to 10 errors in this embodiment). Adaptive speed reduction: when the number of errors is greater than or equal to the preset error threshold for the first time, the system determines that the current scan trajectory has touched or entered the edge transition band or jitter distribution area of ​​the eye diagram. At this time, the threshold comparison logic unit immediately generates a mode switching interrupt signal. In response to the interrupt signal, the adaptive scan controller automatically switches from coarse-tuning scan mode to fine-tuning scan mode. When the scan trajectory crosses the transition band, and the cumulative error rate of multiple consecutive coordinate points recovers to 90% (i.e., completely enters the closed eye area) or drops back to zero (i.e., enters the next effective eye diagram cycle), the adaptive scan controller can switch back to coarse-tuning scan mode according to a predetermined algorithm.

[0135] In this embodiment, the clamping circuit is configured to: when the step instruction issued by the scanning state machine causes the requested voltage or phase value to exceed the maximum / minimum physical extreme value of the digital-to-analog converter or the phase interpolator, intercept the out-of-bounds instruction, hold and clamp the output control signal at the current physical extreme value, and trigger the setting of the overflow / underflow flag.

[0136] (5) Monitoring and sampling point calibration

[0137] The monitoring sampling point calibration unit is configured to compare the number of bit errors of a single scan coordinate point within the dwell monitoring period with a preset boundary judgment threshold. If the number of bit errors reaches or exceeds the boundary judgment threshold (in this embodiment, the boundary judgment threshold is 100 times, i.e., the equivalent local bit error rate is approximately 10), the unit will detect the error. -3The system identifies this location as the physical boundary of the eye diagram and extracts and latches the current voltage or time coordinates as the limit coordinates. Subsequently, based on these limit coordinates and the set safety margin (in this embodiment, the time boundary is shrunken inward by 0.05 UI, and the voltage boundary is shrunken inward by 20 mV), the absolute value of the limit coordinates is subtracted from the safety margin to calculate the final monitoring sampling point coordinates, which are stored in the probe coordinate register unit of the online monitoring module for subsequent real-time polling monitoring.

[0138] In this embodiment, after calibrating the monitoring probe, the system enters 24 / 7 PCIe link monitoring and self-repair, and includes an online monitoring module, a repair decision module, and a parameter adjustment module.

[0139] Specifically, the online monitoring module is connected to the monitoring point calibration module and the signal acquisition module, and is configured to control the offset sampler to perform polling sampling at multiple monitoring sampling points. During the dwell listening period of a single monitoring sampling point, when the number of bit errors generated by the sampling comparison between the offset sampler and the main sampler exceeds the warning threshold, the link status is determined to be abnormal, the polling sampling is interrupted and paused, and a repair trigger signal containing the current monitoring sampling point location information is output.

[0140] In this embodiment, the online monitoring module includes a probe coordinate register unit and a polling control unit. The probe coordinate register unit stores the coordinates of multiple monitoring sampling points. The polling control unit is configured to control the offset sampler to sequentially poll the monitoring sampling points in a time-division multiplexing manner. More specifically, the polling control unit includes a timer configured to control the dwell period of the offset sampler at a single monitoring sampling point. The polling control unit is configured to perform real-time bit-by-bit comparison between the output of the offset sampler and the main sampler using XOR logic within the dwell period of a single monitoring sampling point, and count the inconsistencies to obtain the number of bit errors at a single monitoring sampling point within the dwell period. The online monitoring module includes a comparison unit configured to compare the number of bit errors at a single monitoring sampling point within the dwell period with a warning threshold at the end of the dwell period of a single monitoring sampling point. The polling control unit is configured to: when the number of bit errors is less than the warning threshold, control the offset sampler to poll to the next monitoring sampling point; when the number of bit errors reaches or exceeds the warning threshold, interrupt the polling and generate a repair trigger signal.

[0141] In this implementation, the probe coordinate register unit stores four monitoring sampling points, corresponding to the upper and lower boundaries of the eye diagram in the voltage direction and the left and right boundaries in the time direction, respectively. The coordinates of each monitoring sampling point have been reduced inwards by a preset safety margin. Specifically: the top voltage coordinate P... top (0, V) top Bottom voltage coordinate P bot (0, V) bot ), left phase coordinate Pleft (T) left ,0) and the right-side phase coordinate P right (T) right ,0).

[0142] Specifically, the repair decision module is a combinational logic circuit, which is configured to determine the coordinate axis to which the current monitoring sampling point is located based on the current monitoring sampling point location information in the repair trigger signal, and map the coordinate axis to the corresponding physical layer distortion type: if it belongs to the voltage axis, it is determined to be amplitude attenuation, and if it belongs to the time axis, it is determined to be phase jitter.

[0143] Specifically, the distortion type encoding signal output by the repair decision module is a multi-bit code used to identify two types of distortion: amplitude attenuation and phase jitter. The repair decision module is also configured to output an adjustment enable signal to the parameter adjustment module simultaneously with the output distortion type encoding signal. The adjustment enable signal contains a direction instruction indicating whether to increment or decrement the register value of the target equalizer by 1.

[0144] Specifically, the parameter adjustment module includes an address mapping unit and a read-to-write state machine. The address mapping unit is configured to receive distortion type encoded signals and, based on the determined physical layer distortion type, output the corresponding target equalizer address: when the distortion type encoded signal indicates amplitude attenuation, it outputs the address of the continuous-time linear equalizer control register; when the distortion type encoded signal indicates phase jitter, it outputs the address of the decision feedback equalizer control register. The read-to-write state machine is configured to perform read, modify, and write operations on the target equalizer register value based on the target equalizer register address via the physical layer transceiver's dynamic reconfiguration interface. After each write operation, it sends a re-evaluation trigger signal to the online monitoring module to trigger a re-evaluation of the same monitoring sampling point. The read-to-write state machine is configured to increment or decrement the target equalizer register value by 1 according to the direction command contained in the adjustment enable signal. Specifically, the read-modify-write state machine is configured as follows: before each modification operation, the current link error count is recorded as a first reference value; after the modification operation is performed and the online monitoring module is triggered to re-evaluate, a new link error count is obtained as a second reference value; based on the comparison result between the first and second reference values, it is determined whether the adjustment direction is correct, and the direction command for the next adjustment is determined accordingly. If the second reference value is less than the first reference value, the adjustment direction is determined to be correct, and subsequent adjustments will continue to receive the direction command from the self-repair decision module; if the second reference value is greater than or equal to the first reference value, the adjustment direction is determined to be incorrect, and subsequent adjustments will reverse to receive the direction command from the self-repair decision module. When the second reference value is lower than a preset repair completion threshold, the repair is determined to be complete and the adjustment operation is stopped. After the repair is determined to be complete, a command to resume polling monitoring is sent to the online monitoring module.

[0145] In this embodiment, the workflow after entering 24 / 7 online monitoring and self-repair is as follows:

[0146] S1.1: The coordinates of the monitoring sampling points obtained from the previous-level monitoring probe calibration module are written into the corresponding boundary registers (Y-max, Y-min, X-left, X-right) in the probe coordinate register unit via the internal bus. The time-division multiplexing polling state machine of the polling control unit is started, driving the offset sampler to the first monitoring sampling point (in this embodiment, the top voltage coordinate P) top (Serving as the anchor point for the current testing cycle).

[0147] S1.2: Single-point stationary monitoring and real-time error accumulation

[0148] The timer (a 1ms hardware timer is used in this embodiment) is triggered and starts counting down. During this 1ms single-point dwell listening period: the offset sampler and the main sampler simultaneously sample and decide on the same known input bitstream; the digital outputs of both are synchronously input to the hardware XOR gate; if the decision results for the same bit are inconsistent (i.e., the XOR output is 1), a valid error pulse is generated; the trigger terminal of the error accumulator receives the valid pulse and performs an "increment" operation (i.e., the accumulated error count increments by 1).

[0149] S1.3: Threshold determination and state splitting at the end of the cycle (1ms arrival)

[0150] When the timer countdown reaches zero, the single-session listening ends. The comparator in the comparison unit immediately reads the current count value of the bit error accumulator and compares it with the preset bit error threshold (set to 100 bit errors in this embodiment, which is equivalent to approximately 10). -3 Compare with the local bit error rate:

[0151] Scenario A (Safe State: No Significant Distortion): If the number of bit errors is less than 100, it indicates that there is normal random noise in the current link, but no out-of-bounds noise has occurred. In this case, the time-division multiplexing polling state machine sends a reset signal to the bit error accumulator and drives the offset sampler to the next coordinate in the probe coordinate register (e.g., switching from Ptop to Pbot) in the next clock cycle. The timer resets and restarts the 1ms countdown, and the system seamlessly enters the next monitoring sampling point for sampling.

[0152] Scenario B (Abnormal State: Triggering Adaptive Adjustment): If the number of bit errors is greater than or equal to 100, it indicates that the eye diagram profile has deteriorated significantly and has reached the safety warning line of the current probe. At this time, the online monitoring module immediately interrupts the normal four-point polling operation and executes the following hardware-level abnormal response logic:

[0153] Turn off polling timer: Stop the 1ms countdown and temporarily stop the offset sampler at the current error monitoring sampling point so that the effect of fixed-point repair can be verified later.

[0154] Issue an error ID vector: Convert the spatial location of the current monitoring sampling point into a 4-bit wide error flag vector (probe_err_flag[3:0]), for example, outputting

[0001] represents P. top If the boundary is exceeded, it will be sent to the next level "Repair Decision Module" for pure combinational logic diagnosis.

[0155] Raise the Error Interrupt line: Send an interrupt alarm to the subsequent parameter adjustment module, triggering the DRP adjustment mechanism of the underlying physical layer (PHY) parameters.

[0156] Entering Wait State: The time-division multiplexing polling state machine enters a sleep waiting mode until the parameter adjustment module completes a DRP parameter read / write operation and returns a re-evaluation enable signal line (re_eval_trigger = 1'b1) before waking up this module to re-measure the parameters of the current monitoring sampling point.

[0157] The repair decision module performs the following operations:

[0158] S2.1: Input and Classification of Probe Error Identification: Identify monitoring sampling points based on the error identification vector from S1.2. The corresponding relationships include:

[0001] Top voltage monitoring sampling point alarm (P) top )

[0010] Alarm at bottom voltage monitoring sampling point (P) bot )

[0100] Alarm at the left-side phase monitoring sampling point (P) left )

[1000] Alarm at the right-side phase monitoring sampling point (P) right ) S2.2: Fault Classification and Judgment of Pure Combinational Logic Map the spatial boundary violation physical phenomenon of the monitoring sampling points to the underlying link distortion type: Amplitude attenuation diagnostic logic: A vertical error signal, V, is obtained through a logic OR gate. err = P top OR Pbot If V err = 1, directly diagnosed as a significant signal amplitude attenuation in the link (e.g., caused by high-frequency loss of the trace or ambient temperature rise). Phase jitter diagnostic logic: A horizontal error signal, H, is obtained through another logic OR gate. err = P left OR P right If H left = 1 indicates that the link has severe phase jitter or inter-symbol interference (ISI). S2.3: Output distortion type encoding signal and adjustment enable signal to the parameter adjustment module: Employing a stateless design, it does not calculate the absolute compensation value, but instead generates distortion type encoded signals and adjustment enable signals, delegating the actual accumulation process to the subsequent parameter adjustment module. Distortion type encoded signal: includes first addressing signal and second addressing signal. When the combinational logic determines that the amplitude is attenuated (Verr = 1), the compensation target is pointed to the gain control register of the continuous time linear equalizer (CTLE), that is, the first addressing signal is sent; when it is determined that the phase jitter is 1, the compensation target is pointed to the first tap control register of the decision feedback equalizer (DFE), that is, the second addressing signal is sent. Adjustment enable signal: The combinational logic directly sends a unit step adjustment enable signal to the subsequent parameter adjustment module. In this embodiment, the single compensation amount is fixed as one least significant bit (1 LSB) of the target register, such as a gain level of CTLE or a first-order weight of the DFE tap. The parameter adjustment module performs the following operations: S3.1: Fault Reception and Register Addressing: After receiving the distortion type encoding signal from the previous stage, the multiplexer (MUX) of the address mapping unit immediately maps the target physical address of the DRP to the corresponding register of the target equalizer. Taking the receipt of the first addressing signal as an example, the multiplexer immediately maps the target physical address of the DRP to the gain control register of the continuous time linear equalizer (CTLE). S3.2: Historical Data Latching and Initial Probe (Default +1): The read-to-write state machine reads the current baseline configuration value of the CTLE register through the DRP interface (e.g., in this embodiment, the current gain level is binary code 0100, i.e., decimal 4). At this time, the read-to-write state machine stores the number of alarm errors reported in step S1.3 (e.g., in this embodiment, 150 errors are generated within a 1ms dwell monitoring period, exceeding the set safety threshold of 100 errors) into the historical error register Error0 (i.e., Error0 = 150, the first reference value). Subsequently, the read-to-write state machine performs the default initial compensation operation: pulls up the direction flag bit (DIR = 1) to control the internal arithmetic unit to perform an addition operation. Under the protection of the bit mask, the value of CTLE is modified to 0101 (i.e., 4 + 1 LSB = 5), and written back to the PHY hard core through the DRP interface. S3.3: Hardware Wake-up and Reassessment: After modifying the CTLE register value, the read-write state machine enters a waiting state and sends an enable pulse to the online monitoring module (pulling down the error interrupt line and setting a reassessment trigger signal). This pulse forces the timer and bit error accumulator of the polling control unit to be completely cleared, and restarts a 1ms listening countdown at the error monitoring sampling point to obtain the bit error rate under the new parameters. S3.4: Error Comparison and Direction Decision (Adaptive Optimization): After the 1ms re-evaluation, the online monitoring module returns a new number of bit errors, and the read-modify-write state machine stores it in the current bit error register Error1. Scenario A (Correct Compensation Direction): If the signal eye diagram reopens due to the increased CTLE gain, and Error1 is measured to be 80 (second reference value), the hardware comparator determines that Error1 < Error0 (80 < 150), indicating that the "+1" direction is correct. The read-modify-write state machine maintains DIR = 1 and continues to perform +1 compensation on the CTLE register value in the next cycle. Scenario B (Incorrect Compensation Direction or Overcompensation): If the false triggering is due to system noise, forcibly increasing the CTLE gain amplifies the high-frequency noise, leading to a deterioration of the eye diagram. Error1 is measured as 200 (second reference value). The hardware comparator determines that Error1 > Error0 (200 > 150), indicating that the wrong direction has been taken. The read-to-write state machine immediately flips DIR to 0, switching the internal arithmetic unit to subtraction mode. In the next cycle, the read-to-write state machine performs a -1 LSB operation on the read-back CTLE register value, reverting the parameter or even probing in the opposite direction. Repair Completion and Exit: The above "read-modify-write-retest" cycle is executed at high speed by pure hardware. When the latest test result is lower than the preset repair completion threshold (in this embodiment, the repair completion threshold is the same as the alarm threshold set above, for example, the number of bit errors measured drops to 10, which is far below 100 bit errors), the system determines that the link has been successfully repaired. The read-modify-write state machine then sends a sleep signal to DRP through another control line to stop the parameter modification operation and notifies the probe detection module to resume the standard four monitoring sampling points time-division multiplexing polling monitoring state. Example 2: This example provides an FPGA accelerator card, which includes the PCIe link monitoring and self-healing system for FPGA accelerator cards from Example 1. The above embodiments have the following advantages: Efficient non-graphical extraction of eye diagram parameters: Abandoning traditional CPU-based 2D image scanning and rendering methods, this approach anchors the eye diagram center using a master sampler and controls the offset sampler to perform linear step scans along the time and voltage axes. Hardware XOR logic is used to directly capture signal error thresholds, rapidly extracting core parameters such as eye width and eye height. This process, which involves thousands of samplings and complex post-processing, is compressed into efficient linear probing and boundary calculation, significantly reducing hardware resources and latency. A lightweight online monitoring mechanism based on time-division multiplexing polling: To overcome the limitation of the number of physical samplers, time-division multiplexing polling control is adopted. By controlling a single offset sampler, sampling is performed cyclically between four pre-calibrated key monitoring sampling points (e.g., lingering at each point for 1ms), enabling all-weather, non-intrusive health monitoring under full-speed operation of the business link, while ensuring real-time monitoring and greatly saving hardware resources. Zero-latency fault diagnosis logic: The repair decision module is implemented using stateless, clockless pure combinational logic circuits. This module directly receives alarm flags from monitoring sampling points reported by the online monitoring module, and instantaneously maps the location of the alarm monitoring sampling point to a specific physical damage type (such as amplitude attenuation or clock jitter) through hardware logic gates. This achieves zero-cycle latency and extreme lightweight fault diagnosis, completely avoiding the latency and overhead of software decoding. Intelligent adaptive closed-loop parameter adjustment and repair: Real-time online adjustment of equalizer parameters is achieved through dynamic reconfiguration of ports at the physical layer. The core read-write state machine integrates direction decision logic and historical error status registers, automatically triggering a re-evaluation of the same monitoring point after each parameter modification, and intelligently adjusting the subsequent adjustment direction based on the results. This "probe-modify-verify" closed loop based on gradient descent gives the system adaptive repair capabilities to cope with environmental changes and device aging, significantly enhancing the long-term robustness of the link. A complete on-chip autonomous closed-loop system: Unlike the traditional open-loop diagnostic model of "measurement-derivation-manual analysis," the above embodiment constructs a complete hardware autonomous closed loop within the FPGA chip, encompassing signal quality perception, real-time fault diagnosis, and autonomous parameter adjustment. This system operates independently of the CPU and host computer, integrating eye diagram analysis capabilities on-chip at extremely low cost. Furthermore, it achieves a leap from "monitoring and diagnosis" to "proactive repair," providing continuous quality assurance for core business processes without manual intervention. The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A PCIe link monitoring and self-healing system for FPGA accelerator cards, characterized in that: It includes: The signal acquisition module includes a main sampler and an offset sampler, configured to sample signals of the same PCIe physical channel in parallel. The main sampler is configured to continuously sample from a center sampling point locked by a clock data recovery circuit, and the offset sampler is configured to perform programmable offset sampling relative to the center sampling point in a voltage and time two-dimensional coordinate system. The monitoring point calibration module, connected to the signal acquisition module, is configured to control the offset sampler to scan along the voltage axis and time axis passing through the central sampling point after the link enters the working state. The eye diagram boundary is determined based on the sampling comparison result between the offset sampler and the main sampler, and multiple monitoring sampling points are calculated based on the preset safety margin. The online monitoring module, connected to the monitoring point calibration module and the signal acquisition module, is configured to control the offset sampler to perform polling sampling at multiple monitoring sampling points. During the dwell listening period of a single monitoring sampling point, when the number of bit errors generated by the sampling comparison between the offset sampler and the main sampler exceeds the warning threshold, the link status is determined to be abnormal, the polling sampling is interrupted and paused, and a repair trigger signal containing the current monitoring sampling point location information is output. The repair decision module, connected to the online monitoring module, is configured to receive the repair trigger signal, determine the physical layer distortion type based on the current monitoring sampling point location information, and output the corresponding distortion type encoding signal; The parameter adjustment module, connected to the repair decision module, the online monitoring module, and the physical layer transceiver, is configured to receive the distortion type encoding signal, determine the target equalizer based on the physical layer distortion type, use the monitoring results output by the online monitoring module as feedback, and iteratively adjust the parameters of the target equalizer through the physical layer transceiver until the online monitoring module continuously determines that the link status is normal.

2. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 1, characterized in that: The monitoring point calibration module includes an error detection unit and a monitoring sampling point calibration unit. The error detection unit is configured to use XOR logic to compare the output data of the offset sampler and the main sampler bit by bit in real time when the offset sampler is located at each scan coordinate point, and count the inconsistent results of the comparison to obtain the number of bit errors of a single scan coordinate point in the resident monitoring period. The monitoring sampling point calibration unit is configured to compare the number of bit errors of a single scan coordinate point within the dwell monitoring period with a preset boundary judgment threshold. When the number of bit errors reaches or exceeds the boundary judgment threshold, the scan coordinate point is determined to be the eye diagram limit boundary coordinate. For the determined eye diagram limit boundary coordinate, a preset voltage safety margin or time safety margin is shrunk inward to calculate the corresponding monitoring sampling point.

3. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 1, characterized in that: The monitoring point calibration module includes a voltage adjustment module and a phase adjustment module. The voltage adjustment module includes a programmable digital-to-analog converter for providing a dynamically adjustable voltage bias to the offset sampler. The phase adjustment module includes a programmable phase interpolator for providing a dynamically adjustable phase bias to the offset sampler.

4. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 2, characterized in that: The monitoring point calibration module includes a scanning control unit, which is configured to control the offset sampler to perform step scanning along the voltage axis and the time axis with a preset step size, with the center sampling point as the origin.

5. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 4, characterized in that: The scanning control unit is configured to control the offset sampler to perform adaptive step scanning, the adaptive step scanning including: dynamically adjusting the scanning step size according to the comparison result of the detected number of bit errors and a preset threshold: if the number of bit errors is lower than the preset threshold, a first scanning step size is used; if the number of bit errors reaches or exceeds the preset threshold, a second scanning step size smaller than the first scanning step size is used.

6. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 3, characterized in that: Both the voltage regulation module and the phase regulation module include clamping circuits in their control logic to prevent control commands from going out of bounds and causing control codes to wrap around.

7. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 1, characterized in that: The monitoring point calibration module includes a dwell listening period control unit, which is configured to dynamically control the dwell listening duration of the offset sampler at a single scan coordinate point based on the statistical confidence requirement of the target bit error rate. And / or, before the scan begins, perform zero-point calibration on the voltage bias path of the offset sampler to eliminate the comparator's inherent offset voltage.

8. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 1, characterized in that: The online monitoring module includes a probe coordinate register unit and a polling control unit. The probe coordinate register unit is used to store the coordinates of the multiple monitoring sampling points. The polling control unit is configured to control the offset sampler to poll the monitoring sampling points sequentially in a time-division multiplexing manner.

9. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 8, characterized in that: The polling control unit includes a timer configured to control the dwell period of the offset sampler at a single monitoring sampling point. The polling control unit is configured to perform real-time bit-by-bit comparison between the output of the offset sampler and the main sampler using XOR logic within the dwell period of a single monitoring sampling point, and count the inconsistent results of the comparison to obtain the number of bit errors at a single monitoring sampling point within the dwell period. The online monitoring module includes a comparison unit configured to compare the number of bit errors at a single monitoring sampling point during the dwell listening period with a warning threshold at the end of the dwell listening period. The polling control unit is configured to: when the number of bit errors is less than the warning threshold, control the offset sampler to poll to the next monitoring sampling point; when the number of bit errors reaches or exceeds the warning threshold, interrupt the polling and generate the repair trigger signal.

10. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 9, characterized in that: The polling control unit is also configured to pause polling sampling and enter a waiting state after generating the repair trigger signal, until a re-evaluation trigger signal is received from the parameter adjustment module.

11. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 8, characterized in that: The probe coordinate register unit stores four monitoring sampling points, which correspond to the upper and lower boundaries of the eye diagram in the voltage direction and the left and right boundaries in the time direction, respectively. The coordinates of each monitoring sampling point have been reduced inward by a preset safety margin.

12. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 1, characterized in that: The repair decision module is a combinational logic circuit, which is configured to determine the coordinate axis to which the current monitoring sampling point belongs based on the current monitoring sampling point position information in the repair trigger signal, and map the coordinate axis to the corresponding physical layer distortion type: if it belongs to the voltage axis, it is determined to be amplitude attenuation; if it belongs to the time axis, it is determined to be phase jitter. The distortion type encoding signal output by the repair decision module is a multi-bit encoding used to identify two types of distortion: amplitude attenuation and phase jitter.

13. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 12, characterized in that: The repair decision module is also configured to output an adjustment enable signal to the parameter adjustment module while outputting the distortion type encoding signal. The adjustment enable signal contains a direction instruction indicating that the register value of the target equalizer is incremented or decremented by 1.

14. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 1 or 13, characterized in that: The parameter adjustment module includes an address mapping unit and a read-modify-write state machine. The address mapping unit is configured to receive the distortion type encoding signal and, based on the determined physical layer distortion type, output the corresponding target equalizer address: when the distortion type encoding signal indicates amplitude attenuation, output the address of the continuous-time linear equalizer control register; when the distortion type encoding signal indicates phase jitter, output the address of the decision feedback equalizer control register. The read-modify-write state machine is configured to perform read, modify, and write operations on the register value of the target equalizer based on the target equalizer register address through the dynamic reconfiguration interface of the physical layer transceiver. After each write operation is completed, a re-evaluation trigger signal is sent to the online monitoring module to trigger it to re-evaluate the same monitoring sampling point.

15. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 14, characterized in that: The read-modify-write state machine is configured to increment or decrement the register value of the target equalizer by 1 according to the direction instruction contained in the adjustment enable signal.

16. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 15, characterized in that: The read-modify-write state machine is configured to record the current link error count as a first reference value before each modification operation is performed; After performing the modification operation and triggering the online monitoring module to re-evaluate, a new link error count is obtained as a second reference value; Based on the comparison between the first reference value and the second reference value, it is determined whether the adjustment direction is correct, and the direction command for the next adjustment is determined accordingly.

17. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 16, characterized in that: The read-modify-write state machine is configured such that if the second reference value is less than the first reference value, the adjustment direction is determined to be correct, and subsequent adjustments continue to receive the direction instructions from the self-repair decision module. If the second reference value is greater than or equal to the first reference value, the adjustment direction is determined to be incorrect, and subsequent adjustments will be made in reverse to receive the direction command from the self-healing decision module.

18. The PCIe link monitoring and self-repair system for FPGA accelerator cards according to claim 16, characterized in that: The read-modify-write state machine is configured to: when the second reference value is lower than the preset repair completion threshold, determine that the repair is complete and stop the adjustment operation, and send an instruction to the online monitoring module to resume polling monitoring after the repair is determined to be complete.

19. An FPGA accelerator card, characterized in that, It includes the PCIe link monitoring and self-healing system for FPGA accelerator cards as described in any one of claims 1 to 18.

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