Data acquisition time synchronization method and system of single-photon laser radar

Abstract

The invention discloses a data acquisition time synchronization method and system for a single-photon laser radar. The method comprises the following steps: constructing a high-order counter and a low-order interpolator in a field programmable gate array based on a high-stability constant-temperature crystal oscillator to jointly generate a system timestamp; a reference timestamp is generated when the laser dominant wave and echo signal input passes through the time-to-digital conversion module; recording a system timestamp in the whole process of requesting and returning peripheral data, and synchronously acquiring communication delay and an environment state; a delay compensation and edge prediction mechanism is introduced into time synchronization logic, and peripheral time is mapped to a laser reference time system to be fused with ranging data; when a second pulse signal generated by a GNSS is received, a drift model is established for periodic calibration, and when the signal fails, a historical drift model is automatically called for compensation. According to the invention, the acquisition time of the multi-source heterogeneous data in the single-photon laser radar can be synchronously aligned to a unified time axis, and a unified time reference is provided for subsequent processing.

Description

Technical Field

[0001] This invention relates to the field of single-photon lidar technology, specifically to a multi-source data synchronization method based on field-programmable gate arrays (FPGAs), applicable to the alignment of multi-source data with laser signal timestamps in single-photon lidar. Background Technology

[0002] With the rapid expansion of single-photon lidar technology in fields such as high-precision ranging, 3D imaging, autonomous driving, and space mapping, higher requirements are placed on the time synchronization accuracy of data acquisition from various sensors in the system. Currently, a high count rate time-to-digital converter based on a field programmable gate array (FPGA) and its implementation method have been proposed. This converter can statistically analyze the photon time distribution histogram in real time in a single-photon lidar, improve counting efficiency and support multi-channel expansion. However, this time-to-digital converter does not take into account the synchronization with data from other sensors in the single-photon lidar. Existing methods include a single-photon lidar 3D imaging method employing a multi-laser repetitive cycle scanning and reconstruction algorithm. This method improves the accuracy of deep-field imaging through heterogeneous laser pulses. However, due to the different pulse periods in each sub-region, the lack of a calibration source makes it difficult to unify the calibration timing, easily leading to time drift and the accumulation of ranging errors. A paper published in *Instrumentation Technology and Sensors*, titled "Design of a Multi-Sensor Fusion Synchronization Timing System Based on FPGA," proposes an FPGA-based multi-sensor fusion synchronization timing system aimed at improving the synchronization accuracy and overall robustness of the system during multi-source data fusion. This system integrates multiple sensors, including lidar, camera, and inertial measurement unit (IMU). A pulse-per-second (PPS) calibration module is designed in the FPGA to generate a precise and stable standard trigger signal. Each sensor generates a synchronization pulse based on this standard signal and its own operating frequency, thereby achieving high-precision time synchronization between the lidar, camera, and IMU. However, the system also has some obvious shortcomings: on the one hand, the system synchronization mainly relies on the PPS calibration module inside the FPGA and the triggering capability of each sensor. When the sensor interfaces are different or do not support external triggering, the system's adaptability is limited and its scalability is not strong. On the other hand, in complex external environments or long-term operation scenarios (such as high temperature, field, and no GNSS), the system time base may experience slight drift, and the accumulated error affects the consistency of timestamps. Summary of the Invention

[0003] Purpose of the invention: In order to overcome the above shortcomings, the purpose of this invention is to provide a data acquisition time synchronization method for single-photon lidar.

[0004] To address the aforementioned technical problems, this invention provides a data acquisition time synchronization method for single-photon lidar, applicable to single-photon lidar controlled by a field-programmable gate array (FPGA), comprising the following steps: S1: When the single-photon lidar is started, initialize each functional module and establish a unified system time reference; S2: Based on the reference clock generated by the high-stability isothermal crystal oscillator, a hierarchical time base measurement architecture is constructed. The system timestamp is generated by combining high-bit period counting, mid-bit multi-phase parallel sampling and low-bit sub-cycle interpolation. The original measurement is dynamically corrected by combining online calibration table, temperature and voltage compensation and noise filtering to obtain a system timestamp with confidence. S3: Send control commands to each peripheral device of the single-photon lidar to start the data acquisition process; S4: Control the laser to periodically emit laser pulses, and send the main laser wave signal and echo signal into the time-to-digital converter module to generate a laser ranging timestamp sequence as a reference time axis; S5: Periodically sends data request commands to the servo motor and POS according to the preset frequency and periodically obtains servo rotation position data and positioning data. Based on the environmental perception, model prediction and confidence evaluation results of peripheral communication delay, it dynamically adjusts the request time and request frequency, and writes back the measured return delay and environmental information. S6: When receiving the returned data, the returned data is cached separately and the system timestamp of the receiving time is recorded separately. The data is then merged into peripheral data with system timestamp tags. The communication delay of the peripheral data is dynamically predicted and corrected, and the peripheral data timestamp is mapped onto the reference time axis. S7: When a PPS signal is detected, the system timestamp is periodically calibrated using the PPS signal, and when the PPS signal is unavailable, the system timestamp is compensated and corrected using the historical drift model. S8: Align and fuse laser ranging data, servo motor position data and POS positioning data according to the calibrated unified time reference, and output the multi-source synchronous data with reference timestamp to the host computer.

[0005] In a preferred embodiment of this application, step S1 includes the following steps: When the single-photon lidar is started, it initializes the time-to-digital conversion module, time synchronization module, control module, and data transmission module. At the same time, it starts the built-in calibration circuit and drift model unit to support subsequent self-calibration and drift compensation.

[0006] In a preferred embodiment of this application, step S2 includes the following steps: S201: Use MMCM / PLL or equivalent phase management module to multiply and phase-allocate the reference clock to generate N equally spaced or adjustable phase clocks, and apply a fixed delay matching constraint to the phase output. S202: The external event to be marked or the edge to be tested is input in parallel to each phase sampling trigger and each phase state is latched within the same sampling period to form a multiphase parallel sampling word that reflects the phase distribution when the event arrives. S203: The parallel sampling word is further input to the delay chain measurement unit based on FPGA carry-chain to generate a subdivided hot code sequence, and a Vernier structure is formed by constructing a dual delay chain to obtain higher time resolution; S204: Perform bubble cleaning and error detection on the hot code sequence and correct irregular hot codes through repair logic, while writing the repair flag into the timestamp metadata; S205: Set the high-order counter to a Gray code counter and capture and convert it into a binary cycle count value through a two-phase handshake logic after an event is detected, so as to avoid sampling ambiguity caused by multiple bit flips; S206: Performs offline / factory calibration and online calibration within a field-programmable gate array and maps the raw hot codes of a delay chain or Vernier double chain to physical time quantities via a calibrated LUT; S207: Based on the calibrated delay mapping table, the hot code is mapped to a physical time quantity, and a sub-periodic time component is generated by combining piecewise linear interpolation and polynomial fitting. S208: Combines the high-order cycle count with the calibrated sub-cycle time component into a system timestamp and performs boundary correction when a cross-clock boundary conflict is detected; S209: Perform digital post-processing on the generated system timestamp, including median filtering and confidence calculation, and then write the timestamp, confidence, calibration version number and repair flag into the event cache; multiple parallel timestamp pipelines and event FIFOs are used to support high-throughput concurrent event processing, and pipeline latency and buffer overflow are monitored. S210: The final output timestamp field consists of calibration version number, period high bit, sub-period calibration time, confidence level, and verification and repair flags. The upper-level reading logic can merge or discard the timestamp based on the confidence level and repair flags.

[0007] As a preferred embodiment of this application, in step S3, the method further includes the following steps: S301: Through programmable initialization sequence logic, start commands are sent to the laser, time-to-digital converter module, servo motor and positioning system in sequence according to the preset start order. At the same time, the response delay of each peripheral device is dynamically measured, and the timing of subsequent control commands is adjusted according to the real-time delay curve to optimize the time synchronization accuracy during the peripheral device start-up process and record the response time of each start-up. S302: While sending the start command, collect the laser current, voltage and temperature, the channel status of the time-to-digital converter module and the initialization status of the POS, and store the monitoring results in the status register along with the start timestamp. S303: Combines the peripheral startup sequence with the timestamp generation logic. Before the first timestamp acquisition, it uses dynamic delay compensation and edge prediction algorithms to perform synchronization point calibration, so that the first laser pulse emission is synchronized with the time-to-digital converter's counter and interpolator sampling. At the same time, it records the environmental conditions, reference clock channel, and temperature and voltage parameters at the startup time.

[0008] In a preferred embodiment of this application, step S5 includes the following steps: S501: Before each request cycle, environmental state parameters are collected and an environmental state vector is formed. Then, the environmental state vector is preprocessed and written into a dedicated register. The environmental state parameters include one or more of the following: temperature, voltage, signal strength, bit error rate, round-trip time statistics, packet loss rate, motor load, encoder jitter, and historical delay statistics. If a key component in the environmental state vector exceeds a preset threshold, an environmental upgrade flag is directly triggered. S502: A fuzzy inference system is used to classify the environmental state vector and output the environmental category and environmental uncertainty. The fuzzy inference system uses a Gaussian membership function to model the environmental state parameters and updates the membership function parameters online using a recursive least squares algorithm. S503: Employs a multi-model parallel delay prediction architecture to predict the delay of peripheral communication links. The delay prediction architecture includes a linear autoregressive model, a Gaussian process model, and a particle filter model. Each prediction model outputs the mean and variance of the predicted delay. Then, the outputs of multiple prediction models are weighted and fused based on the Bayesian model averaging method to obtain the final delay prediction distribution. S504: After generating the prediction distribution, the time alignment problem of the data request is modeled as a probability maximization problem. Then, the optimal sending time is calculated based on the delayed prediction distribution, and the sending time is corrected by combining the prediction variance and the target confidence parameter. When the prediction variance increases or the environmental category is characterized by drastic fluctuations, the target confidence parameter is automatically reduced and the data request is sent in advance to reduce the probability of alignment failure.

[0009] As a preferred embodiment of this application, in step S5, the method further includes the following steps: S505: When sending a data request, record the sending timestamp, environment state vector, model weights, prediction mean and prediction variance, and calculate the actual communication delay when receiving data returned by the peripheral device. The actual communication delay is written into the delay measurement cache and the prediction model is updated online based on the delay measurement cache. The online update includes parameter recursive update and particle resampling. S506: Perform anomaly detection on actual communication delays and, when an anomaly sample is detected, isolate and store the anomaly sample and use a substitute sample to participate in model updates to avoid anomaly data contaminating the prediction model; wherein, the anomaly sample record includes time, environment vector and original hot code.

[0010] S507: Perform online change point detection to identify abrupt changes in environmental or communication characteristics and adjust the model learning rate, switch prediction modes, and trigger short-term forced calibration when a change point is detected; S508: Based on prediction confidence, environmental uncertainty and historical error, the data request frequency and sending strategy are dynamically adjusted to balance time alignment accuracy and system throughput, and a long-term optimization strategy based on reinforcement learning is introduced. S509: When a single-channel anomaly is detected in a multi-channel or redundant communication path, it automatically switches to the backup channel and generates alternative data through interpolation during the switching process to ensure data continuity. S510: Calculate the alignment timestamp based on the prediction delay, calibration bias, and filter correction term, and simultaneously calculate the corresponding uncertainty; S511: Continuously record statistical indicators related to the prediction and alignment process and periodically upload the statistical indicators in compressed batches.

[0011] As a preferred embodiment of this application, in step S6, the method further includes the following steps: S601: During the first clock cycle of data reception, the peripheral return data and the corresponding system timestamp are written to the double buffer simultaneously through the atomic transaction binding mechanism, and the clock domain cross detection logic is triggered during the writing process to ensure that timestamp drift or data misalignment will not occur under multi-channel high concurrency. S602: Clock domain cross-checking is performed during peripheral data writing to detect cross-clock domain anomalies under multi-channel high concurrency conditions; S603: During cache scheduling, a dynamic scheduling strategy based on multi-objective optimization is adopted to allocate scheduling priority to the peripheral data according to the importance of the peripheral data, timestamp uncertainty, and drift risk factors; S604: Performs timestamp consistency verification on the bound peripheral data, including calculating the difference sequence between the peripheral timestamp and the reference timestamp generated by the time-to-digital conversion module, and when an abnormal timestamp drift is detected, performs adaptive interpolation correction on the peripheral data and writes the correction parameters into the drift tracking register for subsequent model updates; S605: In the peripheral data fusion stage, a multi-channel consistency marking mechanism based on factor graph is introduced, which uses the timestamps of different peripheral data as nodes and the time alignment constraints as edges to model a joint probability graph. S606: Before the peripheral data is output in batches, a recursive Bayesian drift self-check based on a sliding window is performed to detect time drift during long-term operation of the system. If the mean drift of the posterior distribution exceeds the set threshold, a model update request is automatically triggered, and the cache output timing is adjusted to ensure that the peripheral data can still be stably mapped to a unified time base during long-term operation.

[0012] As a preferred embodiment of this application, in step S7, the method further includes the following steps: S701: Monitors the rising edge of the PPS signal of the POS and, upon detecting the rising edge of the PPS signal, resets the current system clock count value to the ideal whole second value in the subsequent clock cycle to generate a PPS-aligned timestamp.

[0013] S702: When the POS does not provide a valid PPS signal, the historical drift model is invoked to correct the current system timestamp; S703: It divides a portion of the storage area into an unsynchronized data buffer area using the fourth-generation double data rate synchronous dynamic random access memory and places the timestamp sequence generated by the time-to-digital converter and peripheral data with system timestamp tags into the unsynchronized data buffer area. S704: Extract timestamp sequences and peripheral data with timestamp tags from the unsynchronized data buffer. For each timestamp sequence, search for data that meets preset conditions in the peripheral data. If a timestamp sequence is not within the preset range, skip it or fill it with an invalid value. S705: When a valid interval is found, perform linear interpolation on the peripheral data, and use the linearly interpolated data as the synchronized version of the peripheral data, corresponding to the timestamp sequence, and put it into the synchronization time buffer.

[0014] This application also relates to a data time synchronization system for a single-photon lidar, including a time synchronization module, a control module, an interpolator, a counter, an OCXO clock source, and a data interface module. The system executes the method described in any of the above descriptions during operation.

[0015] The technical solution described in this application has the following advantages over the prior art: By matching the high-precision TDC timestamp within the FPGA with the system clock timestamp, the acquisition time of laser ranging data is aligned with that of the servo motor and POS system data. During system startup, the FPGA initializes the TDC, time synchronization, control, data transmission modules, and built-in calibration circuitry and drift model unit, preparing conditions for self-calibration and drift compensation. During acquisition, edge sampling is performed on the frequency-doubling multiphase clock driven by a high-stability temperature-controlled crystal oscillator (OCXO) within the FPGA. Combined with delay chain interpolation and hot code decoding, subdivision calculations within the clock cycle are performed to generate a high-precision timestamp. The control module achieves peripheral synchronous startup according to a programmable sequence and dynamic delay measurement, and performs the first synchronization point calibration. Peripheral data acquisition is performed through fixed-period instructions, recording communication status, environmental parameters, and delay information. The FPGA performs sliding window delay measurement, weighted averaging, and linear prediction in parallel to generate timestamped data. When PPS is valid, the system periodically calibrates the timestamp; when PPS is not available, the historical drift model is called for correction. The TDC timestamp and peripheral data are aligned and interpolated through DDR4 cache to generate a synchronized data sequence, which is then transmitted to the host computer via high-speed data transmission for storage and 3D modeling processing. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0017] Figure 1 This is an application environment diagram of the single-photon lidar data acquisition time synchronization method provided in the embodiments of the present invention.

[0018] Figure 2 This is a flowchart of the single-photon lidar data acquisition time synchronization method provided in the embodiments of the present invention.

[0019] Figure 3 This is a detailed flowchart of step S2 in the single-photon lidar data acquisition time synchronization method provided in the embodiments of the present invention.

[0020] Figure 4 This is a detailed flowchart of step S7 in the single-photon lidar data acquisition time synchronization method provided in the embodiments of the present invention.

[0021] Figure 5 This is a timing diagram of the PPS calibration signal in the single-photon lidar data acquisition time synchronization method provided in this embodiment of the invention.

[0022] Figure 6This is a flowchart of the data extraction and fusion process in the single-photon lidar data acquisition time synchronization method provided in the embodiments of the present invention.

[0023] Figure 7 This is a structural diagram illustrating the working principle of the single-photon lidar data acquisition time synchronization system provided in this embodiment of the invention. Detailed Implementation

[0024] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0025] This application provides a data acquisition time synchronization method based on single-photon lidar, which can be applied to, for example... Figure 1 The single-photon lidar system shown is a field-programmable gate array (FPGA) that serves as the main controller for the entire system. The time-to-digital converter (TDC) module, control module, time synchronization module, and data transmission module are all implemented on the FPGA. The laser emits a laser beam onto a reflector. A servo motor drives the reflector to rotate, and the laser beam follows the reflector's rotation, exiting in a near-elliptical trajectory for planar scanning. A photoelectric sensor receives the laser echo and transmits it to the TDC module to obtain the laser flight distance data. The position and orientation system (POS) provides positioning data. After synchronizing the motor, laser flight distance data, and POS positioning data, the data is transmitted to the host computer via the data transmission module. The host computer processes the data to construct a 3D image.

[0026] refer to Figure 2 As shown in some embodiments of this application, a data acquisition time synchronization method for a single-photon lidar is involved. This method is executed by the FPGA master controller in the single-photon lidar and includes the following steps S1 to S8.

[0027] S1: When the single-photon lidar is started, initialize each functional module and establish a unified system time reference.

[0028] Specifically, in step S1, when the single-photon lidar is started, the FPGA initializes the time-to-digital conversion (TDC) module, time synchronization module, control module, and data transmission module; at the same time, the built-in calibration circuit and drift model unit are started to prepare for subsequent self-calibration and drift compensation.

[0029] S2: The reference clock is output by the Oven Controlled Crystal Oscillator (OCXO) connected to the FPGA. The system adopts a hierarchical time base measurement architecture. The high-order bit is provided by the Gray-encoded period counter driven directly at the same frequency or multiplied by the reference clock. The middle bit is provided by the multiphase parallel sampling array generated by the MMCM / PLL (or equivalent DLL) inside the FPGA. The low-order bit is provided by the TDC based on the FPGA fine-grained controllable delay chain (carry-chain / tap) and the optional Vernier double chain structure. The original measurement is corrected and the uncertainty is estimated in real time by the dynamic calibration table, temperature and pressure monitoring and filter inside the FPGA. Finally, the high-order period count and the calibrated sub-period time are merged into a system timestamp with confidence according to the event pipeline.

[0030] refer to Figure 3 As shown. Specifically, in step S2, the method includes the following steps: S201. Use MMCM / PLL or equivalent phase management module in FPGA to multiply and precisely phase-allocate the OCXO reference clock to generate N equally spaced or adjustable phase clocks (N can be set according to the target resolution and FPGA capability), provide a multi-phase sampling reference for the parallel sampler, and apply fixed delay matching constraints to these phase outputs to reduce system errors caused by wiring asymmetry.

[0031] S202. The external event to be marked or the edge to be tested is simultaneously sent to each phase sampling trigger. The event input is synchronized by a two-stage synchronizer to reduce metastability and save the original trigger pulse width information. All phase samplers latch their states in parallel within the same sampling period to form a multi-channel parallel sampling word (i.e., multi-phase hot code) that reflects the phase distribution when the event arrives.

[0032] S203. The parallel sampling word first enters the delay chain measurement unit based on FPGA carry-chain. By injecting the event pulse edge into the carry tap after layout constraint and capturing the state of each tap with a high-speed clock, a subdivided hot code sequence is obtained. To improve linearity and resolution, two delay chains of different lengths can be constructed in parallel as a Vernier structure, and the propagation difference between the two chains can be measured to obtain finer time resolution.

[0033] S204. Bubble cleaning and error detection are performed on the hot codes from the delay chain and multiphase sampling words within the FPGA. Specifically, the hot codes are converted into coarse binary positions using a priority encoding / prefix-sum circuit in the decoding logic, and inconsistencies are detected using redundant detection bits or simple Hamming checks. If irregular bubbles or metastable bits are detected, the built-in repair logic (such as local majority or neighbor averaging) is triggered and the repair flag is written to the timestamp metadata.

[0034] S205. Set the high-order counter to a Gray code counter and update it on the reference clock edge to avoid sampling ambiguity caused by instantaneous multiple bit flips. The snapshot of the high-order counter is captured in the event path by a two-phase handshake logic: when the low-order delay chain or multi-phase sampler detects a trigger, a synchronous capture pulse is used to latch the current Gray code and convert it back to binary as the period high-order bit. The capture logic includes a boundary detection bit to identify cases where the event occurs near the clock edge.

[0035] S206. Implement a runtime adaptive calibration module within the FPGA. The calibration module consists of two parts: Offline / factory calibration is used to establish the baseline delay per tap of the initial delay chain and generate the initial LUT; Online calibration measures the actual width of each tap by periodically injecting calibration pulses at known intervals (or utilizing the known reference edge of the OCXO) and updating the LUT with a recursive least squares or low-pass averaging algorithm, while simultaneously reading onboard temperature and power supply voltage sensors to construct a second-order or piecewise linear compensation model for temperature and pressure versus time delay.

[0036] S207. The original hot code of the delay chain or Vernier double chain is mapped to a physical time quantity (e.g., picosecond / nanosecond) through a calibration LUT. The calibration mapping adopts a strategy that combines piecewise linear interpolation and small-order polynomial fitting to balance the accuracy and resource overhead at the nonlinear point. At the same time, a protection mechanism (such as sliding window statistics and anomaly detection) is adopted for LUT updates to prevent a single abnormal calibration sample from introducing erroneous compensation.

[0037] S208. When synthesizing the system timestamp, first merge the high-order counter (number of cycles) with the calibrated low-order sub-cycle time components. The merging logic corrects possible cross-clock boundary situations: if the low-order measurement is close to the cycle boundary and there is a contradiction between the high-order snapshot and the sampler state, then add / subtract a reference cycle according to the surrounding sampling state and time continuity rules, and mark the boundary correction in the timestamp metadata.

[0038] S209. Apply digital post-processing to the generated raw timestamps within the FPGA pipeline: First, a short-time window mid-range filter is applied to several consecutive measurements to remove random jitter between pulses; Then calculate and output the confidence index (such as the estimated standard deviation or effective resolution) for each timestamp, and write the timestamp, confidence index, calibration version number and repair flag together into the event FIFO for the upper-layer processor to retrieve and further fuse.

[0039] S210. To ensure high throughput and concurrent event processing capabilities, multiple parallel timestamp pipelines and deep event FIFOs are implemented in the FPGA. Each pipeline uses a fixed-length register group at each stage to achieve a fixed delay and allows backpressure control and counter overflow detection under high event rates. The event FIFO supports timestamp batch reading and over-limit discarding strategies, and provides hardware statistical counters for online performance monitoring (such as the number of uncalibrated events, the number of repairs, and the FIFO overflow rate).

[0040] S211. The final output format is defined as follows: The timestamp field consists of <calibration version number, period high bit, sub-period calibration time (unit picoseconds or nanoseconds), confidence level, and verification and repair flag>. The upper-level reading logic can merge / discard the timestamp based on the confidence level and repair flag to meet different accuracy / reliability requirements.

[0041] In some examples of this application, to reduce device-dependent and layout-dependent uncertainties, strict physical constraints are imposed on the routing of key nodes (multiphase outputs, delay chain inlets, and sampling contacts) during the implementation phase. Timing constraint scripts are used to constrain routing delays, cross-clock constraints, and input / output (IO) delays. The design also includes a diagnostic mode for online verification: in diagnostic mode, the system can output the original hot code DC of the delay chain and record the calibration residual for offline analysis and process-dependent compensation.

[0042] S3: The control module within the FPGA sends control commands to turn on the laser, TDC module, servo motor, and POS, thus initiating data acquisition for the single-photon lidar.

[0043] Specifically, in step S3, the method includes the following steps: S301: During the system startup phase, the control module sends startup commands to the laser, TDC module, servo motor and POS sequentially through programmable initialization sequence logic. At the same time, it dynamically measures the response delay of each peripheral device, adjusts the timing of subsequent control commands based on the real-time delay curve to optimize the synchronous startup accuracy, and records the response time of each startup for adaptive correction.

[0044] S302. While sending the start command, the control module collects the laser current, voltage and temperature, TDC channel status and POS system initialization status through the integrated multi-channel monitoring unit. The monitoring results and start timestamp are written to the status register at the same time to provide a reference for subsequent data acquisition correction, drift compensation and confidence assessment.

[0045] S303, the control module combines the peripheral startup sequence with the timestamp generation logic, performing synchronization point calibration before the first timestamp acquisition. This calibration uses dynamic delay compensation and edge prediction algorithms to synchronize the first laser pulse emission with the TDC counter and interpolator sampling. At the same time, it records the environmental conditions at the startup time, the reference clock channel, and temperature and voltage parameters in the original data, providing traceable information for subsequent data fusion.

[0046] S4: After the control module turns on the laser by sending a control command, the laser periodically emits laser pulses. The main wave signal of the laser is directly output to the TDC module after being connected to the SMA interface on the TDC module through the coaxial cable via the sub-miniature version Aconnector (SMA) interface on the laser. The echo signal is received by the photoelectric sensor, converted into an electrical signal, and then connected to the TDC module through the coaxial cable. The TDC module converts the main wave and echo signals into a high-precision timestamp sequence through time-to-digital conversion technology, which serves as the reference timestamp.

[0047] S5: While the TDC module collects laser flight distance data, the control module periodically sends data request commands to the servo motor and POS at a pre-set fixed frequency and periodically obtains the rotational position data of the servo motor and the positioning data of the POS. The system dynamically adjusts the request time and request frequency by performing environmental perception, model prediction, confidence evaluation and optimal transmission time calculation for peripheral delays, and writes the measured return delay and environmental label back to the FPGA for online adaptive calibration and long-term learning to ensure high-precision time alignment with the TDC flight distance sampling.

[0048] Specifically, in step S5, the method includes the following steps: S501. Before each request cycle, the control module collects and forms an environment state vector S={T_board, Vcc, RSSI, BER, RTT_stats, packet_loss_rate, motor_torque, encoder_jitter, recent_delay_mean, recent_delay_var}. Each quantity is first lightly preprocessed after collection (IIR low-pass filtering and outlier truncation), and several statistical features are calculated (the sliding window length N_env can be set from 32 to 256, and the mean, variance, autocorrelation coefficient, and short-time Fourier spectrum peak value are calculated). The environment vector is also quantized and written to the FPGA dedicated register for subsequent model reading in real time. If the key components in the environment vector exceed the preset threshold, the environment upgrade flag is directly triggered, changing the learning rate and conservative strategy of the subsequent predictor.

[0049] S502. First, perform coarse classification of the environment state vector using a lightweight fuzzy inference system (FIS). The FIS uses three membership functions (stable / moderate / violent), and the membership functions can be Gaussian. ,in, Represents environmental characteristic components; This indicates the membership degree of the feature on a certain fuzzy set; σ is the center value of the membership function; σ is the bandwidth of the membership function, which determines the distribution width of the function.

[0050] During operation, The FIS is dynamically adjusted using the Recursive Least Squares (RLS) method to adapt to environmental aging and device characteristic drift; the FIS ultimately outputs the current environmental category (CCC) and environmental uncertainty. ∈[0,1], they are related to historical errors Together, they serve as prior inputs to the predictor, used to select or adjust the parameters of the predictive model.

[0051] S503, delayed prediction adopts a multi-model parallel hybrid predictor architecture: model set These correspond to the linear autoregressive (AR) model, sparse Gaussian process (GP) model, and particle filter (PF) model, respectively; each model is computed in parallel on the FPGA to predict the distribution. ,in For m∈M, the mean and variance of each model's output predictions are: , .

[0052] The model weights are updated by averaging using a Bayesian model: The likelihood function can be approximated by the current observation error: ; The expected value and variance of the final mixed posterior distribution are: , , in, S represents the link delay; S represents the environment state vector. This refers to the model prediction error; For model weights; These are the mean and variance of the weighted forecasts, respectively.

[0053] S504, after obtaining the predicted distribution (Approximately Gaussian or Gaussian mixture) After that, the control module formalizes the alignment problem into probability maximization: selecting the transmission time. This causes the event to reach the higher time. With TDC sampling time The difference falls within the allowed alignment window The probability is maximized, i.e., the probability is maximized. The above probabilities can be converted to: The closed-form approximate solution to this optimization problem is: ,in, The choice of the parameter desired_confidence can be achieved through cost function optimization: , in, This indicates the probability of a window not falling within the alignment window. , These are preset weighting factors, corresponding to the loss penalty and the transmission frequency cost, respectively; This represents the current data request frequency. For reference request frequency.

[0054] When predicting When variance increases or environmental classification results fluctuate drastically, the system automatically reduces desired_confidence and sends data earlier to reduce the probability of loss; simultaneously, if the calculated... If the transmission frequency exceeds the allowed advance / delay boundaries, or conflicts with the time interval of the previous request, the system will dynamically adjust the transmission frequency. A trade-off is made between throughput and alignment accuracy.

[0055] S505: Each time a request is sent, the control module collects and writes metadata, including the local transmission timestamp, into the dedicated register group at the FPGA layer. (Recorded by high-precision TSC), current environment vector S, model weight vector Predicted mean Prediction variance And the selected desired_confidence, the actual latency is quickly captured by the hardware when the returned data arrives. The measured delay The current S is pushed into the delayed measurement loop buffer (loop length N_delay can be set from 64 to 1024), and the online model update is triggered: the linear module performs RLS weight update (forgetting the factors). The GP module updates sparse kernel points and approximate posterior (using intra-batch least squares), and the particle filter module resamples and updates particle weights. All updates are completed in a pipeline with a fixed periodic delay to avoid blocking real-time acquisition.

[0056] S506. To prevent measurement noise and bubbles from causing poor updates, delayed measurements undergo anomaly detection upon entering the FPGA: a check based on a combination of MAD (median absolute deviation) and local entropy discrimination is used. If... If the deviation from the median of the sliding window exceeds a threshold (e.g., 5×MAD), it is marked as an anomalous sample and processed by a dual-channel strategy: one channel puts the sample into an anomalous buffer for subsequent offline or diagnostic analysis, and the other channel replaces it with a substitute sample (sampled or interpolated from the predicted distribution) and uses it for model updates to avoid contaminating model parameters; the anomalous sample record includes time, environment vector and original hot code.

[0057] S507. The system implements online change-point detection to identify abrupt changes in environmental / communication characteristics. Change-point detection can be approximated using FPGA with Cumulative Sum (CUSUM) or Bayesian Online Change-Point Detection (BOCPD): When a change point is detected, the system automatically increases the model learning rate (reducing the RLS forgetting factor λ to 0.8~0.95), switches to a robust mode based on particle filtering, and triggers a short-term forced calibration cycle (by injecting calibration pulses at known intervals or using synchronization pulses reported by the servo). The change point time and the current model snapshot are written to the persistent calibration log for subsequent analysis.

[0058] S508, Based on prediction confidence Environmental uncertainty Historical error The control module dynamically adjusts the request frequency. Transmission strategy: When the confidence level is high and the environment is stable, a low-power mode is adopted. , / α, α>1), when confidence decreases or uplink congestion / packet loss rate increases, the sampling frequency is increased and randomized transmission offset is used to avoid periodic collisions; in addition, reinforcement learning-based (lightweight Q-learning or policy-based power-penalized model) is introduced as a long-term optimizer, using cumulative reward Learn online for optimal performance in different environments Along with the desired_confidence policy, the Q-table or policy network is stored in the FPGA peripheral processor as a small table / lightweight network and periodically downloaded and updated to the FPGA.

[0059] S509. Supports multiple channels and redundant paths between the receiver and the control module. When a single channel is continuously abnormal, the system automatically switches to the backup channel and generates alternative location data through short-time interpolation at the moment of switching to ensure continuity. After switching, the delay distribution of the two channels is compared to re-estimate the model prior and the model weights are re-initialized if necessary.

[0060] S510, timestamp calculation and confidence propagation employ explicit mathematical synthesis, ultimately aligning the timestamps. Depend on Given, among which For fixed bias correction based on calibration pulse LUT, For the short-time smoothing correction term (short-time window value or small-order Kalman output), the corresponding uncertainty is... ,in It is the local clock jitter variance. To calibrate the residual variance, the entire uncertainty is written into timestamp metadata, which the upper layers of the system can then use to... The threshold determines whether to merge, discard, or label the timestamp.

[0061] The S511 FPGA internal statistician continuously records key metrics (mean delay MAE, RMSE, retransmit_rate, FIFO_occupancy, model_confidence) and periodically uploads these metrics to the main processor in compressed batches for offline batch training or cloud model updates. Online learning uses SGD / RLS with a limited step size combined with L2 regularization to prevent overfitting. When necessary, a larger-scale model fine-tuning is performed in a non-real-time window through a replay buffer, and the new parameters are sent to the field FPGA after verification.

[0062] S6: When receiving the returned data, the returned data is cached separately and the system timestamp of the receiving time is recorded separately. The data is then merged into peripheral data with system timestamp tags. The communication delay of the peripheral data is dynamically predicted and corrected, and the peripheral data timestamp is mapped onto the reference time axis.

[0063] Specifically, in step S6, the method includes the following steps: S601: During the first clock cycle of data reception, the control module uses an atomic transaction binding mechanism to simultaneously write the returned data and the corresponding high-precision system timestamp into the dual buffer. During the writing process, clock domain cross-detection logic is triggered to ensure that timestamp drift or data misalignment does not occur under high concurrency of multiple channels. In addition to saving the timestamp, the binding operation also synchronously records the channel number, dynamic delay compensation factor, and environmental monitoring parameters to form a multi-dimensional timestamp metadata vector to support subsequent cross-channel consistency analysis.

[0064] S602, the clock domain cross-detection logic is jointly driven by a hardware-level flip-flop and a time / event-based consistency monitoring unit: the hardware-level flip-flop performs multi-level synchronous sampling of bidirectional asynchronous event signals (such as asynchronous data-valid pulses, FIFO write / read enable changes, peripheral serial numbers, or event counter overflows) and generates cross-domain edge event indicators; the time / event consistency monitoring unit then compares the high-resolution timestamp differences acquired across domains in parallel. With adaptive threshold (The threshold can be adaptively adjusted based on temperature, voltage, and historical jitter statistics.) When more than K consecutive samples are detected or when asynchronous sequence numbers are not consecutive, a clock domain crossover anomaly trigger signal is generated. After a small delay and debouncing process, the trigger signal drives the crossover detection FSM, which performs an instant snapshot (freezing the relevant buffer), atomic rollback, or critical section locking operation.

[0065] S603. In the cache scheduling process, a dynamic scheduler based on multi-objective optimization is introduced to replace the traditional priority queue. The scheduler assigns a scheduling priority to each returned data item: ,in, For data importance metrics (configured by the application layer); The entropy value of the timestamp distribution reflects the uncertainty of the data; For drift risk factors (predicted by historical models); For adaptive weighting, the control module decides whether to write to the cache immediately, delay writing, or compress storage based on priority, in order to improve the stability of data fusion and the consistency of timestamps.

[0066] S604. Perform timestamp consistency verification on the bound peripheral data. The FPGA internally calculates the difference sequence between the TDC reference timestamp and the peripheral timestamp in parallel: Then use chi-square consistency check: ; If the statistic exceeds the threshold, the timestamp is determined to have an abnormal drift, and the adaptive interpolation kernel function is called to dynamically correct it. The corrected data and correction parameters are written to the drift tracking register for subsequent online model updates.

[0067] S605. A multi-channel consistency marking mechanism based on factor graph is introduced during the data fusion stage. The control module models the servo motor and POS data as a joint probability graph, where nodes represent their respective timestamps and edges represent alignment constraints. The marginal confidence of each data point is calculated through belief propagation, and the maximum a posteriori (MAP) result is selected as the final alignment benchmark. When a conflict is detected between the timestamps or state parameters of the two types of data, the redundancy correction logic will automatically prioritize retaining the channel data with higher confidence and mark the data with lower confidence as requiring secondary correction.

[0068] S606. Before batch outputting the fused data, the system will perform a recursive Bayesian drift self-check based on a sliding window; specifically, it will check the most recent M timestamp sequences { Establish a drift estimation model: δ represents the system drift, and S is the current environmental context (temperature, voltage, channel status). If the mean drift δ of the posterior distribution exceeds the set threshold, a model update request will be automatically triggered, and the cache output timing will be adjusted to ensure that peripheral data can still be stably mapped to a unified time base under long-term operation.

[0069] S7: Processes the base timestamp and peripheral data with system timestamp tags generated by the TDC module, such as... Figure 4 As shown, based on the system timestamp tag of the peripheral data, the peripheral data is corrected and inserted into the reference timestamp. During the entire data acquisition process, the presence of the PPS signal is continuously detected. If it exists, the system timestamp is continuously corrected using the PPS signal. If it does not exist, the system timestamp is corrected using the historical drift model. Finally, the peripheral data with the reference timestamp tag is merged.

[0070] Specifically, in step S7, the method includes the following steps: S2071. During data acquisition, the FPGA monitors the rising edge of the POS's PPS. The system timestamp may drift slowly over long periods of operation. By monitoring the rising edge of the PPS, the system timestamp is calibrated every second. Figure 4 As shown, once the rising edge of PPS is detected, the system_counter value is reset to the ideal whole second value in the following clock cycle, thereby achieving system time alignment.

[0071] When pps_valid is valid and the rising edge of pps_in arrives, sync_flag is set to high, indicating that the system has performed time alignment; pps_capture captures the current value of system_counter and calculates the difference delta_ns between it and the ideal time, which represents the amount of system time drift.

[0072] S2072. When the POS does not provide a valid PPS signal, the system cannot calibrate the system timestamp in real time. In this case, the FPGA calls the historical drift model to correct the current system timestamp. During the period when continuous PPS signals exist, the error between the system timestamp and the ideal integer second is recorded, and a time drift rate model is constructed. Let the timestamp recorded by the system at a certain moment when the i-th PPS signal arrives be... Its theory should be The drift error is: ,in, For the first Time drift error in seconds (unit: ns); For the first time recorded by the system The timestamp corresponding to each PPS signal; This is the ideal interval for PPS.

[0073] Using linear fitting methods for multiple By fitting the data, the drift rate can be obtained. That is, the system time drift per unit time: ; When the system fails to receive a new PPS signal, assume that the current time has elapsed since the last PPS signal. Seconds, the system will display the current system timestamp. The following corrections are made: ,in, The system timestamp is corrected for the drift model; The time interval between the current moment and the most recent valid PPS signal; The drift slope per unit time; This is the original, uncorrected system timestamp.

[0074] S2073: A portion of the storage area on the FPGA board is divided into unsynchronized data buffers using the Double Data Rate 4 Synchronous Dynamic Random Access Memory (DDR4). The timestamp sequence generated by the TDC module and peripheral data with system timestamp tags are placed in the unsynchronized data buffers.

[0075] S2074, such as Figure 5 As shown, the time synchronization module extracts the TDC timestamp sequence and peripheral data with timestamp tags from the unsynchronized data cache of DDR4, and extracts a set of TDC timestamp sequences { , ,…, }, a set of peripheral data with system timestamp tags {( , )}, where is the system timestamp, It is the system timestamp of the data value for peripheral data.

[0076] S2075, Compare with the TDC timestamp sequence, for each Searching for satisfactory data in peripheral devices The data, of which ( , )and( , ) are peripheral data points that are adjacent in time. Not in any [ , If the range is within the specified range, skip it or fill it with an invalid value.

[0077] S2076. Find the effective interval, and perform linear interpolation on the peripheral data, using the following formula: .

[0078] S2077, will As a synchronized version of peripheral data, with Correspondingly, the synchronized data will be... Place it in the synchronization time buffer.

[0079] S8: Align and fuse the laser ranging data, servo motor position data, and POS positioning data according to the calibrated unified time reference. Then, the data transmission module transmits the fused data with the reference timestamp tag through the 3.0 high-speed transmission to the host computer for storage or subsequent 3D modeling processing.

[0080] The proposed method incorporates system time accuracy factors into the single-photon lidar measurement process. It improves the timestamp generation and time synchronization algorithms by combining the characteristics of the FPGA's internal TDC module and the high-stability OCXO clock's high-order counter and low-order interpolator. Under conditions of peripheral collaborative operation and PPS signal availability, it introduces multi-channel reference clock comparison and fusion, high-order counter epoch field and atomic update, low-order interpolator adaptive topology and temperature compensation, dynamic delay prediction and correction of peripheral returned data, and time axis compensation based on a drift model. This enables the alignment and fusion of laser ranging data, servo motor position data, and POS positioning data under a unified time reference. This method is beneficial for maintaining timestamp consistency and continuous data synchronization under different peripheral response delays, communication states, and environmental conditions.

[0081] Based on the same inventive concept, this application also provides a single-photon lidar data acquisition time synchronization system for implementing the aforementioned single-photon lidar data acquisition time synchronization method. The solution provided by this system is similar to the implementation described in the above method. Therefore, the specific limitations of one or more single-photon lidar data acquisition time synchronization system embodiments provided below can be found in the limitations of the single-photon lidar data acquisition time synchronization method described above, and will not be repeated here.

[0082] In one exemplary embodiment, such as Figure 6 As shown, a single-photon lidar data acquisition time synchronization system is provided, including a TDC module, a control module, a time synchronization module, and a data transmission module. Of course, the architecture shown in the figure is merely exemplary; when implementing different functions, one or at least two components of the system shown can be omitted according to actual needs.

[0083] In one exemplary embodiment, such as Figure 7As shown, an FPGA-based lidar data acquisition and time synchronization device is provided, comprising a TDC module, a control module, a time synchronization module, and a data transmission module, all of which work collaboratively via an on-chip bus. The FPGA uses an OCXO as a reference, combining a frequency-doubling multiphase clock and delay chain subdivision to achieve a high-resolution system timestamp, and dynamically corrects process drift and temperature drift through an adaptive calibration loop. The control module is responsible for laser emission, peripheral triggering, and status acquisition, and calls cross-clock domain detection logic when receiving data to ensure the consistency and atomicity of timestamp binding. The synchronization module performs periodic calibration when receiving the PPS signal from the POS, and utilizes multi-model delay prediction and drift compensation to maintain time continuity in environments with PPS loss or severe fluctuations. In peripheral data fusion, servo motor and POS return data are timestamp bound and cached through a double-buffering and priority scheduling mechanism. The system achieves multi-source data alignment through consistency verification and interpolation correction, and performs drift self-checking and model updates before batch output, thereby ensuring high-precision synchronization during long-term operation. The entire device achieves unified time reference and high-precision fusion processing of laser TDC data, POS data, and servo motor status data.

[0084] In one exemplary embodiment, the FPGA-based lidar data acquisition time synchronization device of the present invention is applied to an UAV-borne mapping scenario. The UAV is equipped with lidar, POS, and servo scanning motors. The device generates a high-resolution system timestamp through an OCXO-driven multiphase clock array and a TDC module. During flight, the control module triggers the laser to emit and acquires echo signals in real time, while periodically sending data requests to the POS and servo motors. Combined with cross-clock domain detection and dynamic delay prediction mechanisms, the peripheral data and the laser echo timestamp are kept aligned. The system performs time consistency verification and interpolation correction on multi-source data in the fusion buffer, and performs drift self-check and model update before batch output. This ensures the continuity of time reference even when PPS is lost or attitude changes drastically. The resulting unified time reference data is beneficial for subsequent high-precision point cloud reconstruction and attitude calculation.

[0085] Those skilled in the art will understand that the FPGA-based architecture described is merely an illustrative hardware implementation of the method described in this application. In practical applications, the module partitioning method, logic unit deployment scheme, interface standard, and signal connection topology can be adjusted and expanded according to specific chip resources, power consumption budget, latency requirements, and other system design indicators. Alternatively, the corresponding logic design and system integration deployment can be completed through toolchains provided by different FPGA manufacturers (such as Vivado, Quartus, etc.).

[0086] In one exemplary embodiment, a hardware logic combination scheme configured inside an FPGA is also provided, including TDC timestamp generation logic, control and alignment logic, time synchronization module and PPS calibration unit. This combination logic can implement all the functional steps in the above-described time synchronization method embodiment.

[0087] In one exemplary embodiment, a logic design file stored in an FPGA configuration file is also provided. This file is used to deploy the aforementioned time synchronization function onto a programmable logic device. When loaded onto the FPGA, it enables the entire process of high-precision time alignment and data fusion in a single-photon lidar system.

[0088] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by programmable logic units (such as lookup tables, flip-flops, state machines, counters, etc.) inside the FPGA; the functional logic can be written in a hardware description language (HDL), and after generating the corresponding bitstream configuration file, it can be loaded onto the target FPGA device for execution, thereby achieving functional control consistent with the processes described in the above method embodiments.

[0089] In the embodiments provided in this application, the memory, on-chip cache, temporary register, or external extended storage resources used may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric memory (FRAM), phase change memory (PCM), graphene memory, etc.; volatile memory may include random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), or Block RAM inside an FPGA, etc., used to perform functions such as timestamps, configuration parameters, and data caching.

[0090] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A data acquisition time synchronization method for a single-photon lidar, characterized in that, When applied to single-photon lidar controlled by a field-programmable gate array (FPGA), the following steps are included: S1: When the single-photon lidar is started, initialize each functional module and establish a unified system time reference; S2: Based on the reference clock generated by the high-stability isothermal crystal oscillator, a hierarchical time base measurement architecture is constructed. The system timestamp is generated by combining high-bit period counting, mid-bit multi-phase parallel sampling and low-bit sub-cycle interpolation. The original measurement is dynamically corrected by combining online calibration table, temperature and voltage compensation and noise filtering to obtain a system timestamp with confidence. S3: Send control commands to each peripheral device of the single-photon lidar to start the data acquisition process; S4: Control the laser to periodically emit laser pulses, and send the main laser wave signal and echo signal into the time-to-digital converter module to generate a laser ranging timestamp sequence as a reference time axis; S5: Periodically sends data request commands to the servo motor and POS according to the preset frequency and periodically obtains servo rotation position data and positioning data. Based on the environmental perception, model prediction and confidence evaluation results of peripheral communication delay, it dynamically adjusts the request time and request frequency, and writes back the measured return delay and environmental information. S6: When receiving the returned data, the returned data is cached separately and the system timestamp of the receiving time is recorded separately. The data is then merged into peripheral data with system timestamp tags. The communication delay of the peripheral data is dynamically predicted and corrected, and the peripheral data timestamp is mapped onto the reference time axis. S7: When a PPS signal is detected, the system timestamp is periodically calibrated using the PPS signal, and when the PPS signal is unavailable, the system timestamp is compensated and corrected using the historical drift model. S8: Align and fuse laser ranging data, servo motor position data and POS positioning data according to the calibrated unified time reference, and output the multi-source synchronous data with reference timestamp to the host computer.

2. The data acquisition time synchronization method for a single-photon lidar according to claim 1, characterized in that, In step S1, the method includes the following steps: When the single-photon lidar is started, it initializes the time-to-digital conversion module, time synchronization module, control module, and data transmission module. At the same time, it starts the built-in calibration circuit and drift model unit to support subsequent self-calibration and drift compensation.

3. A data acquisition time synchronization method for a single-photon lidar according to claim 1 or 2, characterized in that, In step S2, the method includes the following steps: S201: Use MMCM / PLL or equivalent phase management module to multiply and phase-allocate the reference clock to generate N equally spaced or adjustable phase clocks, and apply a fixed delay matching constraint to the phase output. S202: The external event to be marked or the edge to be tested is input in parallel to each phase sampling trigger and each phase state is latched within the same sampling period to form a multiphase parallel sampling word that reflects the phase distribution when the event arrives. S203. The parallel sampling word is further input to the delay chain measurement unit based on FPGA carry-chain to generate a subdivided hot code sequence, and a Vernier structure is formed by constructing a dual delay chain to obtain higher time resolution. S204. Perform bubble cleaning and error detection on the hot code sequence and correct irregular hot codes through repair logic, while writing the repair flag into the timestamp metadata. S205. Set the high-order counter to a Gray code counter and capture and convert it into a binary cycle count value through a two-phase handshake logic after the event is detected, so as to avoid sampling ambiguity caused by multiple bit flips. S206. Perform offline / factory calibration and online calibration within the field-programmable gate array and map the raw hot code of the delay chain or Vernier double chain to the physical time quantity via a calibration LUT; S207. Based on the calibrated delay mapping table, the hot code is mapped to a physical time quantity, and a sub-period time component is generated by combining piecewise linear interpolation and polynomial fitting. S208. Combine the high-order cycle count with the calibrated sub-cycle time component to form a system timestamp and perform boundary correction when a cross-clock boundary conflict is detected. S209. Perform digital post-processing on the generated system timestamp, including median filtering and confidence calculation, and then write the timestamp, confidence, calibration version number and repair flag into the event cache; multiple parallel timestamp pipelines and event FIFOs are used to support high-throughput concurrent event processing, and pipeline latency and buffer overflow are monitored. S210. The final output timestamp field consists of calibration version number, period high bit, sub-period calibration time, confidence level, and verification and repair flags. The upper-level reading logic can merge or discard the timestamp based on the confidence level and repair flags.

4. The data acquisition time synchronization method for a single-photon lidar according to claim 2, characterized in that, In step S2, the method further includes the following steps: During the implementation phase, strict constraints are imposed on the routing of key nodes, and timing constraint scripts are used to constrain routing delay, cross-clock constraints, and input / output delays. This also includes a diagnostic mode for online verification: in diagnostic mode, the system can output the original hot code DC of the delay chain and record the calibration residual for offline analysis and process-related compensation.

5. A data acquisition time synchronization method for a single-photon lidar according to claim 1 or 4, characterized in that, In step S3, the method further includes the following steps: S301: Through programmable initialization sequence logic, start commands are sent to the laser, time-to-digital converter module, servo motor and positioning system in sequence according to the preset start order. At the same time, the response delay of each peripheral device is dynamically measured, and the timing of subsequent control commands is adjusted according to the real-time delay curve to optimize the time synchronization accuracy during the peripheral device start-up process and record the response time of each start-up. S302: While sending the start command, collect the laser current, voltage and temperature, the channel status of the time-to-digital converter module and the initialization status of the POS, and store the monitoring results in the status register along with the start timestamp. S303: Combines the peripheral startup sequence with the timestamp generation logic. Before the first timestamp acquisition, it uses dynamic delay compensation and edge prediction algorithms to perform synchronization point calibration, so that the first laser pulse emission is synchronized with the time-to-digital converter's counter and interpolator sampling. At the same time, it records the environmental conditions, reference clock channel, and temperature and voltage parameters at the startup time.

6. The data acquisition time synchronization method for a single-photon lidar according to claim 5, characterized in that, In step S5, the method includes the following steps: S501: Before each request cycle, environmental state parameters are collected and an environmental state vector is formed. Then, the environmental state vector is preprocessed and written into a dedicated register. The environmental state parameters include one or more of the following: temperature, voltage, signal strength, bit error rate, round-trip time statistics, packet loss rate, motor load, encoder jitter, and historical delay statistics. If a key component in the environmental state vector exceeds a preset threshold, an environmental upgrade flag is directly triggered. S502: A fuzzy inference system is used to classify the environmental state vector and output the environmental category and environmental uncertainty. The fuzzy inference system uses a Gaussian membership function to model the environmental state parameters and updates the membership function parameters online using a recursive least squares algorithm. S503: Employs a multi-model parallel delay prediction architecture to predict the delay of peripheral communication links. The delay prediction architecture includes a linear autoregressive model, a Gaussian process model, and a particle filter model. Each prediction model outputs the mean and variance of the predicted delay. Then, the outputs of multiple prediction models are weighted and fused based on the Bayesian model averaging method to obtain the final delay prediction distribution. S504: After generating the prediction distribution, the time alignment problem of the data request is modeled as a probability maximization problem. Then, the optimal sending time is calculated based on the delayed prediction distribution, and the sending time is corrected by combining the prediction variance and the target confidence parameter. When the prediction variance increases or the environmental category is characterized by drastic fluctuations, the target confidence parameter is automatically reduced and the data request is sent in advance to reduce the probability of alignment failure.

7. The data acquisition time synchronization method for a single-photon lidar according to claim 6, characterized in that, In step S5, the method further includes the following steps: S505: When sending a data request, record the sending timestamp, environment state vector, model weights, prediction mean and prediction variance, and calculate the actual communication delay when receiving data returned by the peripheral device. The actual communication delay is written into the delay measurement cache and the prediction model is updated online based on the delay measurement cache. The online update includes parameter recursive update and particle resampling. S506: Perform anomaly detection on actual communication delays and, when anomalies are detected, isolate and store the anomalies and use alternative samples to participate in model updates to avoid anomalies polluting the prediction model; the anomaly sample record includes time, environment vector and original hot code; S507: Perform online change point detection to identify abrupt changes in environmental or communication characteristics and adjust the model learning rate, switch prediction modes, and trigger short-term forced calibration when a change point is detected; S508: Based on prediction confidence, environmental uncertainty and historical error, the data request frequency and sending strategy are dynamically adjusted to balance time alignment accuracy and system throughput, and a long-term optimization strategy based on reinforcement learning is introduced. S509: When a single-channel anomaly is detected in a multi-channel or redundant communication path, it automatically switches to the backup channel and generates alternative data through interpolation during the switching process to ensure data continuity. S510: Calculate the alignment timestamp based on the prediction delay, calibration bias, and filter correction term, and simultaneously calculate the corresponding uncertainty; S511: Continuously record statistical indicators related to the prediction and alignment process and periodically upload the statistical indicators in compressed batches.

8. The data acquisition time synchronization method for a single-photon lidar according to claim 7, characterized in that, In step S6, the method further includes the following steps: S601: During the first clock cycle of data reception, the peripheral return data and the corresponding system timestamp are written to the double buffer simultaneously through the atomic transaction binding mechanism, and the clock domain cross detection logic is triggered during the writing process to ensure that timestamp drift or data misalignment will not occur under multi-channel high concurrency. S602: Clock domain cross-checking is performed during peripheral data writing to detect cross-clock domain anomalies under multi-channel high concurrency conditions; S603: During cache scheduling, a dynamic scheduling strategy based on multi-objective optimization is adopted to allocate scheduling priority to the peripheral data according to the importance of the peripheral data, timestamp uncertainty, and drift risk factors; S604: Performs timestamp consistency verification on the bound peripheral data, including calculating the difference sequence between the peripheral timestamp and the reference timestamp generated by the time-to-digital conversion module, and when an abnormal timestamp drift is detected, performs adaptive interpolation correction on the peripheral data and writes the correction parameters into the drift tracking register for subsequent model updates; S605: In the peripheral data fusion stage, a multi-channel consistency marking mechanism based on factor graph is introduced, which uses the timestamps of different peripheral data as nodes and the time alignment constraints as edges to model a joint probability graph. S606: Before the peripheral data is output in batches, a recursive Bayesian drift self-check based on a sliding window is performed to detect time drift during long-term operation of the system. If the mean drift of the posterior distribution exceeds the set threshold, a model update request is automatically triggered, and the cache output timing is adjusted to ensure that the peripheral data can still be stably mapped to a unified time base during long-term operation.

9. A data acquisition time synchronization method for a single-photon lidar according to claim 8, characterized in that, In step S7, the method further includes the following steps: S701: Monitors the rising edge of the PPS signal of the POS and, upon detecting the rising edge of the PPS signal, resets the current system clock count value to the ideal whole second value in the following clock cycle to generate a PPS-aligned timestamp. S702: When the POS does not provide a valid PPS signal, the historical drift model is invoked to correct the current system timestamp; S703: It divides a portion of the storage area into an unsynchronized data buffer area using the fourth-generation double data rate synchronous dynamic random access memory and places the timestamp sequence generated by the time-to-digital converter and peripheral data with system timestamp tags into the unsynchronized data buffer area. S704: Extract timestamp sequences and peripheral data with timestamp tags from the unsynchronized data buffer. For each timestamp sequence, search for data that meets preset conditions in the peripheral data. If a timestamp sequence is not within the preset range, skip it or fill it with an invalid value. S705: When a valid interval is found, perform linear interpolation on the peripheral data, and use the linearly interpolated data as the synchronized version of the peripheral data, corresponding to the timestamp sequence, and put it into the synchronization time buffer.

10. A data time synchronization system for a single-photon lidar, characterized in that, The system includes a time synchronization module, a control module, an interpolator, a counter, an OCXO clock source, and a data interface module. When the system is running, it executes the method described in any one of claims 1 to 9.

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