Epitaxial growth optimization method for EEL

Abstract

The embodiment of the invention provides an epitaxial growth optimization method for EEL. The epitaxial growth optimization method comprises the following steps: epitaxially growing an n-type covering layer on a substrate; a multi-period quantum well active layer with a first V / III ratio and a first growth rate is epitaxially grown on the n-type covering layer in a first temperature interval, and the active layer comprises InGaAs quantum well layers and AlGaAs barrier layers which are alternately stacked; epitaxially growing a p-type limiting layer on the active layer; wherein the InGaAs quantum well layer grows at the temperature of 600 DEG C to 650 DEG C, and the AlGaAs barrier layer grows at the temperature of 700 DEG C to 750 DEG C; wherein the V / III ratio is the molar flow ratio of the group V element precursor to the group III element precursor, and the first V / III ratio is 250; wherein the first growth rate ranges from 0.5 nm / s to 1.0 nm / s; wherein the p-type limiting layer adopts carbon as a p-type doping agent. By respectively setting and accurately maintaining the optimal growth temperatures of the quantum well layer and the barrier layer, respective ideal crystal growth dynamic conditions are provided for the quantum well layer and the barrier layer, and the intrinsic quality of the material is ensured.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to an optimization method for epitaxial growth of EEL. Background Technology

[0002] Metal-organic chemical vapor deposition (MOCVD) is the mainstream technique for fabricating this type of quantum well structure. To obtain high-quality quantum wells, it is typically necessary to control parameters such as the growth temperature, gas flow rate, and growth rate of the reaction chamber, and to employ appropriate doping strategies to modulate their electrical properties. For example, InGaAs quantum wells and AlGaAs barrier layers can be grown within a specific temperature window, and the V / III ratio can be optimized to suppress defects. Regarding doping, zinc (Zn) is commonly used as a p-type dopant, and silicon (Si) as an n-type dopant to achieve the desired carrier concentration.

[0003] However, existing MOCVD processes and doping strategies still face a series of technical bottlenecks in practical applications, restricting further improvements in the performance of quantum well devices. First, at the material growth level, insufficient uniformity of temperature distribution within the reaction chamber easily leads to spatial fluctuations in the quantum well material composition, affecting the uniformity of the band structure. Simultaneously, limited precision in matching and controlling growth parameters may result in decreased quantum well interface steepness, wider transition layers, and the introduction of higher concentrations of point defects (such as vacancies and interstitial atoms), damaging the lattice integrity of the material. Second, at the device electrical performance level, traditional p-type Zn dopants are prone to diffusion during subsequent high-temperature processes, causing broadening of the carrier concentration distribution and band distortion at the quantum well interface. Uniform doping distribution can also easily induce localized high current densities and resistive heating effects during device operation, affecting device reliability and lifetime. Existing technologies struggle to achieve atomically sharp interfaces while precisely controlling the doping distribution to synergistically optimize the intrinsic quality of the material and the electrical performance of the device. Summary of the Invention

[0004] In view of this, embodiments of this application provide a method for optimizing epitaxial growth of EEL. One or more embodiments of this application also relate to an apparatus for optimizing epitaxial growth of EEL, a computing device, a computer-readable storage medium, and a computer program, to address the technical deficiencies existing in the prior art.

[0005] In a first aspect, embodiments of this application provide a method for optimizing epitaxial growth of EEL, comprising:

[0006] An n-type capping layer is epitaxially grown on the substrate; On the n-type capping layer, within a first temperature range, a multi-period quantum well active layer having a first V / III ratio and a first growth rate is epitaxially grown, the active layer comprising alternately stacked InGaAs quantum well layers and AlGaAs barrier layers. A p-type confinement layer is epitaxially grown on the active layer; The InGaAs quantum well layer is grown at a temperature of 600°C to 650°C, and the AlGaAs barrier layer is grown at a temperature of 700°C to 750°C. Wherein, the V / III ratio is the molar flow ratio of the group V element precursor to the group III element precursor, and the first V / III ratio is 250; Wherein, the first growth rate is from 0.5 nm / s to 1.0 nm / s; The p-type confinement layer uses carbon as a p-type dopant.

[0007] In one possible implementation, the temperature gradient within the reaction chamber is controlled within ±0.5°C during the epitaxial growth of the multi-period quantum well active layer.

[0008] In one possible implementation, the spatial variation of the In component in the InGaAs quantum well layer is less than 0.5%.

[0009] In one possible implementation, the thickness of the interface transition layer between the InGaAs quantum well layer and the AlGaAs barrier layer is less than 1 nm by controlling the first V / III ratio.

[0010] In one possible implementation, the InGaAs quantum well layer and the AlGaAs barrier layer are grown at the first growth rate, and the uniformity of the single-layer thickness fluctuates by less than 1%.

[0011] In one possible implementation, the n-type capping layer uses silicon as the n-type dopant with a doping concentration of 1 × 10¹. 8 cm - ³.

[0012] In one possible implementation, the p-type confinement layer is a p-type layer with a gradually varying doping concentration, starting from 1 × 10¹ near the active layer. 8 cm - ³, gradually decreasing to 5×10¹ towards the side away from the active layer. 7 cm - ³.

[0013] In one possible implementation, during the growth of the InGaAs quantum well layer, the ratio of the flow rate of the arsenic source gas introduced into the reaction chamber to the total flow rate of the indium and gallium source gases is maintained at the first V / III ratio; during the growth of the AlGaAs barrier layer, the ratio of the flow rate of the arsenic source gas introduced into the reaction chamber to the total flow rate of the aluminum and gallium source gases is maintained at the first V / III ratio.

[0014] In one possible implementation, when switching from growing the InGaAs quantum well layer to growing the AlGaAs barrier layer, the temperature of the reaction chamber is first raised from the lower limit of the first temperature range to the upper limit, and then the aluminum source gas is introduced and its flow rate is stabilized.

[0015] In one possible implementation, a heavily doped p-type contact layer is epitaxially grown on top of the p-type confinement layer. The p-type contact layer also uses carbon as the p-type dopant, and its doping concentration is higher than the peak doping concentration of the p-type confinement layer.

[0016] Secondly, embodiments of this application provide an epitaxial growth optimization apparatus for EEL, comprising: The reaction chamber module is used to support the substrate and provide an epitaxial growth environment. A temperature control module, coupled to the reaction chamber module, is used to control the growth temperature within the reaction chamber module. The temperature control module is configured to control the temperature in a first temperature range of 600°C to 650°C when growing an InGaAs quantum well layer, and to control the temperature in a second temperature range of 700°C to 750°C when growing an AlGaAs barrier layer. A gas delivery module, connected to the reaction chamber module, is used to deliver precursor gas to the reaction chamber module, wherein the gas delivery module is configured to control the molar flow ratio of the input group V precursor to group III precursor to be 250 during the growth of InGaAs quantum well layer or AlGaAs barrier layer. A growth rate control module, communicatively connected to the gas delivery module and the reaction chamber module, is configured to control the growth rate of the InGaAs quantum well layer and the AlGaAs barrier layer between 0.5 nm / s and 1.0 nm / s by adjusting the precursor gas supply and reaction conditions; and, The doping control module, integrated with the gas delivery module, is configured to provide a carbon-containing precursor to the gas delivery module during the growth of the p-type confinement layer, so as to introduce carbon as a p-type dopant into the reaction chamber module.

[0017] Thirdly, embodiments of this application provide a computing device, including: Memory and processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions, which, when executed by the processor, implement the steps of the epitaxial growth optimization method for EEL described above.

[0018] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the epitaxial growth optimization method for EEL described above.

[0019] Fifthly, embodiments of this application provide a computer program, wherein when the computer program is executed in a computer, the computer is instructed to perform the steps of the above-described epitaxial growth optimization method for EEL.

[0020] The technical solution provided in this application firstly involves epitaxially growing an n-type capping layer on a substrate. Subsequently, on the n-type capping layer, an InGaAs quantum well layer is grown within a temperature range of 600°C to 650°C and an AlGaAs barrier layer is grown within a temperature range of 700°C to 750°C by precisely controlling the temperature of the reaction chamber, thereby cyclically constructing a multi-period quantum well active layer. During this process, the molar ratio of group V precursor to group III precursor introduced into the reaction chamber is precisely controlled by a gas delivery system to maintain it stably at 250, while the growth rate of each layer is controlled within the range of 0.5 nm / s to 1.0 nm / s. Finally, on the active layer, a p-type confinement layer with carbon as a p-type dopant is epitaxially grown by introducing a carbon-containing precursor as a dopant, thus completing the entire epitaxial structure. By separately setting and precisely maintaining the optimal growth temperatures for the quantum well layer and the barrier layer, ideal crystal growth kinetics conditions were provided for both, ensuring the intrinsic quality of the material. Maintaining a high V / III ratio of 250 effectively suppressed point defects (such as group III vacancies) caused by insufficient group V elements, reducing the density of nonradiative recombination centers. Limiting the growth rate to a moderate range of 0.5-1.0 nm / s facilitated sufficient atomic migration on the growth surface, thus ensuring both high-speed growth and precise thickness control and good interface atomic arrangement. Using carbon instead of traditional zinc as the p-type dopant avoided dopant diffusion problems in subsequent high-temperature processes, allowing the doping profile and quantum well interface to remain steep. These measures combined ultimately resulted in a quantum well epitaxial wafer possessing high material quality, low defect density, precise structural control, and stable electrical performance. Attached Figure Description

[0021] Figure 1 This is a flowchart of an epitaxial growth optimization method for EEL provided in one embodiment of this application; Figure 2This is a schematic diagram of the structure of an epitaxial growth optimization device for EEL provided in one embodiment of this application; Figure 3 This is a structural block diagram of a computing device provided in one embodiment of this application. Detailed Implementation

[0022] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0023] The terminology used in one or more embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of one or more embodiments of this application. The singular forms “a” and “the” as used in one or more embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in one or more embodiments of this application refers to and includes any or all possible combinations of one or more associated listed items.

[0024] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this application, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this application, and similarly, second may also be referred to as first. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0025] This application provides a method for optimizing epitaxial growth of EEL, and also relates to an apparatus for optimizing epitaxial growth of EEL, a computing device, and a computer-readable storage medium, which will be described in detail in the following embodiments.

[0026] Figure 1 This is a flowchart of an epitaxial growth optimization method for EEL provided in one embodiment of this application.

[0027] See Figure 1 The method specifically includes the following steps: Step 101: Epitaxially grow an n-type capping layer on the substrate.

[0028] Step 102: On the n-type capping layer, within a first temperature range, an epitaxial growth of a multi-period quantum well active layer having a first V / III ratio and a first growth rate is performed. The active layer comprises alternating stacked InGaAs quantum well layers and AlGaAs barrier layers.

[0029] Step 103: On the active layer, an epitaxial p-type confinement layer is grown.

[0030] In some embodiments, during the epitaxial growth of the multi-period quantum well active layer, the temperature gradient within the reaction chamber is controlled within ±0.5°C. This is achieved using an MOCVD reaction chamber equipped with a multi-zone independent heating system, and integrating high-precision thermocouples or infrared temperature measurement arrays below or around the wafer susceptor to monitor the temperature distribution on the growth surface in real time and in situ. Based on the monitoring feedback, the control system dynamically and precisely adjusts the power output of each heating zone, thereby actively compensating for temperature non-uniformity caused by airflow, radiation, and reaction heat, ensuring that the temperature difference between any two points on the entire wafer growth plane does not exceed 1°C (i.e., ±0.5°C). This precise temperature uniformity control has a direct and crucial benefit: fundamentally guaranteeing the spatial uniformity of the indium (In) composition in the epitaxial material, especially in the temperature-sensitive InGaAs quantum well. It strictly limits the fluctuation of In composition to a very small range (e.g., <0.5%), thereby ensuring a high degree of consistency of quantum well band structure, emission wavelength and carrier recombination characteristics across the entire chip and even the entire wafer, significantly improving the uniformity of device performance and production yield.

[0031] In some embodiments, the spatial variation of the In composition in the InGaAs quantum well layer is less than 0.5%. By employing multi-zone heating and closed-loop temperature control techniques to maintain the temperature gradient within the reaction chamber within ±0.5°C, combined with optimized gas flow field design, the uniform mass transport and decomposition / adsorption kinetics of the group III precursor (especially the indium source) above the substrate growth surface are fundamentally guaranteed. This precise process control ensures a high degree of consistency in the probability of indium atoms incorporating into the lattice at both the macroscopic wafer scale and the microscopic quantum well region, thereby successfully suppressing the spatial variation of the key element indium (In) composition in the InGaAs quantum well to below 0.5%. This indicator ensures excellent spatial uniformity of the quantum well's bandgap (i.e., emission wavelength). Edge-emitting laser chips fabricated with this material exhibit significantly improved emission wavelength consistency, which greatly reduces the performance dispersion of different devices on the same wafer and between different batches. This provides a crucial material basis for high-yield, large-scale manufacturing of laser arrays with highly concentrated wavelengths, and directly improves the system performance and reliability of the final devices in applications such as wavelength division multiplexing.

[0032] In some embodiments, by controlling the first V / III ratio, the thickness of the interface transition layer between the InGaAs quantum well layer and the AlGaAs barrier layer is less than 1 nm. By precisely setting and stably maintaining the V / III ratio (i.e., the molar flow ratio of group V to group III precursors) at a high ratio of 250, sufficient and stable group V element (e.g., arsenic) atomic coverage is provided to the growth surface during the growth of the InGaAs quantum well layer and the AlGaAs barrier layer. In specific implementation, when one layer is completed and the next layer is about to be switched (e.g., from InGaAs to AlGaAs), the control system will almost synchronously and rapidly switch the group III metal-organic source (e.g., turn off the indium source and turn on the aluminum source) according to a preset program, while maintaining a high flow rate and stable supply of the arsenic source. This high V / III ratio environment ensures that the growth surface is always saturated with excess group V atoms at the moment of source gas switching, thereby greatly suppressing the mutual diffusion and mixing of group III atoms due to surface migration or memory effect, so that the change of material composition only occurs within a few atomic monolayers. An atomically steep heterojunction interface is achieved, and the physical thickness of the interface transition layer is successfully controlled to less than 1 nm. Such a sharp interface significantly enhances the quantum well's ability to confine charge carriers (electrons and holes), improving the quantum well's density of states and radiative recombination efficiency. This is crucial for reducing the threshold current of lasers, increasing differential gain, and modulating bandwidth.

[0033] In some embodiments, the InGaAs quantum well layer and AlGaAs barrier layer are grown at a first growth rate, with a single-layer thickness uniformity fluctuation of less than 1%. This is achieved by precisely setting and stably controlling the growth rate of the InGaAs quantum well layer and AlGaAs barrier layer within the "first growth rate" range of 0.5 nm / s to 1.0 nm / s. This is specifically achieved through high-precision, high-stability control of the Group III metal-organic source gas flow rate, combined with the synergistic stabilization of the reaction chamber pressure and substrate temperature. At this moderate growth rate, the reaction precursors reaching the substrate surface have sufficient time to migrate and find the lowest-energy lattice sites for orderly arrangement, while avoiding excessive impurity incorporation due to an excessively slow growth rate or growth kinetic instability caused by an excessively fast growth rate. This comprehensive control ensures a highly consistent deposition rate of each epitaxial layer within the wafer plane, thereby achieving a single-layer thickness uniformity fluctuation of less than 1%. This precision setting ensures that the physical thickness of each well and barrier in the multi-period quantum well structure has nanometer-level repeatability in space. This makes the energy level position, optical transition wavelength, and carrier confinement capability of the quantum well highly uniform across the entire chip, improving the consistency of the emission wavelength and the stability of the lateral mode of the edge-emitting laser device. This is crucial for achieving high-performance, high-yield mass production of lasers.

[0034] In some embodiments, silicon is used as the n-type dopant in the n-type capping layer, with a doping concentration of 1 × 10¹. 8 cm - ³. During the growth of the n-type capping layer, silicon-containing precursors such as silane (SiH4) are introduced into the reaction chamber as doping sources. A high-precision mass flow controller is used to precisely match the flow rate of this precursor with that of the main III-V group precursors. Simultaneously, the substrate temperature and growth rate are strictly controlled. This allows silicon (Si) atoms to be incorporated into the AlGaAs lattice through substitution, and the net carrier concentration is stably controlled at 1×10¹. 8 cm - The concentration is approximately 3. This doping strategy has two key advantages. First, silicon doping at this concentration can form a low-resistance ohmic contact base in the n-type capping layer, significantly reducing the device's series resistance. Second, silicon, as a shallow-level donor with an extremely low diffusion coefficient, can effectively prevent significant diffusion of the dopant during subsequent high-temperature growth or processing while achieving high electron concentration. This maintains the steepness of the interface with the active region and the integrity of the electrical performance, providing a highly conductive and stable electron injection layer for the quantum well active region.

[0035] In some embodiments, the p-type confinement layer is a p-type layer with a gradually varying doping concentration, starting from 1 × 10¹ near the active layer. 8 cm - ³, gradually decreasing to 5×10¹ towards the side farther from the active layer. 7 cm - ³. During the growth of the p-type confinement layer, the gas flow rate of the carbon-containing precursor (such as CBr4) is precisely controlled to decrease linearly or stepwise over time. While maintaining other growth parameters stable, this allows the concentration of carbon atoms incorporated into the AlGaAs lattice to decrease from an initial high concentration of 1 × 10¹ adjacent to the active region. 8 cm - ³, gradually and smoothly decreasing along the growth direction to 5 × 10¹ far from the active region. 7 cm - ³, thus forming a p-type layer with a gradually varying doping concentration. This design provides a higher carrier concentration near the active region to reduce contact resistance and improve hole injection efficiency, while the lower concentration away from the active region effectively reduces the optical absorption loss of free carriers. In terms of thermal and reliability, the gradually varying doping profile optimizes the electric field distribution inside the device, avoids carrier accumulation and Joule heat concentration at the interface, significantly reduces the series resistance and operating temperature rise of the device, thereby improving the power conversion efficiency, long-term operating stability and lifetime of the edge-emitting laser.

[0036] In some embodiments, during the growth of the InGaAs quantum well layer, the ratio of the arsenic source gas flow rate to the total flow rate of the indium and gallium source gases introduced into the reaction chamber is maintained at a first V / III ratio; during the growth of the AlGaAs barrier layer, the ratio of the arsenic source gas flow rate to the total flow rate of the aluminum and gallium source gases introduced into the reaction chamber is maintained at a first V / III ratio. During the growth of the InGaAs quantum well layer, the control system precisely maintains the ratio of the arsenic source flow rate (e.g., AsH3) to the total flow rate of the indium source (e.g., TMIn) and gallium source (e.g., TMGa) at the first V / III ratio (250); when switching to the growth of the AlGaAs barrier layer, the control system also precisely maintains the ratio of the same arsenic source flow rate to the total flow rate of the aluminum source (e.g., TMAI) and gallium source at this first V / III ratio (250). The core of this implementation process lies in using the same set of highly stable arsenic source delivery units and dynamically maintaining a constant molar flow rate ratio through closed-loop feedback, based on the total flow rate of the group III source adjusted in real time according to different growth stages. Its key beneficial effect lies in providing a unified, excessive group V atomic chemical environment for the two different material systems, quantum well and barrier layer. This not only ensures the optimal crystal growth stoichiometry for InGaAs and AlGaAs respectively, greatly reducing the generation of various point defects (such as group III vacancies), but more importantly, the constant high V / III ratio background creates consistent and ideal thermodynamic and kinetic conditions for the formation of atomically steep interfaces during material switching, thereby synergistically achieving low defect density and high interface quality throughout the structure.

[0037] In some embodiments, when switching from growing an InGaAs quantum well layer to growing an AlGaAs barrier layer, the temperature of the reaction chamber is first raised from the lower limit of the first temperature range to the upper limit, and then aluminum source gas is introduced and its flow rate is stabilized. When switching from InGaAs quantum well layer to AlGaAs barrier layer growth, the specific implementation process is as follows: First, the arsenic source gas is continuously introduced into the reaction chamber to maintain the stability of the group V element atmosphere and avoid the generation of defects at the interface due to arsenic deficiency. Then, the temperature of the reaction chamber is steadily increased from the lower limit of the first temperature range (600℃) corresponding to the growth of InGaAs quantum well layer to the upper limit (750℃) corresponding to the growth of AlGaAs barrier layer through the temperature control system of the epitaxial equipment. After the temperature stabilizes at the target value and the fluctuation is controlled within ±0.5℃, the aluminum source gas introduction program is started. The aluminum source gas flow rate is precisely adjusted to the preset value and kept stable through the flow controller. At the same time, the ratio of the arsenic source gas flow rate to the total flow rate of aluminum and gallium source gases is maintained at 250, which is the first V / III ratio, and then the epitaxial growth of AlGaAs barrier layer begins. The sequence of raising the temperature before introducing the aluminum source in this process avoids unexpected reactions between the aluminum source gas and other precursor gases at low temperatures, preventing the formation of impurity phases and ensuring precise control of the stoichiometry of the AlGaAs barrier layer. Introducing the aluminum source after a stable temperature rise and stabilization effectively reduces interfacial composition mixing caused by temperature fluctuations and sudden changes in aluminum source flow rate, reducing the thickness of the interfacial transition layer between the InGaAs quantum well layer and the AlGaAs barrier layer (which can be controlled below 1 nm), and improving the interface smoothness and steepness. At the same time, a stable temperature and gas atmosphere can ensure the crystal quality of the AlGaAs barrier layer, reduce defect density, and ultimately help improve the luminous efficiency, threshold current characteristics, and long-term operational stability of the EEL device.

[0038] In some embodiments, a heavily doped p-type contact layer is epitaxially grown on top of the p-type confinement layer. The p-type contact layer also uses carbon as the p-type dopant, and its doping concentration is higher than the peak doping concentration of the p-type confinement layer. Specifically, to maintain the stability of key process parameters such as the reaction chamber temperature, V / III ratio (maintaining a first V / III ratio of 250), and growth rate (0.5 nm / s to 1.0 nm / s), carbon is used as the p-type dopant. By precisely controlling the flow rate of the carbon source gas (such as propane, methane, etc.), the doping concentration of the p-type contact layer is made significantly higher than the peak doping concentration of the p-type confinement layer (i.e., higher than 1 × 10¹). 8 cm -³), ensuring a high carrier concentration in the contact layer; maintaining a stable molar flow ratio of arsenic source to group III element precursor during growth to ensure the crystal integrity and compositional uniformity of the contact layer until the preset contact layer thickness is achieved. A heavily doped p-type contact layer can significantly reduce the contact resistance between the front electrode and the p-type confinement layer, reducing carrier transport losses at the electrode-semiconductor interface and improving current injection efficiency; using the same carbon dopant as the p-type confinement layer avoids interface diffusion contamination or lattice mismatch problems caused by differences in dopant types, ensuring the quality of the interface bonding between the contact layer and the confinement layer and reducing defect generation; a highly doped contact layer can form a good ohmic contact, allowing current to be evenly distributed within the device, avoiding heat loss caused by localized current concentration, thereby improving the electro-optical conversion efficiency, output power stability, and lifespan of the EEL device, while also providing good process compatibility for subsequent electrode fabrication processes.

[0039] This embodiment provides an optimized epitaxial growth method for EEL (Extraction Electrode Microarray) using a metal-organic chemical vapor deposition (MOCVD) system. The specific steps are as follows: First, a GaAs substrate meeting lattice matching requirements is selected. An n-type capping layer is epitaxially grown on the substrate surface. This capping layer uses silicon as the n-type dopant, with the doping concentration precisely controlled at 1×10¹. 8 cm -³, ensuring efficient carrier transport. Subsequently, a multi-period quantum well active layer is epitaxially grown on the n-type capping layer. This active layer consists of alternating stacked InGaAs quantum well layers and AlGaAs barrier layers. During the growth process, the first V / III ratio is strictly controlled to be 250 (i.e., the molar flow ratio of group V element precursors to group III element precursors), and the first growth rate is maintained between 0.5 nm / s and 1.0 nm / s. Specifically, the InGaAs quantum well layer is grown at a temperature of 600℃, and the AlGaAs barrier layer is grown at a temperature of 750℃. The temperature gradient within the reaction chamber is controlled within ±0.5℃ to ensure that the spatial variation of the In composition in the InGaAs quantum well layer is less than 0.5%, while ensuring that the uniformity of the monolayer thickness of the InGaAs quantum well layer and the AlGaAs barrier layer is less than 1%. During the growth of the InGaAs quantum well layer, the ratio of the arsenic source gas flow rate to the total flow rate of the indium and gallium source gases in the reaction chamber was maintained at 250. Similarly, during the growth of the AlGaAs barrier layer, the ratio of the arsenic source gas flow rate to the total flow rate of the aluminum and gallium source gases was maintained at 250. When switching from InGaAs quantum well layer to AlGaAs barrier layer growth, the arsenic source gas was continuously supplied to maintain a stable atmosphere. Then, the reaction chamber temperature was steadily increased from 600℃ to 750℃. After the temperature stabilized and the fluctuations met requirements, the aluminum source gas was introduced and its flow rate stabilized to ensure that the interface transition layer thickness was less than 1 nm. After the active layer growth was completed, a p-type confinement layer was epitaxially grown on its surface. This confinement layer used carbon as the p-type dopant, with a gradually varying doping concentration, starting from 1×10¹ near the active layer. 8 cm - ³, gradually decreasing to 5×10¹ towards the side farther from the active layer. 7 cm - ³. Finally, a heavily doped p-type contact layer is epitaxially grown on top of the p-type confinement layer. This contact layer also uses carbon as the p-type dopant, and its doping concentration is higher than the peak doping concentration of the p-type confinement layer (i.e., higher than 1 × 10¹). 8 cm - (³) This ensures good contact with subsequent electrodes. The EEL epitaxial structure prepared by the method in this embodiment has a steep active layer interface, excellent crystal quality, significantly reduced defect density, and good uniformity of In composition and layer thickness. The doping design of the p-type confinement layer and contact layer reduces carrier transport losses and avoids interface contamination and lattice mismatch problems. Ultimately, the device has higher luminous efficiency, better threshold current characteristics, more stable output power, and longer lifespan. At the same time, it has strong process compatibility and is suitable for large-scale production applications.

[0040] Corresponding to the above method embodiments, this application also provides embodiments of an epitaxial growth optimization apparatus for EEL. Figure 3 A schematic diagram of an epitaxial growth optimization apparatus for EEL (Extravaginal Electron Microarray) according to an embodiment of this application is shown. Figure 3 As shown, the device includes: The reaction chamber module 201 is used to support the substrate and provide an epitaxial growth environment; Temperature control module 202, coupled to reaction chamber module, is used to control the growth temperature within reaction chamber module. The temperature control module is configured to control the temperature in a first temperature range of 600°C to 650°C when growing InGaAs quantum well layer, and to control the temperature in a second temperature range of 700°C to 750°C when growing AlGaAs barrier layer. Gas delivery module 203, connected to reaction chamber module, is used to deliver precursor gas to reaction chamber module. The gas delivery module is configured to control the molar flow ratio of group V precursor to group III precursor to be 250 when growing InGaAs quantum well layer or AlGaAs barrier layer. The growth rate control module 204, communicatively connected to the gas delivery module and the reaction chamber module, is configured to control the growth rate of the InGaAs quantum well layer and the AlGaAs barrier layer between 0.5 nm / s and 1.0 nm / s by adjusting the precursor gas supply and reaction conditions; and, The doping control module 205, integrated with the gas delivery module, is configured to provide a carbon-containing precursor to the gas delivery module during the growth of the p-type confinement layer, so as to introduce carbon as a p-type dopant into the reaction chamber module.

[0041] In one possible implementation, the temperature control module 202 is further configured to control the temperature gradient of the wafer growth plane within the reaction chamber module to within ±0.5℃ during the growth of the InGaAs quantum well layer and the AlGaAs barrier layer. In one possible implementation, the temperature control module 202 includes a multi-zone heater and a closed-loop temperature sensor network for real-time monitoring and zoned adjustment of the temperature distribution within the reaction chamber module.

[0042] In one possible implementation, the gas delivery module 203 includes: A first mass flow controller group for conveying group III precursors, wherein the group III precursors include at least an indium source, a gallium source, and an aluminum source; A second mass flow controller for conveying Group V precursors, wherein the Group V precursors are arsenic sources; And a central controller for receiving a set value of 250 for the molar flow ratio and adjusting the output of the first mass flow controller group and the second mass flow controller in real time to maintain the molar flow ratio.

[0043] In one possible implementation, the central controller is also configured to: when switching from growing an InGaAs quantum well layer to growing an AlGaAs barrier layer, control the gas delivery module to start the delivery of the aluminum source precursor and stabilize the flow rate after the temperature control module has completed the heating.

[0044] In one possible implementation, the growth rate control module 204 establishes a growth rate control model by calibrating the relationship between the mass flow rate of the group III precursor in the gas delivery module and the actual film thickness deposited in the reaction chamber module, and performs real-time feedback control based on the model.

[0045] In one possible implementation, the doping control module 205 includes a dedicated carbon-containing precursor source and its corresponding third mass flow controller for precisely controlling the carbon doping concentration.

[0046] In one possible implementation, the central controller of the doping control module 205 is further configured to: control the third mass flow controller according to a preset concentration gradient program during the growth of the p-type confinement layer, so that the p-type confinement layer is formed from a 1×10¹ ohm diameter near the active layer. 8 cm - ³ Gradually change to 5×10¹ away from one side 7 cm - The doping concentration distribution of ³.

[0047] In one possible implementation, the gas delivery module 203 further includes a fourth mass flow controller for delivering silane, and the doping control module is configured to control the silicon doping concentration at 1 × 10¹ during the growth of the n-type capping layer by controlling the fourth mass flow controller. 8 cm - Approximately 3.

[0048] In one possible implementation, the device also includes an in-situ monitoring module for real-time monitoring of the growth thickness and interface state of the InGaAs quantum well layer and AlGaAs barrier layer, and feeding the monitoring data back to the growth rate control module and the gas delivery module to achieve closed-loop control of the growth rate and interface steepness.

[0049] The above is a schematic scheme of an epitaxial growth optimization apparatus for EEL according to this embodiment. It should be noted that the technical solution of this epitaxial growth optimization apparatus for EEL and the technical solution of the epitaxial growth optimization method for EEL described above belong to the same concept. For details not described in detail in the technical solution of the epitaxial growth optimization apparatus for EEL, please refer to the description of the technical solution of the epitaxial growth optimization method for EEL described above.

[0050] Figure 3 A structural block diagram of a computing device 300 according to an embodiment of this application is shown. The components of the computing device 300 include, but are not limited to, a memory 310 and a processor 320. The processor 320 is connected to the memory 310 via a bus 330, and a database 350 is used to store data.

[0051] The computing device 300 also includes an access device 340, which enables the computing device 300 to communicate via one or more networks 360. Examples of these networks include Public Switched Telephone Network (PSTN), Local Area Network (LAN), Wide Area Network (WAN), Personal Area Network (PAN), or combinations of communication networks such as the Internet. The access device 340 may include one or more of any type of wired or wireless network interface (e.g., a network interface card (NIC)), such as an IEEE 802.11 Wireless Local Area Network (WLAN) wireless interface, a Wi-MAX (Worldwide Interoperability for Microwave Access) interface, an Ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a Bluetooth interface, or a Near Field Communication (NFC) interface.

[0052] In one embodiment of this application, the aforementioned components of the computing device 300 and Figure 3 Other components, not shown, can also be connected to each other, for example, via a bus. It should be understood that... Figure 3 The block diagram of the computing device shown is for illustrative purposes only and is not intended to limit the scope of this application. Those skilled in the art can add or replace other components as needed.

[0053] The computing device 300 can be any type of stationary or mobile computing device, including mobile computers or mobile computing devices (e.g., tablet computers, personal digital assistants, laptop computers, notebook computers, netbooks, etc.), mobile phones (e.g., smartphones), wearable computing devices (e.g., smartwatches, smart glasses, etc.) or other types of mobile devices, or stationary computing devices such as desktop computers or personal computers (PCs). The computing device 300 can also be a mobile or stationary server.

[0054] The processor 320 executes computer-executable instructions, which, when executed by the processor, implement the steps of the epitaxial growth optimization method for EEL described above. The above is an illustrative scheme of a computing device according to this embodiment. It should be noted that the technical solution of this computing device and the technical solution of the epitaxial growth optimization method for EEL described above belong to the same concept. Details not described in detail in the technical solution of the computing device can be found in the description of the technical solution of the epitaxial growth optimization method for EEL described above.

[0055] An embodiment of this application also provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the epitaxial growth optimization method for EEL described above.

[0056] The above is an illustrative scheme of a computer-readable storage medium according to this embodiment. It should be noted that the technical solution of this storage medium belongs to the same concept as the technical solution of the epitaxial growth optimization method for EEL described above. For details not described in detail in the technical solution of the storage medium, please refer to the description of the technical solution of the epitaxial growth optimization method for EEL described above.

[0057] An embodiment of this application also provides a computer program, wherein when the computer program is executed in a computer, the computer is instructed to perform the steps of the above-described epitaxial growth optimization method for EEL.

[0058] The above is an illustrative scheme of a computer program according to this embodiment. It should be noted that the technical solution of this computer program belongs to the same concept as the technical solution of the above-described epitaxial growth optimization method for EEL. For details not described in detail in the technical solution of the computer program, please refer to the description of the technical solution of the above-described epitaxial growth optimization method for EEL.

[0059] The foregoing has described specific embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0060] The computer instructions include computer program code, which may be in the form of source code, object code, executable file, or certain intermediate forms. The computer-readable medium may include any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium may be appropriately added to or subtracted according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media may not include electrical carrier signals and telecommunication signals.

[0061] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of this application are not limited to the described order of actions, because according to the embodiments of this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the embodiments of this application.

[0062] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0063] The preferred embodiments disclosed above are merely illustrative of this application. The optional embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the embodiments of this application. These embodiments are selected and specifically described in this application to better explain the principles and practical applications of the embodiments of this application, thereby enabling those skilled in the art to better understand and utilize this application. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for optimizing epitaxial growth of EEL, characterized in that, include: An n-type capping layer is epitaxially grown on the substrate; On the n-type capping layer, within a first temperature range, a multi-period quantum well active layer having a first V / III ratio and a first growth rate is epitaxially grown, the active layer comprising alternately stacked InGaAs quantum well layers and AlGaAs barrier layers. A p-type confinement layer is epitaxially grown on the active layer; The InGaAs quantum well layer is grown at a temperature of 600°C to 650°C, and the AlGaAs barrier layer is grown at a temperature of 700°C to 750°C. Wherein, the V / III ratio is the molar flow ratio of the group V element precursor to the group III element precursor, and the first V / III ratio is 250; Wherein, the first growth rate is from 0.5 nm / s to 1.0 nm / s; The p-type confinement layer uses carbon as a p-type dopant.

2. The method according to claim 1, characterized in that, During the epitaxial growth of the multi-period quantum well active layer, the temperature gradient within the reaction chamber is controlled within ±0.5℃.

3. The method according to claim 2, characterized in that, In the InGaAs quantum well layer, the spatial variation of the In composition is less than 0.5%.

4. The method according to claim 1, characterized in that, By controlling the first V / III ratio, the thickness of the interface transition layer between the InGaAs quantum well layer and the AlGaAs barrier layer is made less than 1 nm.

5. The method according to claim 1, characterized in that, The InGaAs quantum well layer and the AlGaAs barrier layer are grown at the first growth rate, and the uniformity of the single-layer thickness fluctuates by less than 1%.

6. The method according to claim 1, characterized in that, The n-type capping layer uses silicon as the n-type dopant, with a doping concentration of 1×10¹. 8 cm - ³.

7. The method according to claim 1, characterized in that, The p-type confinement layer is a p-type layer with a gradually varying doping concentration, starting from 1×10¹ near the active layer. 8 cm - ³, gradually decreasing to 5×10¹ towards the side away from the active layer. 7 cm - ³.

8. The method according to claim 1, characterized in that, During the growth of the InGaAs quantum well layer, the ratio of the flow rate of arsenic source gas to the total flow rate of indium and gallium source gases in the reaction chamber is maintained at the first V / III ratio; during the growth of the AlGaAs barrier layer, the ratio of the flow rate of arsenic source gas to the total flow rate of aluminum and gallium source gases in the reaction chamber is maintained at the first V / III ratio.

9. The method according to claim 1, characterized in that, When switching from growing the InGaAs quantum well layer to growing the AlGaAs barrier layer, the temperature of the reaction chamber is first raised from the lower limit of the first temperature range to the upper limit, and then the aluminum source gas is introduced and its flow rate is stabilized.

10. The method according to claim 1, characterized in that, On top of the p-type confinement layer, a heavily doped p-type contact layer is epitaxially grown. The p-type contact layer also uses carbon as the p-type dopant, and its doping concentration is higher than the peak doping concentration of the p-type confinement layer.

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