Non-volatile storage circuit supporting double parallel operation, storage circuit and chip
By designing independent SRAM and RRAM computation paths in NVSRAM, dual parallel computation is achieved, solving the mutual exclusion and timing conflict problems between RRAM and SRAM, improving computational efficiency and functional versatility, and making it suitable for networks such as the Deepsets algorithm.
Patent Information
- Application Number
- CN202610157902.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-04
- Publication Date
- 2026-05-19
AI Technical Summary
In existing NVSRAM-based in-memory computing circuits, the computation/read/write paths of RRAM and SRAM are mutually exclusive, resulting in limited computing power and making it difficult to achieve dual parallel operations.
Design a non-volatile memory circuit that supports dual parallel operation. By forming independent computing paths in SRAM and RRAM cells respectively, and using 6T-SRAM cells and 3T-2R RRAM cells, the multiplication operation of weights and inputs is realized, and data storage and computing tasks are completed through independent read and write channels.
It enables simultaneous parallel computation of two paths in a non-volatile memory circuit, improving computational efficiency and functional versatility. It solves the mutual exclusion and timing conflict problems between RRAM and SRAM, and is suitable for networks such as Deepsets algorithm that require a large number of multiplication operations between different inputs with the same weight.
Smart Images
Figure CN122067575A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuits, and in particular to a non-volatile memory circuit that supports dual parallel operation, and its corresponding in-memory computing circuit based on NVSRAM and CIM chip. Background Technology
[0002] Non-volatile static random access memory, also known as NVSRAM, is a memory device composed of non-volatile components (such as RRAM or MRAM) and SRAM. The non-volatile components can assist the SRAM circuit in backing up and restoring stored data. In NVSRAM-based in-memory computing circuits, the computing functions are usually only implemented by the SRAM circuit.
[0003] In NVSRAM, RRAM circuits are mostly designed with backup / recovery mechanisms, and their conduction paths are mainly used for SET / RESET and state transitions. Without changing the internal connection relationship of the cell, RRAM branches lack independently reusable calculation / read paths. Therefore, under the existing scheme, if the in-memory calculation circuit is designed based on NVSRAM, when using RRAM to perform calculation tasks, it will inevitably be mutually exclusive with the access path of SRAM. This makes it possible for the same NVSRAM type in-memory calculation unit to usually only perform one arithmetic operation task. Summary of the Invention
[0004] To address the problem that existing NVSRAM-based in-memory computing circuits suffer from limited computing power due to mutual exclusion and timing conflicts between SRAM and RRAM, this invention provides a non-volatile memory circuit that supports dual parallel operations, along with its corresponding NVSRAM-based in-memory computing circuit and CIM chip.
[0005] The technical solution provided by this invention is as follows: A non-volatile memory circuit supporting dual parallel operation comprises two parts: an SRAM cell and an RRAM cell. The SRAM cell is a read-write separated SRAM cell including a 6T-SRAM cell and an independent read channel. Storage nodes Q and QB in the 6T-SRAM cell are used for pre-storing weights and supporting multiplication operations between the weights and one of the input channels. The RRAM cell includes three NMOS transistors N7~N9 and two memristors M1 and M2. The drain of N7 is connected to Q, the gate of N7 is connected to the backup word line CWLL, the source of N7 is connected to the drain of N9 and the upper electrode of M1, and the lower electrode of M1 is connected to the backup bit line PBL; the source of N9 is connected to the source line SL, and the gate of N9 is connected to the compute word line RWL; the drain of N8 is connected to QB, the gate of N8 is connected to the backup word line CWLR; the source of N8 is connected to the upper electrode of M2, and the lower electrode of M2 is connected to the backup bit line PBLB.
[0006] In this invention, the RRAM unit is used, on the one hand, to back up and restore the level states of Q and QB through M1 and M2, and on the other hand, to implement the multiplication operation of the weight with another input. The implementation method of the multiplication operation in the RRAM unit includes: using the backed-up resistance state of M1 to represent the weight, and using the level of RWL to represent the input; then, when the read voltage is applied to PBL, the read current flowing through M1 is used to represent the product of the input and the weight.
[0007] As a further improvement of this invention, the operation logic for implementing the multiplication operation between a single-bit weight and a single-bit input in the RRAM cell is as follows: S1: Data is pre-written into the storage node of the 6T-SRAM cell according to the weight, and then CWLL and CWLR are set to high level, and PBL and PBLB are grounded, so as to realize the weight pre-storage through the impedance state of M1 and M2.
[0008] Where M1 is the low-resistivity state LRS characterization weight of 1, and M1 is the high-resistivity state HRS characterization weight of 0.
[0009] S2: Set CWLL and CWLR to low level, SL to ground, RWL to the input level state, and PBL to the read voltage Vread, which is a voltage signal less than the SET voltage of M1 and M2; then the magnitude of the read current Iread flowing through M1 represents the product: Specifically, when RWL is high, the input is 1; when RWL is low, the input is 0. When Iread is greater than the threshold current I0, the product is 1; when Iread is less than the threshold current I0, the product is 0.
[0010] As a further improvement of this invention, the operation logic for implementing the multiplication operation between a single-bit weight and a multi-bit input in the RRAM cell is as follows: S1: Data is pre-written into the storage node of the 6T-SRAM cell according to the weight, and then CWLL and CWLR are set to high level, and PBL and PBLB are grounded, so as to realize the weight pre-storage through the impedance state of M1 and M2.
[0011] Where M1 represents the low-resistivity state with a weight of 1, and M1 represents the high-resistivity state with a weight of 0.
[0012] S2: Set CWLL and CWLR to low level, SL to ground, RWL to the input level state, and PBL to the read voltage Vread; then the magnitude and duration of the read current Iread flowing through M1 represent the product: Specifically, when RWL is high, it indicates that the input is greater than 0, and its value is encoded by the pulse width of RWL; when RWL is low, it indicates that the input is 0. Correspondingly, when Iread is greater than the threshold current I0, it indicates that the product is greater than 0, and its value is encoded by the duration of Iread; when Iread is less than the threshold current I0, it indicates that the product is 0.
[0013] As a further improvement of the present invention, the operation logic for data backup implemented by the RRAM unit is as follows: Initially, both M1 and M2 are set to high impedance. While writing data, CWLL and CWLR are set to high level, and PBL and PBLB are connected to low level. This enables the backup of the original stored data through the impedance state of M1 and M2 after power failure. After the backup is completed, CWLL and CWLR are set to low level.
[0014] The circuit principle for data backup in the RRAM cell is as follows: If the stored data is "1", then Q is high and QB is low. At this time, the upper electrode of M1 is connected to a high level and the lower electrode is connected to a low level, thus it will be switched from a high-impedance state to a low-impedance state; while the upper and lower electrodes of M2 are both connected to a low level, so it will remain in a high-impedance state. Conversely, if the stored data is "0", then Q is low and QB is high. At this time, the upper electrode of M2 is connected to a high level and the lower electrode is connected to a low level, thus it will be switched from a high-impedance state to a low-impedance state; while M1, since both the upper and lower electrodes are connected to a low level, will remain in a high-impedance state.
[0015] Therefore, M1 and M2 back up the level states of the storage nodes Q and QB in the 6T-SRAM, which are used to characterize the stored data, through their non-volatile impedance states. If the storage node connected to M1 or M2 is at a high level, it is in a low impedance state; conversely, if the storage node connected to M1 or M2 is at a low level, it is in a high impedance state.
[0016] The data recovery operation logic implemented by the RRAM unit in this invention is as follows: After the SRAM cell is powered off, CWLL and CWLR are set to high level, and PBL and PBLB are set to the recovery voltage Vrec. Vrec is a voltage signal that is less than the RESET voltage of M1 and M2. After the SRAM cell is powered on again, the memory node connected to the memristor in the low-impedance state is restored to high level, and the memory node connected to the memristor in the high-impedance state is restored to low level, thereby realizing the recovery of the original stored data. After the recovery is completed, CWLL and CWLR are set to low level.
[0017] As a further improvement of this invention, the non-volatile memory circuit supporting dual parallel operation implements data storage function through SRAM cells. The read and write operations in the SRAM cells are completed using independent read and write channels; each read channel is connected to an independent read word line and read bit line. Furthermore, the method for implementing multiplication operations in the SRAM cells is as follows: weights are pre-stored in the storage nodes of the 6T-SRAM cells; the input is represented by the level state of the read word line; and the change in the bit line voltage of the read bit line is used to represent the product of the weights and the input.
[0018] In one embodiment of the present invention, the SRAM cell may be an 8T-SRAM scheme comprising two PMOS transistors P1 and P2 and six NMOS transistors N1 to N6. The circuit connection is as follows: the sources of P1 and P2 are connected to VDD; the sources of N1 and N2 are grounded; the gates of P2 and N2 are connected to the drains of P1 and N1, and are denoted as memory node Q; the gates of P1 and N1 are connected to the drains of P2 and N2, and are denoted as inverted memory node QB; the drain of N3 and the gate of N5 are connected to Q; the source of N3 is connected to bit line BL; the drain of N4 is connected to QB; the source of N4 is connected to bit line BLB; the gates of N3 and N4 are connected to word line WL; the source of N5 is connected to VSS; the drain of N5 is connected to the drain of N6; the source of N6 is connected to read bit line CBL, and the gate of N6 is connected to read word line CWL; among them, P1, P2, and N1~N4 constitute a 6T-SRAM cell, and N5 and N6 constitute the read channel section.
[0019] The operation logic for multiplication between a single-bit weight and a single-bit input in this type of SRAM cell is as follows: S01: In write mode, pre-store the weights in the storage node; and pre-charge CBL to a high level.
[0020] Where Q represents a high level with a weight of 1, and Q represents a low level with a weight of 0.
[0021] S02: The input value is represented by the level state of CWL, and the product operation result is obtained according to the bit line voltage of CBL.
[0022] Specifically, if CWL is high, the input is "1"; if CWL is low, the input is "0"; if the bit line voltage of CBL drops from high to low, the product is 1; if the bit line voltage of CBL remains high, the product is 0.
[0023] In the second embodiment of the present invention, the SRAM cell can adopt a 7T-SRAM scheme including two PMOS transistors P1 and P2 and five NMOS transistors N1 to N5. The circuit connection is as follows: the sources of P1 and P2 are connected to VDD; the sources of N1 and N2 are grounded; the gates of P2 and N2 are connected to the drains of P1 and N1, and are denoted as storage node Q; the gates of P1 and N1 are connected to the drains of P2 and N2, and are denoted as inverting storage node QB; the drain of N3 and the gate of N5 are connected to Q; the source of N3 is connected to bit line BL; the drain of N4 is connected to QB; the source of N4 is connected to bit line BLB; the gates of N3 and N4 are connected to word line WL; the source of N5 is connected to read word line CWL; and the drain of N5 is connected to read bit line CBL. Among them, P1, P2, and N1 to N4 constitute a 6T-SRAM cell, and N5 constitutes the read channel portion.
[0024] The operation logic for multiplication between a single-bit weight and a single-bit input in this type of SRAM cell is as follows: S01: In write mode, pre-store the weights in the storage node; and pre-charge CBL to a high level.
[0025] Where Q represents a high level with a weight of 1, and Q represents a low level with a weight of 0.
[0026] S02: The input value is represented by the level state of CWL, and the product operation result is obtained according to the bit line voltage of CBL.
[0027] Specifically, if CWL is high, the input is "0"; if CWL is low, the input is "1"; if the bit line voltage of CBL drops from high to low, the product is 1; if the bit line voltage of CBL remains high, the product is 0.
[0028] In the third embodiment of the present invention, the SRAM cell can be a 9T-SRAM configuration comprising two PMOS transistors P1 and P2 and seven NMOS transistors N1~N6 and N10, with the circuit connection as follows: The sources of P1 and P2 are connected to VDD; the sources of N1 and N2 are grounded; the gates of P2 and N2 are connected to the drains of P1 and N1, and are denoted as memory node Q; the gates of P1 and N1 are connected to the drains of P2 and N2, and are denoted as inverted memory node QB; the drain of N3 and the gate of N5 are connected to Q; the source of N3 is connected to bit line BL; the drain of N4 is connected to QB; the source of N4 is connected to bit line BLB; the gates of N3 and N4 are connected to word line WL; the source of N5 is connected to read bit line CBL; the drains of N5 and N6 are connected to the source of N10; the source of N6 is connected to read bit line CBLB, and the gate of N10 is connected to read word line CWL; the drain of N10 is grounded; among them, P1, P2, N1~N4 constitute a 6T-SRAM cell, and N5, N6, and N10 constitute the read channel section.
[0029] The operation logic for multiplication between a single-bit weight and a single-bit input in this type of SRAM cell is as follows: S01: In write mode, pre-store the weights in the storage node; and pre-charge CBL to a high level.
[0030] Where Q represents a high level with a weight of 1, and Q represents a low level with a weight of 0.
[0031] S02: The input value is represented by the level state of CWL, and the product operation result is obtained according to the bit line voltage of CBL.
[0032] Specifically, if CWL is high, the input is "1"; if CWL is low, the input is "0"; if the bit line voltage of CBL drops from high to low, the product is 1; if the bit line voltage of CBL remains high, the product is 0.
[0033] The present invention also includes an in-memory computing circuit based on NVSRAM, which includes: an in-memory array, a row driving circuit, a column driving circuit, a sensitive amplifier array, and a quantization circuit.
[0034] The memory array is constructed using non-volatile memory circuits supporting dual parallel operations as described above, arranged as memory cell arrays. Each memory cell in the same column shares bit lines BL, BLB, CBL, PBL, PBLB, or CBLB (if any); each memory cell in the same row shares word lines WL, CWL, CWLL, and CWLR.
[0035] The row drive circuit is used to adjust the level states of WL, CWL, CWLL, and CWLR. The column drive circuit is used to adjust the level states or voltage values of BL, BLB, CBL, PBL, PBLB, or CBLB.
[0036] The sensitive amplifier array is connected to the read line CBL and used to read data. The quantization circuit uses a current-type, voltage-type, time-domain, or integral-domain readout circuit to convert the analog signals representing the computation results output by the SRAM and RRAM cells in each memory unit into corresponding digital quantities.
[0037] The present invention also includes a CIM chip, which is packaged from the aforementioned NVSRAM-based in-memory circuit.
[0038] The present invention has the following beneficial effects: This invention introduces a special 3T-2R structure RRAM cell based on a read-write separated SRAM. This RRAM cell enables the overall circuit to simultaneously achieve non-volatile storage and read-write separation design, further realizing two completely decoupled, independent, and parallel multiplication operations. This significantly improves the computational efficiency of the in-memory circuit when performing similar computational tasks such as those involving Deepsets' algorithm with different inputs of the same weight, enhancing the circuit's functional versatility and practical value.
[0039] This novel non-volatile memory circuit overcomes the shortcomings of existing NVSRAMs, where the non-volatile branch (RRAM) is mainly used for SET / RESET and backup recovery, lacking a reusable independent computation / read path, making it difficult to perform computations within the memory array. It also solves the problem of electrical coupling between the RRAM branch and SRAM memory nodes and access paths, which leads to mutual exclusion and timing conflicts in SRAM computation / read / write when reusing RRAM for read / computation. Attached Figure Description
[0040] Figure 1 This is a circuit diagram of a non-volatile memory circuit with an 8T SRAM cell structure that supports dual parallel operation, as provided in Embodiment 1 of the present invention.
[0041] Figure 2 This is a circuit diagram of a non-volatile memory circuit with a 7T SRAM cell structure that supports dual parallel operation, as provided in Embodiment 1 of the present invention.
[0042] Figure 3 This is a circuit diagram of a non-volatile memory circuit with a 9T SRAM cell structure that supports dual parallel operation, as provided in Embodiment 1 of the present invention.
[0043] Figure 4 This is a circuit architecture diagram of the NVSRAM-based in-memory computing circuit provided in Embodiment 2 of the present invention.
[0044] Figure 5 This is a signal flow diagram for testing the circuit during the data backup operation process.
[0045] Figure 6 This is a signal flow diagram for testing the circuit during the data recovery operation process.
[0046] Figure 7 This is a signal flow graph used to test the circuit's performance during parallel computing operations in the experiment. Detailed Implementation
[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.
[0049] Example 1 Each NVSRAM cell typically consists of two parts: an SRAM cell and an RRAM cell. After circuit structure optimization, both the SRAM and RRAM cells have the potential to perform in-memory computation tasks. However, considering that the RRAM may interfere with the data storage or computation functions of the SRAM during actual computation, a single NVSRAM cell circuit usually only supports one computation task. That is, the complex signal coupling relationship between the SRAM and RRAM cells affects the improvement of the NVSRAM circuit's computing power.
[0050] Building upon this, this embodiment provides a non-volatile memory circuit supporting dual parallel computation, comprising two parts: an SRAM unit and an RRAM unit. This structure ensures the complete data storage function of SRAM and the non-volatility achieved through RRAM, while simultaneously forming independent computation paths within the SRAM and RRAM units, thus enabling two parallel computations with equal weights in both SRAM and RRAM. Based on this characteristic, the non-volatile memory circuit supporting dual parallel computation provided in this embodiment is particularly suitable for networks such as the Deepsets algorithm, which requires performing a large number of multiplications or multiply-accumulate operations between different inputs with equal weights. Furthermore, in practical applications, different computational tasks can be flexibly allocated based on unit characteristics; for example, high-precision computation can be handled by SRAM, while low-precision computation can be handled by RRAM, with both performing collaborative computation. Compared to existing memory architectures based on pure SRAM designs, this non-volatile memory circuit supporting dual parallel computation provided in this embodiment can significantly increase computation speed and improve storage density.
[0051] Specifically, in the non-volatile memory circuit supporting dual parallel operation provided in this embodiment, the SRAM cell adopts a read-write separated SRAM cell. This type of SRAM cell typically consists of a basic 6T-SRAM cell and an independent read channel composed of several MOS transistors. The storage nodes Q and QB in the 6T-SRAM cell are used for data storage on one hand, and for pre-storing weights on the other, thereby cooperating with the read channel to perform multiplication operations between the weights and one of the inputs.
[0052] In practical applications of this embodiment, the circuit structure of the SRAM cell is not limited, and various read-write separated SRAM cells supporting multiplication operations can be used. In the non-volatile memory circuit supporting dual parallel operation provided in this embodiment, the data storage function is still implemented through the SRAM cell. Specifically, read and write operations in the SRAM cell are completed using independent read and write channels; in the 6T-SRAM cell, two NMOS transmission transistors connected to the storage node and bit lines BL and BLB constitute the write channel; the read channel is handled by other newly added MOS transistors connected to the storage node, and the read channel also has independent read word lines and read bit lines. Furthermore, the method for implementing multiplication operations in this type of read-write separated SRAM cell is as follows: weights are pre-stored in the storage node of the 6T-SRAM cell, the input is represented by the level state of the read word line, and the change in the bit line voltage of the read bit line is used to represent the product of the weights and the input. The read, write, and operation logic of read-write separated SRAM cells under different schemes will be described in detail later in conjunction with specific circuit structures.
[0053] In particular, such as Figure 1 As shown, the RRAM cell in this embodiment includes three NMOS transistors N7~N9 and two memristors M1 and M2. The circuit connection is as follows: the drain of N7 is connected to Q, the gate of N7 is connected to the backup word line CWLL, the source of N7 is connected to the drain of N9 and the upper electrode of M1, and the lower electrode of M1 is connected to the backup bit line PBL; the source of N9 is connected to the source line SL, and the gate of N9 is connected to the compute word line RWL; the drain of N8 is connected to QB, and the gate of N8 is connected to the backup word line CWLR; the source of N8 is connected to the upper electrode of M2, and the lower electrode of M2 is connected to the backup bit line PBLB.
[0054] In this embodiment, the RRAM unit is used to back up and restore the level states of Q and QB through M1 and M2, and also to implement the multiplication operation of the weight with another input. The multiplication operation in the RRAM unit is implemented by using the backed-up resistance state of M1 to represent the weight, and using the level of RWL to represent the input. Then, when the read voltage is applied to PBL, the read current flowing through M1 is used to represent the product of the input and the weight.
[0055] Specifically, the data backup operation logic of the RRAM unit in this embodiment is as follows: Initially, both M1 and M2 are set to high impedance (HRS). During data writing, CWLL and CWLR are set to high level (VDD), and PBL and PBLB are connected to low level (0V). This enables backup of the original stored data through the impedance state of M1 and M2 after power failure. After the backup is completed, CWLL and CWLR are set to low level.
[0056] The RRAM cell's data backup circuit works as follows: If the stored data is "1", then Q is high and QB is low. At this time, the upper electrode of M1 is connected to a high level and the lower electrode to a low level, creating a voltage difference across M1. This performs a SET operation on the memristor M1, changing it from a high-resistance state (HRS) to a low-resistance state (LRS). Meanwhile, the upper and lower electrodes of M2 are both connected to low levels, resulting in no voltage difference and maintaining a high-resistance state. Conversely, if the stored data is "0", then Q is low and QB is high. At this time, the upper electrode of M2 is connected to a high level and the lower electrode to a low level, thus changing it from a high-resistance state to a low-resistance state. M1, with both its upper and lower electrodes connected to low levels, remains in a high-resistance state.
[0057] In summary, RRAM achieves backup of the level states of storage nodes Q and QB in 6T-SRAM, which characterize stored data, through the resistance states of M1 and M2. Since the resistance states of memristors M1 and M2 are maintained after power is turned off, the backed-up data is non-volatile. Specifically, if the storage node connected to M1 or M2 is at a high level, it is in a low-resistance state; conversely, if the storage node connected to M1 or M2 is at a low level, it is in a high-resistance state.
[0058] Data recovery refers to the process by which RRAM restores the original voltage level of a storage node after data stored in an SRAM cell is lost due to a power outage, using its own backup data. Specifically, in this embodiment, the data recovery operation logic of the 3T-2R structure RRAM cell is as follows: When the SRAM cell is partially powered off, the stored data in its memory node is lost. At this time, CWLL and CWLR are set to high level, and PBL and PBLB are set to the recovery voltage Vrec. Vrec is a voltage signal that is less than the RESET voltage of M1 and M2. At this time, the recovery voltage Vrec can form charging channels through M1 and M2 respectively and precharge memory nodes Q and QB. Since M1 and M2 are always in a high-resistance state and the other in a low-resistance state when backing up different data, and the charging channel in the low-resistance state charges faster and the charging channel in the high-resistance state charges slower, this pre-charging process can create an initial voltage difference between memory nodes Q and QB, and the direction of this voltage difference is consistent with the direction of the voltage difference between the original memory data corresponding node level states. Under these conditions, when the SRAM power supply is restored, its anti-cross-coupled circuit structure gradually releases the voltage difference, restoring the voltage state of the memory nodes to their pre-power-down state. This causes the memory nodes connected to the low-impedance memristors in M1 and M2 to return to a high level, and the memory nodes connected to the high-impedance memristors to a low level, thus completing the task of restoring the original stored data. After data recovery is complete, CWLL and CWLR are set to low.
[0059] Furthermore, based on the circuit structure of the 3T-2R RRAM cell designed in this embodiment, the operation logic for implementing the multiplication operation between a single-bit weight and a single-bit input is as follows: S1: Data is pre-written into the storage node of the 6T-SRAM cell according to the weight, and then CWLL and CWLR are set to high level, and PBL and PBLB are grounded, so as to realize the weight pre-storage through the impedance state of M1 and M2.
[0060] Where M1 is the low-resistivity state LRS characterization weight of 1, and M1 is the high-resistivity state HRS characterization weight of 0.
[0061] S2: Set CWLL and CWLR to low level, SL to ground, RWL to represent the level state of input IN, and PBL to the read voltage Vread, which is a voltage signal less than the SET voltage of M1 and M2; then the magnitude of the read current Iread flowing through M1 represents the product: when RWL is high level, the input is 1; when RWL is low level, the input is 0; when Iread is greater than the threshold current I0, the product is 1; when Iread is less than the threshold current I0, the product is 0.
[0062] For example, when weight W=1, Q is high, QB is low, M1 is in a low-impedance state, and M2 is in a high-impedance state. When input IN=1, RWL is high, and N9 is on. Simultaneously, when CWLL is low, N7 is off, SL is grounded, and PBL is connected to the read voltage Vread. Therefore, a discharge path from bottom to top is formed across the low-impedance state M1, and the discharge current Iread is equal to Vread / R. M1 ;R M1 This is the equivalent resistance value of M1. Since M1 is in a low-resistance state at this time, Iread is relatively large, in the μA range, which is greater than the preset threshold current I0, indicating that the product is 1, that is, the operation "1×1=1" is realized. When weight W=1, Q is high, QB is low, M1 is in low impedance state, and M2 is in high impedance state. When input IN=0, RWL is low and N9 is off. Simultaneously, when CWLL is low, N7 is off, SL is grounded, and PBL is connected to the read voltage Vread. In the low impedance state, a bottom-to-top discharge path cannot be formed across M1, and the discharge current Iread is 0, less than the preset threshold current I0, indicating a product of 0, i.e., the operation "0×1=0" is achieved.
[0063] When weight W=0, Q is low, QB is high, M1 is in a high-impedance state, and M2 is in a low-impedance state. When input IN=1, RWL is high, and N9 is on. Simultaneously, when CWLL is low, N7 is off, SL is grounded, and PBL is connected to the read voltage Vread. Therefore, a discharge path from bottom to top is formed across the two ends of the high-impedance M1, and the discharge current Iread is equal to Vread / R. M1 ;R M1 This is the equivalent resistance value of M1. Since M1 is in a high-resistance state at this time, Iread is relatively small, in the nA range, which is less than the preset threshold current I0, indicating that the product is 0, that is, the operation "1×0=0" is realized. When weight W=0, Q is low, QB is high, M1 is high impedance, and M2 is low impedance. When input IN=0, RWL is low and N9 is off. Simultaneously, when CWLL is low, N7 is off, SL is grounded, and PBL is connected to the read voltage Vread. In the low impedance state, a bottom-to-top discharge path cannot be formed across M1, and the discharge current Iread is 0, less than the preset threshold current I0, indicating a product of 0, i.e., the operation "0×0=0".
[0064] In the RRAM cell, the duration of the high-level state at the N9 gate terminal characterizes the duration of the discharge current Iread. Therefore, this 3T-2R structure RRAM can be further used to implement multiplication operations between single-bit weights and multi-bit inputs. The operation logic is as follows: S1: Data is pre-written into the storage node of the 6T-SRAM cell according to the weight, and then CWLL and CWLR are set to high level, and PBL and PBLB are grounded, so as to realize the weight pre-storage through the impedance state of M1 and M2.
[0065] Where Q represents a high level with a weight of 1, and Q represents a low level with a weight of 0.
[0066] S2: Set CWLL and CWLR to low level, SL to ground, RWL to the input level state, and PBL to the read voltage Vread; then the magnitude and duration of the read current Iread flowing through M1 represent the product: Specifically, a high level RWL indicates an input greater than 0, and its value is encoded by the pulse width of RWL. Taking a 3-bit input as an example, a high level RWL signal with a single pulse width Δt indicates input IN=001, a high level RWL signal with twice the pulse width 2Δt indicates input IN=010, and so on, with a high level RWL signal with seven times the pulse width 7Δt indicating input IN=111. A low level RWL indicates an input of 0.
[0067] Correspondingly, when Iread is greater than the threshold current I0 and the duration is Δt, it indicates that the input IN=001; when Iread is greater than the threshold current I0 and the duration is 2Δt, it indicates that the input IN=010, and so on. When Iread is greater than the threshold current I0 and the duration is 7Δt, it indicates that the input IN=111. When Iread is less than the threshold current I0, it indicates that the product is 0.
[0068] In one typical solution provided in this embodiment, such as Figure 1 As shown, the SRAM cell can adopt an 8T-SRAM scheme including two PMOS transistors P1 and P2 and six NMOS transistors N1~N6. The circuit connection is as follows: the sources of P1 and P2 are connected to VDD; the sources of N1 and N2 are grounded; the gates of P2 and N2 are connected to the drains of P1 and N1, and are denoted as memory node Q; the gates of P1 and N1 are connected to the drains of P2 and N2, and are denoted as inverted memory node QB; the drain of N3 and the gate of N5 are connected to Q; the source of N3 is connected to bit line BL; the drain of N4 is connected to QB; the source of N4 is connected to bit line BLB; the gates of N3 and N4 are connected to word line WL; the source of N5 is connected to VSS; the drain of N5 is connected to the drain of N6; the source of N6 is connected to read bit line CBL, and the gate of N6 is connected to read word line CWL; among them, P1, P2, and N1~N4 constitute a 6T-SRAM cell, and N5 and N6 constitute the read channel section.
[0069] This type of SRAM cell is a classic 8T read / write separated SRAM. Data writing is achieved through a 6T-SRAM cell section. Specifically, when writing data "1", bit line BL is set to high and BLB to low; conversely, when writing data "0", bit line BL is set to low and BLB to high. Data reading is achieved using the read channel formed by N5 and N6. In operation, the read bit line CBL is pre-charged to high, then the read word line CWL is set to high, and N6 is turned on. If the stored data is 1, then Q is high, and N5 is turned on. At this time, CBL will form a discharge channel to ground through N6 and N5, and the level will drop from high to low, thus reading the data 1. Conversely, if the stored data is 0, then Q is low, and N5 is turned off. At this time, CBL cannot form a discharge channel to ground through N6 and N5 and cannot maintain a high level, thus reading the data 0.
[0070] Correspondingly, the operation logic for multiplication between a single-bit weight and a single-bit input in this type of SRAM cell with an 8T structure is as follows: S01: In write mode, pre-store the weights in the storage node; and pre-charge CBL to a high level.
[0071] Where Q represents a high level with a weight of 1, and Q represents a low level with a weight of 0.
[0072] S02: The input value is represented by the level state of CWL, and the product operation result is obtained according to the bit line voltage of CBL.
[0073] Specifically, if CWL is high, the input is "1"; if CWL is low, the input is "0"; if the bit line voltage of CBL drops from high to low, the product is 1; if the bit line voltage of CBL remains high, the product is 0.
[0074] Similarly, this SRAM cell can also be used to implement multiplication operations between multi-bit inputs and single-bit weights. That is, the value when the input is greater than 1 is represented by the pulse width when CWL is high, while the value when the product is greater than 1 is represented by the discharge amount ΔV of the bit line voltage. The specific circuit principle for implementing multiplication operations in this 8T read-write separated SRAM cell will not be elaborated further in this embodiment.
[0075] In the second solution provided in this embodiment, the SRAM cell can also be as follows: Figure 2As shown, a 7T-SRAM scheme including two PMOS transistors P1 and P2 and five NMOS transistors N1~N5 is configured as follows: the sources of P1 and P2 are connected to VDD; the sources of N1 and N2 are grounded; the gates of P2 and N2 are connected to the drains of P1 and N1, and are denoted as memory node Q; the gates of P1 and N1 are connected to the drains of P2 and N2, and are denoted as inverting memory node QB; the drain of N3 and the gate of N5 are connected to Q; the source of N3 is connected to bit line BL; the drain of N4 is connected to QB; the source of N4 is connected to bit line BLB; the gates of N3 and N4 are connected to word line WL; the source of N5 is connected to read word line CWL; and the drain of N5 is connected to read bit line CBL. P1, P2, and N1~N4 constitute a 6T-SRAM cell, and N5 constitutes the read channel portion.
[0076] Similar to the 8T structure, this type of SRAM cell implements data writing through the 6T-SRAM cell section. Specifically, when writing data "1", bit line BL is set to high and BLB to low; conversely, when writing data "0", bit line BL is set to low and BLB to high. Data reading is achieved using N5 to form the read channel. In practice, the read bit line CBL is pre-charged to high, and the read word line CWL is grounded. If the stored data is 1, Q is high, and N5 is on. CBL then forms a discharge channel to ground through N5, dropping from high to low, thus reading the data 1. Conversely, if the stored data is 0, Q is low, and N5 is off. CBL cannot form a discharge channel to ground through N5 and maintain a high level, thus reading the data 0.
[0077] Accordingly, the operation logic for implementing the multiplication operation between a single-bit weight and a single-bit input in this type of SRAM cell is as follows: S01: In write mode, pre-store the weights in the storage node; and pre-charge CBL to a high level.
[0078] Where Q represents a high level with a weight of 1, and Q represents a low level with a weight of 0.
[0079] S02: The input value is represented by the level state of CWL, and the product operation result is obtained according to the bit line voltage of CBL.
[0080] Specifically, if CWL is high, the input is "0"; if CWL is low, the input is "1"; if the bit line voltage of CBL drops from high to low, the product is 1; if the bit line voltage of CBL remains high, the product is 0.
[0081] Similarly, this SRAM cell can also be used to implement multiplication operations between multi-bit inputs and single-bit weights. That is, the value when the input is greater than 1 is represented by the pulse width when CWL is high, while the value when the product is greater than 1 is represented by the discharge amount ΔV of the bit line voltage. The specific circuit principle for implementing multiplication operations in this 7T read-write separated SRAM cell will not be elaborated further in this embodiment.
[0082] In the third solution of this embodiment, such as Figure 3 As shown, the SRAM cell can adopt a 9T-SRAM scheme including two PMOS transistors P1 and P2 and seven NMOS transistors N1~N6 and N10. The circuit connection is as follows: the sources of P1 and P2 are connected to VDD; the sources of N1 and N2 are grounded; the gates of P2 and N2 are connected to the drains of P1 and N1, and are denoted as memory node Q; the gates of P1 and N1 are connected to the drains of P2 and N2, and are denoted as inverting memory node QB; the drain of N3 is connected to the gate of N5. Q; the source of N3 is connected to bit line BL; the drain of N4 is connected to QB; the source of N4 is connected to bit line BLB; the gates of N3 and N4 are connected to word line WL; the source of N5 is connected to read bit line CBL; the drains of N5 and N6 are connected to the source of N10; the source of N6 is connected to read bit line CBLB, and the gate of N10 is connected to read word line CWL; the drain of N10 is grounded; among them, P1, P2, N1~N4 constitute a 6T-SRAM cell, and N5, N6, and N10 constitute the read channel section.
[0083] Similar to the 8T structure, this type of SRAM cell implements data writing through the 6T-SRAM cell section. Specifically, when writing data "1", bit line BL is set to high and BLB to low; conversely, when writing data "0", bit line BL is set to low and BLB to high. A read channel is formed using N5 and N10 or N6 and N10 to read data. In operation, the read bit line CBL is pre-charged to high, then the read word line CWL is set to high, turning on N10. If the stored data is 1, Q is high, and N5 is on. CBL then forms a discharge channel to ground through N5 and N10, dropping from high to low, thus reading the data 1. Conversely, if the stored data is 0, Q is low, and N5 is off. CBL cannot form a discharge channel to ground through N5 and N10 and cannot maintain a high level, thus reading the data 0. Figure 3 In the 9T-SRAM, the read channels formed by N6 and N10 are similar in principle to those formed by N5 and N10, the only difference being that they complete data reading through the level state of the storage node QB.
[0084] Accordingly, the operation logic for multiplication between a single-bit weight and a single-bit input in this type of 9T SRAM cell is as follows: S01: In write mode, pre-store the weights in the storage node; and pre-charge CBL to a high level.
[0085] Where Q represents a high level with a weight of 1, and Q represents a low level with a weight of 0.
[0086] S02: The input value is represented by the level state of CWL, and the product operation result is obtained according to the bit line voltage of CBL.
[0087] Specifically, if CWL is high, the input is "1"; if CWL is low, the input is "0"; if the bit line voltage of CBL drops from high to low, the product is 1; if the bit line voltage of CBL remains high, the product is 0.
[0088] Similarly, this SRAM cell can also be used to implement multiplication operations between multi-bit inputs and single-bit weights. That is, the value when the input is greater than 1 is represented by the pulse width when CWL is high, while the value when the product is greater than 1 is represented by the discharge amount ΔV of the bit line voltage. The specific circuit principle for implementing multiplication operations in this 9T read-write separated SRAM cell will not be elaborated further in this embodiment.
[0089] In summary, this embodiment introduces a special 3T-2R structure RRAM cell based on the read-write separated SRAM, thereby realizing non-volatile storage, read-write separation design, and complete decoupling of the two paths in a single circuit, without affecting each other, and enabling parallel processing multiplication operation function.
[0090] Example 2 Based on the various circuit schemes provided in Example 1, such as Figure 4 As shown, this embodiment further provides an in-memory computing circuit based on NVSRAM, which includes: an in-memory array, a row driver circuit, a column driver circuit, a sensitive amplifier array, and a quantization circuit. In fact, similar to conventional SRAM-based in-memory computing circuits, the in-memory computing circuit of this embodiment also includes a clock circuit, a mode conversion circuit, and various peripheral circuits for generating, encoding, or decoding input signals or output signals in practical applications. This embodiment will not describe in detail the circuit components commonly required in these different solutions.
[0091] The in-memory array employs non-volatile memory circuits supporting dual parallel operations, as described above, arranged as the in-memory cell array. In-memory cells in the same column share bit lines BL, BLB, CBL, PBL, and PBLB. When the SRAM portion of the in-memory cell is of type 9T, it also shares bit line CBLB. In-memory cells in the same row share word lines WL, CWL, CWLL, and CWLR.
[0092] The row drive circuit is used to adjust the level states of WL, CWL, CWLL, and CWLR. In this embodiment, the level states of WL, CWL, CWLL, and CWLR include a high level state (VDD) and a low level state (0V). The column drive circuit is used to adjust the level states or voltage values of BL, BLB, CBL, PBL, and PBLB; if the SRAM portion of the memory unit uses a 9T type, the column drive circuit is also used to adjust the level state of CBLB. The level states of BL, BLB, CBL, and CBLB include a high level (VDD) and a low level (0V); while the voltage values of PBL and PBLB include the read voltage (Vread), the recovery voltage (Vrec), and 0V.
[0093] The sensitive amplifier array is connected to the read line CBL and used to read data. The quantization circuit uses a current-type, voltage-type, time-domain, or integral-domain readout circuit to convert the analog signals representing the computation results output by the SRAM and RRAM cells in each memory unit into corresponding digital quantities.
[0094] In practical applications, Figure 4 The circuit shown can not only implement non-volatile storage, read-write separation design, and dual parallel multiplication operations, but also further cooperate with peripheral circuits to implement operations such as multiply-accumulate (MAC).
[0095] In practical applications, this embodiment also provides a CIM chip, which is packaged from the aforementioned NVSRAM-based in-memory computing circuit.
[0096] Simulation test To verify the performance and advantages of the non-volatile memory circuit supporting dual parallel operation and its corresponding NVSRAM-based in-memory computing circuit provided in this embodiment, technicians conducted... Figure 4 The performance of the circuit shown was simulated and tested. Considering that the storage and operation functions of the SRAM cell are relatively common, this simulation mainly focuses on the RRAM cell part of the 3T-2R structure.
[0097] I. Data Backup and Recovery This experiment tested the circuit's data backup and recovery functions. The signal flow diagram during the data backup process is shown below. Figure 5As shown in the diagram, the data backup operation requires writing the values stored in the Q and QB cells of the SRAM into the RRAM. In storage mode, the CWLL and CWLR word lines are given multiple high pulse levels, and PBL and PBLB are grounded to create a voltage difference across the RRAM. For the memristor in the Q node section, its t terminal is connected to the Q node voltage, which performs a SET operation on the RRAM, changing it from the default high-resistance state HRS to the low-resistance state LRS. Meanwhile, the voltages across the QB node are both low, and the resistance state remains unchanged as a high-resistance state.
[0098] The signal flow diagram during the data recovery process is as follows: Figure 6 As shown in the figure, a voltage no higher than RESET is applied to PBL and PBLB to precharge the Q and QB nodes respectively. The RRAM of the Q node is LRS, which charges quickly, while the RRAM of the QB node is HRS, which charges slowly. After the power is turned on, the cross-coupling structure of the SRAM itself will amplify this trend, latching the Q node to 1 and the QB to 0, thereby completing the recovery operation.
[0099] II. Multiplication operations in the RRAM section This experiment tested the multiplication function of the RRAM section of the circuit. The signal flow graph during the operation is shown below. Figure 7 As shown in the diagram, a read voltage no higher than SET and RESET is applied to PBL, SL is grounded, RWL is high, and N9 is turned on, thus forming a read path for memristor M1 (or its corresponding branch) and generating a read current. This read current is represented as I5 / b at terminal b; when RWL is high and the memristor corresponding to the weight is in a low-resistance state LRS, I5 / b increases to the µA level, indicating a product of 1.
[0100] The above-described embodiments are merely one implementation of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.
Claims
1. A non-volatile memory circuit supporting dual parallel operation, characterized in that, It includes: The SRAM cell uses a read-write separated SRAM cell including a 6T-SRAM cell and an independent read channel. The storage nodes Q and QB in the 6T-SRAM cell are used for pre-stored weights. SRAM cells support multiplication operations between the weights and one of the inputs; The RRAM cell includes three NMOS transistors N7~N9 and two memristors M1 and M2; the drain of N7 is connected to Q, the gate of N7 is connected to the backup word line CWLL, the source of N7 is connected to the drain of N9 and the upper electrode of M1, and the lower electrode of M1 is connected to the backup bit line PBL; the source of N9 is connected to the source line SL, and the gate of N9 is connected to the calculation word line RWL; the drain of N8 is connected to QB, the gate of N8 is connected to the backup word line CWLR; the source of N8 is connected to the upper electrode of M2, and the lower electrode of M2 is connected to the backup bit line PBLB; The RRAM unit is used to back up and restore the level states of Q and QB through M1 and M2, and to implement the multiplication operation of weight with another input. The implementation method includes: the resistance state after backup of M1 is used to characterize the weight, and the level of RWL is used to characterize the input. When the read voltage is connected to PBL, the read current flowing through M1 is used to characterize the product of the input and the weight.
2. The non-volatile memory circuit supporting dual parallel operation according to claim 1, characterized in that, The operation logic for implementing the multiplication operation between a single-bit weight and a single-bit input in the RRAM unit is as follows: S1: Data is pre-written into the storage node of the 6T-SRAM cell according to the weight, and then CWLL and CWLR are set to high level, and PBL and PBLB are grounded, so as to realize the weight pre-store through the resistive state of M1 and M2. Where M1 is the low-resistivity state LRS characterization weight of 1, and M1 is the high-resistivity state HRS characterization weight of 0; S2: Set CWLL and CWLR to low level, SL to ground, RWL to the input level state, and PBL to the read voltage Vread; then the magnitude of the read current Iread flowing through M1 represents the product: Specifically, when RWL is high, the input is 1; when RWL is low, the input is 0. When Iread is greater than the threshold current I0, the product is 1; when Iread is less than the threshold current I0, the product is 0.
3. The non-volatile memory circuit supporting dual parallel operation according to claim 1, characterized in that: The operation logic for implementing the multiplication operation between a single-bit weight and a multi-bit input in the RRAM unit is as follows: S1: Data is pre-written into the storage node of the 6T-SRAM cell according to the weight, and then CWLL and CWLR are set to high level, and PBL and PBLB are grounded, so as to realize the weight pre-store through the resistive state of M1 and M2. Where Q represents a high level with a weight of 1, and Q represents a low level with a weight of 0; S2: Set CWLL and CWLR to low level, SL to ground, RWL to the input level state, and PBL to the read voltage Vread; then the magnitude and duration of the read current Iread flowing through M1 represent the product: When RWL is high, it indicates that the input is greater than 0, and its value is encoded by the pulse width of RWL; when RWL is low, it indicates that the input is 0. When Iread is greater than the threshold current I0, the product is greater than 0, and its value is encoded by the duration of Iread; when Iread is less than the threshold current I0, the product is 0.
4. The non-volatile memory circuit supporting dual parallel operation according to claim 1, characterized in that, The data backup operation logic of the RRAM unit is as follows: Initially, both M1 and M2 are set to high impedance. While data is being written, CWLL and CWLR are set to high level, and PBL and PBLB are connected to low level. This enables backup of the original stored data through the impedance state of M1 and M2 after power failure. After the backup is completed, CWLL and CWLR are set to low level. Specifically, if the stored data is "1", Q is high and QB is low, then the upper electrode of M1 is connected to a high level and the lower electrode is connected to a low level, and it is converted to a low-impedance state; if both the upper and lower electrodes of M2 are connected to a low level, it remains in a high-impedance state. If the stored data is "0", Q is low and QB is high, then the upper electrode of M2 is connected to a high level and the lower electrode is connected to a low level, and it is converted to a low-impedance state; if both the upper and lower electrodes of M1 are connected to a low level, it remains in a high-impedance state. The data recovery operation logic of the RRAM unit is as follows: After the SRAM cell is powered off, CWLL and CWLR are set to high level, and PBL and PBLB are set to the recovery voltage Vrec. When the SRAM cell is powered on again, the memory node connected to the memristor in the low-impedance state is restored to high level, and the memory node connected to the memristor in the high-impedance state is restored to low level, thereby realizing the recovery of the original stored data. After the recovery is completed, CWLL and CWLR are set to low level.
5. The non-volatile memory circuit supporting dual parallel operation according to claim 1, characterized in that: Data storage is implemented using SRAM cells, with read and write operations in the SRAM cells completed using independent read and write channels; the read channel is connected to read word lines and read bit lines. In the SRAM cell implementing multiplication, the weights are pre-stored in the storage node of the 6T-SRAM cell. The input is represented by the level state of the read word line, and the change of the bit line voltage of the read bit line is used to represent the product of the weights and the input.
6. The non-volatile memory circuit supporting dual parallel operation according to claim 5, characterized in that: The SRAM cell includes two PMOS transistors P1 and P2 and six NMOS transistors N1 to N6, and the circuit connection is as follows: The sources of P1 and P2 are connected to VDD; the sources of N1 and N2 are grounded; the gates of P2 and N2 are connected to the drains of P1 and N1, and are denoted as memory node Q; the gates of P1 and N1 are connected to the drains of P2 and N2, and are denoted as inverted memory node QB; the drain of N3 and the gate of N5 are connected to Q; the source of N3 is connected to bit line BL; the drain of N4 is connected to QB; the source of N4 is connected to bit line BLB; the gates of N3 and N4 are connected to word line WL; the source of N5 is connected to VSS; the drain of N5 is connected to the drain of N6; the source of N6 is connected to read bit line CBL, and the gate of N6 is connected to read word line CWL; wherein, P1, P2, and N1~N4 constitute a 6T-SRAM cell, and N5 and N6 constitute the read channel section; The operation logic for implementing the multiplication operation between a single-bit weight and a single-bit input in the SRAM cell is as follows: S01: In write mode, pre-store the weights in the storage node; and pre-charge CBL to a high level; Where Q represents a high level with a weight of 1, and Q represents a low level with a weight of 0; S02: The input value is represented by the level state of CWL, and the product operation result is obtained according to the bit line voltage of CBL; Specifically, if CWL is high, the input is "1"; if CWL is low, the input is "0"; if the bit line voltage of CBL drops from high to low, the product is 1; if the bit line voltage of CBL remains high, the product is 0.
7. The non-volatile memory circuit supporting dual parallel operation according to claim 5, characterized in that: The SRAM cell includes two PMOS transistors P1 and P2 and five NMOS transistors N1 to N5, and the circuit connection is as follows: The sources of P1 and P2 are connected to VDD; the sources of N1 and N2 are grounded; the gates of P2 and N2 are connected to the drains of P1 and N1, and are denoted as memory node Q; the gates of P1 and N1 are connected to the drains of P2 and N2, and are denoted as inverting memory node QB; the drain of N3 and the gate of N5 are connected to Q; the source of N3 is connected to bit line BL; the drain of N4 is connected to QB; the source of N4 is connected to bit line BLB; the gates of N3 and N4 are connected to word line WL; the source of N5 is connected to read word line CWL; the drain of N5 is connected to read bit line CBL; wherein, P1, P2, N1~N4 constitute a 6T-SRAM cell, and N5 constitutes the read channel section; The operation logic for implementing the multiplication operation between a single-bit weight and a single-bit input in the SRAM cell is as follows: S01: In write mode, pre-store the weights in the storage node; and pre-charge CBL to a high level; Where Q represents a high level with a weight of 1, and Q represents a low level with a weight of 0; S02: The input value is represented by the level state of CWL, and the product operation result is obtained according to the bit line voltage of CBL; Specifically, if CWL is high, the input is "0"; if CWL is low, the input is "1"; if the bit line voltage of CBL drops from high to low, the product is 1; if the bit line voltage of CBL remains high, the product is 0.
8. The non-volatile memory circuit supporting dual parallel operation according to claim 5, characterized in that, The SRAM cell includes two PMOS transistors P1 and P2 and seven NMOS transistors N1~N6 and N10, and the circuit connection is as follows: The sources of P1 and P2 are connected to VDD; the sources of N1 and N2 are grounded; the gates of P2 and N2 are connected to the drains of P1 and N1, and are denoted as memory node Q; the gates of P1 and N1 are connected to the drains of P2 and N2, and are denoted as inverting memory node QB; the drain of N3 and the gate of N5 are connected to Q; the source of N3 is connected to bit line BL; the drain of N4 is connected to QB; the source of N4 is connected to bit line BLB; the gates of N3 and N4 are connected to word line WL; the source of N5 is connected to read bit line CBL; the drains of N5 and N6 are connected to the source of N10; the source of N6 is connected to read bit line CBLB, the gate of N10 is connected to read word line CWL; the drain of N10 is grounded; among them, P1, P2, N1~N4 constitute a 6T-SRAM cell, and N5, N6, and N10 constitute the read channel section; The operation logic for implementing the multiplication operation between a single-bit weight and a single-bit input in the SRAM cell is as follows: S01: In write mode, pre-store the weights in the storage node; and pre-charge CBL to a high level; Where Q represents a high level with a weight of 1, and Q represents a low level with a weight of 0; S02: The input value is represented by the level state of CWL, and the product operation result is obtained according to the bit line voltage of CBL; Specifically, if CWL is high, the input is "1"; if CWL is low, the input is "0"; if the bit line voltage of CBL drops from high to low, the product is 1; if the bit line voltage of CBL remains high, the product is 0.
9. A memory computing circuit based on NVSRAM, characterized in that, It includes: The in-memory array is formed by arranging non-volatile memory circuits supporting dual parallel operation as described in any one of claims 1-8 as an array of in-memory units; each of the in-memory units in the same column shares bit lines BL, BLB, CBL, PBL, PBLB, or CBLB; each of the in-memory units in the same row shares word lines WL, CWL, CWLL, and CWLR. A line drive circuit, which is used to adjust the level states of WL, CWL, CWLL and CWLR; A column drive circuit is used to adjust the level state or voltage value of BL, BLB, CBL, PBL, PBLB, or CBLB. A sensitive amplifier array, connected to the read line CBL, is used to achieve data reading; The quantization circuit employs current-type, voltage-type, time-domain, or integral-domain readout circuits to convert the analog signals representing the computation results output by the SRAM and RRAM units in each memory unit into corresponding digital quantities.
10. A CIM chip, characterized in that, It is packaged from an in-memory computing circuit based on NVSRAM as described in claim 9.