Multi-task queue management method, multi-task queue management device, terminal equipment, chip and chip module

Abstract

This application relates to the field of communication terminal technology, and provides a multi-task queue management method, a multi-task queue management device, a terminal device, a chip, and a chip module. The method includes: each subtask control unit determining the validity of a subtask arbitration request signal and a subtask arbitration request masking signal based on a subtask trigger signal, a subtask priority value, and the current state of the processed subtask, and outputting these to a multi-task arbitration control unit, so that the multi-task arbitration control unit selects the highest-priority valid subtask from the multi-task queue as the target subtask; outputting the target subtask's configuration parameter read signal and the subtask configuration parameter storage base address to a subtask configuration parameter read / write unit to trigger the accelerator to process the target subtask. This method enables hardware to support software configuration of high-priority subtasks interrupting the currently processed subtask, thus ensuring the processing efficiency of high-priority subtasks.

Description

Technical Field

[0001] This application relates to the field of communication terminal technology, and in particular to a multi-task queue management method, a multi-task queue management device, a terminal device, a chip, a chip module, a computer-readable storage medium, and a computer program product. Background Technology

[0002] The convergence of 4G and 5G in the physical layer hardware of wireless communication chips is a key technological means to significantly reduce chip costs. This convergence scheme uses hardware resource reuse design to allow the 4G and 5G physical layers to share a single set of physical layer hardware resources. To adapt to this hardware convergence architecture, the software layer needs to implement coordinated scheduling of 4G / 5G multitasking. On the one hand, the software needs to obtain current network configuration information in real time and dynamically adjust the priority of relevant 4G / 5G subtasks; on the other hand, due to the uniqueness of hardware resources, the software needs to control the execution of 4G / 5G multitasking in a serial manner. 4G stands for Fourth-Generation Mobile Communication Technology, and 5G stands for Fifth-Generation Mobile Communication Technology.

[0003] However, in the traditional software scheduling method mentioned above, multiple tasks are executed serially, which may cause unavoidable delays in the start-up and execution of high-priority subtasks, affecting the processing efficiency of high-priority subtasks. Summary of the Invention

[0004] Therefore, it is necessary to provide a multi-task queue management method, a multi-task queue management device, a terminal device, a chip, a chip module, a computer-readable storage medium, and a computer program product to address the above-mentioned technical problems.

[0005] Firstly, this application provides a multi-task queue management method applied to sub-task control units in a queue manager on a terminal side, wherein each sub-task control unit is connected to a corresponding task configuration interface, and the queue manager further includes a multi-task arbitration control unit and a sub-task configuration parameter read / write unit, wherein the multi-task arbitration control unit is used to connect to each sub-task control unit and the sub-task configuration parameter read / write unit, and the method includes:

[0006] Receive the subtask trigger signal and subtask priority value input from the corresponding task configuration interface;

[0007] Based on the subtask trigger signal, the subtask priority value, and the current state of the processed subtask, determine the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal;

[0008] The validity of the subtask arbitration request signal, the validity of the subtask arbitration request masking signal, the subtask priority value, and the storage base address of the subtask configuration parameters are output to the multitask arbitration control unit. This allows the multitask arbitration control unit to treat the subtasks of the corresponding subtask control unit with valid subtask arbitration request signals and invalid subtask arbitration request masking signals as valid subtasks in the multitask queue. Based on the subtask priority values ​​of each valid subtask, the highest priority valid subtask is selected from the multitask queue as the target subtask. A configuration parameter read signal for the target subtask is generated, and the configuration parameter read signal and the storage base address of the subtask configuration parameters are output to the subtask configuration parameter read / write unit. This allows the subtask configuration parameter read / write unit to trigger the accelerator to process the target subtask.

[0009] In one embodiment, determining the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal based on the subtask trigger signal, the subtask priority value, and the current state of the processed subtask includes:

[0010] Based on the subtask trigger signal, control the subtask arbitration request signal to take effect;

[0011] Based on the priority values ​​of the subtasks to be executed and the priority values ​​of the currently processed subtasks, determine whether the priority of the subtask to be executed is higher than the priority of the currently processed subtask.

[0012] When the priority of the subtask to be executed is higher than the priority of the currently processed subtask, the control subtask arbitration request masking signal takes effect.

[0013] If the priority of the subtask to be executed is lower than the priority of the currently processed subtask, or if the current processed subtask ends, the control subtask arbitration request masking signal is invalid.

[0014] In one embodiment, when the subtask of the subtask control unit is the currently processed subtask, the method further includes:

[0015] If it is detected that the priority of a subtask of another subtask control unit is higher than the priority of the currently processed subtask, an interrupt signal is generated and output to the accelerator; the interrupt signal is used to instruct the accelerator to stop processing the currently processed subtask, generate the current processing subtask end signal and feed it back to each subtask control unit.

[0016] In one embodiment, the method further includes:

[0017] Upon receiving the signal indicating the end of the current processing subtask, the control subtask arbitration request signal is invalidated, and the current processing subtask is removed from the multitask queue.

[0018] Secondly, this application also provides another multi-task queue management method, applied to a multi-task arbitration control unit in a queue manager on the terminal side. The queue manager further includes multiple sub-task control units and a sub-task configuration parameter read / write unit connected to the multi-task arbitration control unit. The method includes:

[0019] The system receives the validity of the subtask arbitration request signal, the validity of the subtask arbitration request masking signal, the subtask priority value, and the base address for storing subtask configuration parameters from each subtask control unit. The validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal are determined by each subtask control unit based on the subtask trigger signal, the subtask priority value, and the current state of the subtask being processed.

[0020] Subtasks of the subtask control unit whose corresponding subtask arbitration request signal is valid and subtask arbitration request masking signal is invalid are considered as valid subtasks in the multitask queue.

[0021] Based on the subtask priority value of each valid subtask, the highest priority valid subtask is selected from the multitask queue and used as the target subtask.

[0022] A configuration parameter read signal for the target subtask is generated, and the configuration parameter read signal and the base address of the subtask configuration parameter storage are output to the subtask configuration parameter read / write unit so that the subtask configuration parameter read / write unit triggers the accelerator to process the target subtask.

[0023] In one embodiment, the trigger accelerator processes the target subtask, including:

[0024] Based on the configuration parameter read signal of the target subtask and the subtask configuration parameter storage base address, the configuration parameters stored at the subtask configuration parameter storage base address are read from the configuration parameter storage source and written to the accelerator.

[0025] After reading the configuration parameters and writing them to the accelerator, a configuration completion trigger signal is generated.

[0026] Upon completion of the configuration, a trigger signal is sent to trigger the accelerator to process the target subtask.

[0027] Thirdly, this application also provides a multi-task queue management device, applied to each sub-task control unit in a queue manager on the terminal side, wherein each sub-task control unit is connected to a corresponding task configuration interface, and the queue manager further includes a multi-task arbitration control unit and a sub-task configuration parameter read / write unit, wherein the multi-task arbitration control unit is used to connect to each sub-task control unit and the sub-task configuration parameter read / write unit, and the device includes:

[0028] The signal and priority value receiving module is used to receive the subtask trigger signal and subtask priority value input from the corresponding task configuration interface;

[0029] The signal validity determination module is used to determine the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal based on the subtask trigger signal, the subtask priority value, and the current processing subtask status.

[0030] The validity and priority value output module is used to output the validity of the subtask arbitration request signal, the validity of the subtask arbitration request masking signal, the subtask priority value, and the storage base address of the subtask configuration parameters to the multitask arbitration control unit. This allows the multitask arbitration control unit to treat the subtasks of the corresponding subtask control unit with valid subtask arbitration request signals and invalid subtask arbitration request masking signals as valid subtasks in the multitask queue. Based on the subtask priority values ​​of each valid subtask, the module selects the highest priority valid subtask from the multitask queue as the target subtask. It then generates a configuration parameter read signal for the target subtask and outputs the target subtask configuration parameter read signal and the subtask configuration parameter storage base address to the subtask configuration parameter read / write unit. This allows the subtask configuration parameter read / write unit to trigger the accelerator to process the target subtask.

[0031] Fourthly, this application also provides another multi-task queue management device, applied to a multi-task arbitration control unit in a queue manager on the terminal side. The queue manager further includes multiple sub-task control units and a sub-task configuration parameter read / write unit connected to the multi-task arbitration control unit. The device includes:

[0032] The validity and priority value receiving module is used to receive the validity of the subtask arbitration request signal, the validity of the subtask arbitration request masking signal, the subtask priority value, and the storage base address of the subtask configuration parameters from each subtask control unit; wherein, the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal are determined by each subtask control unit based on the subtask trigger signal, the subtask priority value, and the current state of the subtask being processed;

[0033] The valid subtask determination module is used to identify the subtasks of the subtask control unit whose corresponding subtask arbitration request signal is valid and subtask arbitration request masking signal is invalid as valid subtasks in the multitask queue.

[0034] The target subtask determination module is used to select the highest priority valid subtask from the multi-task queue based on the subtask priority value of each valid subtask, and use it as the target subtask.

[0035] The read signal and address output module is used to generate a configuration parameter read signal for the target subtask, and output the configuration parameter read signal and the subtask configuration parameter storage base address to the subtask configuration parameter read / write unit so that the subtask configuration parameter read / write unit triggers the accelerator to process the target subtask.

[0036] Fifthly, this application also provides a terminal device, including a queue manager, an accelerator, and multiple task configuration interfaces;

[0037] The queue manager includes:

[0038] Multiple subtask control units, each of which is connected to the task configuration interface, are used to execute the steps of the above method;

[0039] Subtask configuration parameter read / write unit, used to connect to the multitask arbitration control unit;

[0040] The multi-task arbitration control unit is used to connect with the plurality of sub-task control units and the sub-task configuration parameter read / write unit, and is also used to execute the steps of the above method.

[0041] Sixthly, this application also provides a chip configured with a plurality of first pins for connecting to a task configuration interface, and second and third pins for connecting to an accelerator, the chip comprising:

[0042] Multiple subtask control units, each of which is connected to the first pin in a one-to-one manner, are used to execute the steps of the above method;

[0043] The subtask configuration parameter read / write unit is used to connect to the multitask arbitration control unit and the second pin;

[0044] The multi-task arbitration control unit is used to connect with the plurality of sub-task control units, the sub-task configuration parameter read / write unit and the third pin, and is also used to perform the steps of the above method.

[0045] In a seventh aspect, this application also provides a chip module, including a communication module, a power module, a storage module, and a chip as described in the above embodiments, wherein:

[0046] The power module is used to provide power to the chip module;

[0047] The storage module is used to store data and instructions;

[0048] The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices.

[0049] Eighthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, the computer program being executed by a processor using the methods described above.

[0050] Ninthly, this application also provides a computer program product. The computer program product includes a computer program that is executed by a processor using the methods described above.

[0051] In this application, each subtask control unit determines the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal based on the subtask trigger signal, the subtask priority value, and the current state of the processed subtask. The validity of the subtask arbitration request signal, the validity of the subtask arbitration request masking signal, the subtask priority value, and the storage base address of the subtask configuration parameters are output to the multi-task arbitration control unit. This allows the multi-task arbitration control unit to select the highest-priority valid subtask from the multi-task queue as the target subtask. The configuration parameter read signal and the storage base address of the subtask configuration parameters are output to the subtask configuration parameter read / write unit, causing the subtask configuration parameter read / write unit to trigger the accelerator to process the target subtask. By setting the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal, this application enables hardware to support software configuration of high-priority subtasks interrupting the currently processed subtask, thus ensuring the processing efficiency of high-priority subtasks. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is an application environment diagram of a multi-task queue management method in one embodiment;

[0054] Figure 2 This is a flowchart illustrating a multi-task queue management method in one embodiment;

[0055] Figure 3 This is a flowchart illustrating a multi-task queue management method in another embodiment;

[0056] Figure 4 This is a schematic diagram of the queue manager in one embodiment;

[0057] Figure 5 This is a schematic diagram of the control flow of a subtask control unit coordinating with a multitask arbitration control unit and a subtask configuration parameter reading / writing unit in one embodiment.

[0058] Figure 6 This is a structural block diagram of a multi-task queue management device in one embodiment;

[0059] Figure 7 This is a structural block diagram of a multi-task queue management device in another embodiment;

[0060] Figure 8 This is an internal structure diagram of a chip module in one embodiment. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0062] It should be noted that the terms "comprising" and "having," and any variations thereof, as used in this application, are intended to cover non-exclusive inclusion. The term "multiple" as used in this application refers to two or more. The term "and / or" as used in this application refers to one of the solutions, or any combination of multiple solutions.

[0063] The multi-task queue management method provided in this application embodiment can be applied to, for example... Figure 1In the application environment shown, the queue manager 11 of terminal device 1 includes multiple subtask control units 111, a multitask arbitration control unit 112, and a subtask configuration parameter read / write unit 113. Each subtask control unit 111 is connected to a corresponding task configuration interface 12. The multitask arbitration control unit 112 is used to connect to each subtask control unit 111 and the subtask configuration parameter read / write unit 113. The subtask configuration parameter read / write unit 113 is used to connect to the accelerator 13 of terminal device 1. Each subtask control unit 111 determines the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal based on the subtask trigger signal, the subtask priority value, and the current state of the processed subtask. It then outputs the validity of the subtask arbitration request signal, the validity of the subtask arbitration request masking signal, the subtask priority value, and the subtask configuration parameter storage base address to the multitask arbitration control unit 112, so that the multitask arbitration control unit 112 selects the highest-priority valid subtask from the multitask queue as the target subtask. Finally, it outputs the target subtask configuration parameter read signal and the subtask configuration parameter storage base address to the subtask configuration parameter read / write unit 113, so that the subtask configuration parameter read / write unit 113 triggers the accelerator 13 to process the target subtask.

[0064] In one exemplary embodiment, such as Figure 2 As shown, a multi-task queue management method is provided, which can be applied to... Figure 1 Taking the queue manager 11 of terminal device 1 as an example, the method includes the following steps S201 to S203. Wherein:

[0065] Step S201: Receive the subtask trigger signal and subtask priority value input from the corresponding task configuration interface 12.

[0066] Task configuration interface 12 can be a software configuration interface. The design of the multi-task configuration interface 12 allows software to pre-deploy multiple sub-tasks, transferring the complex multi-task queue maintenance work caused by dual-card multi-mode to hardware implementation, effectively reducing software design complexity.

[0067] The subtask trigger signal is used to instruct the subtask control unit 111 to trigger a subtask. After each subtask control unit 111 triggers a subtask, the subtask to be executed is called the subtask to be executed by the subtask control unit 111 itself.

[0068] The subtask priority value is used to characterize the priority of a subtask; the higher the subtask priority value, the higher the priority of the subtask.

[0069] Subtasks can be cell search tasks (cs).

[0070] When a subtask is issued, each subtask control unit 111 can receive the subtask trigger signal and subtask priority value input from the corresponding task configuration interface 12 to trigger its own subtask to be executed.

[0071] After each subtask control unit 111 triggers its own subtask to be executed, it outputs the corresponding subtask arbitration request signal and subtask arbitration request masking signal.

[0072] Each subtask control unit 111 receives a subtask trigger signal and a subtask priority value from the corresponding task configuration interface 12 each time it triggers its own subtask to be executed. The subtask trigger signal, subtask priority value, subtask arbitration request signal and subtask arbitration request masking signal of this time are all one-to-one with the subtask to be executed by the subtask control unit 111.

[0073] Step S202: Determine the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal based on the subtask trigger signal, the subtask priority value, and the current state of the subtask being processed.

[0074] The current status of the subtask being processed includes its task priority and execution status.

[0075] The subtask arbitration request signal is used to indicate that a subtask has been triggered and initiates an arbitration request to the multitask arbitration control unit 112. The subtask arbitration request signal carries validity information. When the subtask arbitration request signal is valid, the multitask arbitration control unit 112 can respond to the subtask arbitration request signal. When the subtask arbitration request signal is invalid, the multitask arbitration control unit 112 can ignore the subtask arbitration request signal.

[0076] The subtask arbitration request masking signal is used to instruct the multitask arbitration control unit 112 to temporarily mask the arbitration request of a subtask. The subtask arbitration request masking signal carries validity information. When the subtask arbitration request masking signal is valid, the multitask arbitration control unit 112 can respond to the subtask arbitration request masking signal. When the subtask arbitration request masking signal is invalid, the multitask arbitration control unit 112 can ignore the subtask arbitration request masking signal.

[0077] When a subtask has a higher priority than the currently processed subtask, the currently processed subtask should be interrupted. However, to ensure hardware control stability, the higher-priority subtask's request can be temporarily masked. This means the subtask arbitration request masking signal can be made valid. Once the currently processed subtask sends a signal indicating that it has finished processing, the masking signal can be released, thus invalidating the subtask arbitration request masking signal and allowing the higher-priority subtask to participate in the arbitration of the multi-task arbitration unit.

[0078] The subtask control unit 111 can determine the validity of the subtask arbitration request signal based on the subtask trigger signal. It can also determine the validity of the corresponding subtask arbitration request masking signal based on the subtask priority value, the current subtask's priority, and its execution status. Therefore, if its own subtask's priority is higher than the current subtask's priority, it can temporarily mask its own subtask's request. Once the current subtask sends a completion signal, it can release its own subtask, allowing it to participate in the multi-task arbitration unit's arbitration.

[0079] Step S203: The validity of the subtask arbitration request signal, the validity of the subtask arbitration request masking signal, the subtask priority value, and the storage base address of the subtask configuration parameters are output to the multitask arbitration control unit 112, so that the multitask arbitration control unit 112 takes the subtasks of the subtask control unit 111 with valid subtask arbitration request signals and invalid subtask arbitration request masking signals as valid subtasks in the multitask queue; according to the subtask priority value of each valid subtask, the highest priority valid subtask is selected from the multitask queue as the target subtask; a configuration parameter read signal for the target subtask is generated, and the configuration parameter read signal and the storage base address of the subtask configuration parameters are output to the subtask configuration parameter read / write unit 113, so that the subtask configuration parameter read / write unit 113 triggers the accelerator 13 to process the target subtask.

[0080] The subtasks whose corresponding subtask arbitration request signals are valid and whose subtask arbitration request masking signals are invalid are the subtasks for which the multitask arbitration control unit 112 needs to respond to the arbitration request. At this time, the multitask arbitration control unit 112 can determine the subtask as a valid subtask.

[0081] The higher the priority value of a subtask, the higher its priority. The multitask arbitration control unit 112 can determine the valid subtask with the highest priority value in the multitask queue as the highest priority valid subtask; it can also use the highest priority valid subtask as the target subtask.

[0082] After determining the target subtask, the multi-task arbitration control unit 112 can generate a configuration parameter read signal for the target subtask. This configuration parameter read signal can also be referred to as the configuration parameter read trigger signal.

[0083] The multi-task arbitration control unit 112 can output the target sub-task configuration parameter read signal and the sub-task configuration parameter storage base address to the sub-task configuration parameter read / write unit 113.

[0084] The subtask configuration parameter read / write unit 113 can read the corresponding configuration parameters and write them to the accelerator 13 according to the configuration parameter read signal and the subtask configuration parameter storage base address of the target subtask, generate a configuration completion trigger signal, and trigger the accelerator 13 to process the target subtask.

[0085] In the above-mentioned multi-task queue management method, by setting the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal, the hardware supports the software configuration of high-priority subtasks interrupting the currently processed subtasks, which can ensure the processing efficiency of high-priority subtasks.

[0086] In one embodiment, the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal are determined based on the subtask trigger signal, the subtask priority value, and the current processing subtask status. The specific steps are as follows: Based on the subtask trigger signal, the subtask arbitration request signal is activated; based on the subtask priority value of the subtask to be executed and the subtask priority value of the currently processing subtask, it is determined whether the priority of the subtask to be executed is higher than the priority of the currently processing subtask; if the priority of the subtask to be executed is higher than the priority of the currently processing subtask, the subtask arbitration request masking signal is activated; if the priority of the subtask to be executed is lower than the priority of the currently processing subtask, or if the current processing subtask end signal is received, the subtask arbitration request masking signal is deactivated.

[0087] When the subtask control unit 111 receives the subtask trigger signal, it can control the subtask arbitration request signal to take effect.

[0088] When the priority value of the subtask to be executed by the subtask control unit 111 is greater than the priority value of the currently processed subtask, it is determined that the priority of the subtask to be executed is higher than the priority of the currently processed subtask; when the priority value of the subtask to be executed by the subtask control unit 111 is lower than the priority value of the currently processed subtask, it is determined that the priority of the subtask to be executed is lower than the priority of the currently processed subtask.

[0089] If the priority of its own pending subtask is higher than the priority of the currently processed subtask, in order to ensure hardware stability, new task arbitration is only performed after the current task processed by accelerator 13 has stabilized. The subtask control unit 111 controls the subtask arbitration request masking signal to take effect. Thus, even if the priority of the subtask control unit 111's own pending subtask is higher, and the subtask arbitration request signal of the subtask control unit 111 is activated, the subtask control unit 111's own pending subtask does not actually participate in the arbitration of the multi-task arbitration unit, and will not affect the output of the multi-task arbitration unit, thereby avoiding conflicts.

[0090] If the current subtask is interrupted or completed normally, the subtask control unit 111 can receive the current subtask completion signal.

[0091] In this embodiment, the subtask arbitration request signal is activated based on the subtask trigger signal; the subtask arbitration request masking signal is activated when the task priority of the subtask to be executed is higher than the task priority of the currently processed subtask; the subtask arbitration request masking signal is deactivated when the task priority of the subtask to be executed is lower than the task priority of the currently processed subtask, or when the currently processed subtask ends, the subtask arbitration request masking signal is deactivated. This allows the hardware to support software configuration of high-priority subtasks interrupting the currently processed subtask, which can improve the processing efficiency of high-priority subtasks while ensuring hardware stability.

[0092] In one embodiment, when the subtask of the subtask control unit 111 is the currently processed subtask, the method provided by this application further includes: when it is detected that the priority of the subtask of another subtask control unit 111 is higher than the priority of the currently processed subtask, generating an interrupt signal and outputting it to the accelerator 13; the interrupt signal is used to instruct the accelerator 13 to stop processing the currently processed subtask, generating a current processing subtask end signal and feeding it back to each subtask control unit 111.

[0093] When the subtask of the subtask control unit 111 is the currently processed subtask, the subtask control unit 111 monitors the task status of each task configuration interface 12 in real time.

[0094] If it is detected that the priority of a subtask of another subtask control unit 111 is higher than the priority of the currently processed subtask, an interrupt signal (which can be called a subtask interruption signal) is generated and output to the accelerator 13 to interrupt the current processing of the accelerator 13, instructing the accelerator 13 to stop processing the currently processed subtask, and generate a current processing subtask end signal and output it to the multi-task arbitration control unit 112 so that the multi-task arbitration control unit 112 can feed back the current processing subtask end signal to each subtask control unit 111.

[0095] If no other subtask control unit 111 is detected to have a higher priority than the currently processed subtask, the accelerator 13 will normally complete the processing of the current subtask. After completing the processing of the current subtask, the accelerator 13 generates a current subtask completion signal and outputs it to the multi-task arbitration control unit 112, so that the multi-task arbitration control unit 112 will feed back the current subtask completion signal to each subtask control unit 111.

[0096] In this embodiment, when the subtask of the subtask control unit 111 is the currently processed subtask, if it is detected that the priority of the subtask of another subtask control unit 111 is higher than the priority of the currently processed subtask, an interrupt signal is generated and output to the accelerator 13, so that the accelerator 13 stops processing the currently processed subtask, generates the current processing subtask end signal and feeds it back to each subtask control unit 111, so that the high-priority subtask does not need to wait for the low-priority subtask to finish before it is started to be executed, supports the interruption of the current processing subtask by the high-priority subtask, and can ensure the processing efficiency of the high-priority subtask.

[0097] In one embodiment, the method provided by this application further includes: upon receiving a signal indicating the end of the current processing subtask, invalidating the subtask arbitration request signal and removing the current processing subtask from the multitask queue.

[0098] When the subtask of the subtask control unit 111 is the currently processed subtask, when the subtask control unit 111 receives the current processing subtask end signal, the control subtask arbitration request signal is invalidated, and the current processing subtask is removed from the multi-task queue. This allows high-priority subtasks to start execution without waiting for low-priority subtasks to finish, supports high-priority subtasks to interrupt the current processing subtask, and can ensure the processing efficiency of high-priority subtasks.

[0099] In one exemplary embodiment, such as Figure 3 As shown, a multi-task queue management method is provided, which can be applied to... Figure 1 Taking the multi-task arbitration control unit 112 in the queue manager 11 of terminal device 1 as an example, the method includes the following steps S301 to S304. Wherein:

[0100] Step S301: Receive the validity of the subtask arbitration request signal, the validity of the subtask arbitration request masking signal, the subtask priority value, and the storage base address of the subtask configuration parameters from each subtask control unit 111; wherein, the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal are determined by each subtask control unit 111 based on the subtask trigger signal, the subtask priority value, and the current state of the processed subtask.

[0101] The subtask trigger signal is used to instruct the subtask control unit 111 to trigger a subtask. After each subtask control unit 111 triggers a subtask, the subtask to be executed is called the subtask to be executed by the subtask control unit 111 itself.

[0102] The subtask priority value is used to characterize the priority of a subtask; the higher the subtask priority value, the higher the priority of the subtask.

[0103] Subtasks can be cell search tasks (cs).

[0104] The current status of the subtask being processed includes its task priority and execution status.

[0105] The subtask arbitration request signal is used to indicate that a subtask has been triggered and initiates an arbitration request to the multitask arbitration control unit 112. The subtask arbitration request signal carries validity information. When the subtask arbitration request signal is valid, the multitask arbitration control unit 112 can respond to the subtask arbitration request signal. When the subtask arbitration request signal is invalid, the multitask arbitration control unit 112 can ignore the subtask arbitration request signal.

[0106] The subtask arbitration request masking signal is used to instruct the multitask arbitration control unit 112 to temporarily mask the arbitration request of a subtask. The subtask arbitration request masking signal carries validity information. When the subtask arbitration request masking signal is valid, the multitask arbitration control unit 112 can respond to the subtask arbitration request masking signal. When the subtask arbitration request masking signal is invalid, the multitask arbitration control unit 112 can ignore the subtask arbitration request masking signal.

[0107] When a subtask has a higher priority than the currently processed subtask, the currently processed subtask should be interrupted. However, to ensure hardware control stability, the higher-priority subtask's request can be temporarily masked. This means the subtask arbitration request masking signal can be made valid. Once the currently processed subtask sends a signal indicating that it has finished processing, the masking signal can be released, thus invalidating the subtask arbitration request masking signal and allowing the higher-priority subtask to participate in the arbitration of the multi-task arbitration unit.

[0108] When a subtask is issued, each subtask control unit 111 can receive the subtask trigger signal and subtask priority value input from the corresponding task configuration interface 12 to trigger its own subtask to be executed.

[0109] After each subtask control unit 111 triggers its own subtask to be executed, it outputs the corresponding subtask arbitration request signal and subtask arbitration request masking signal.

[0110] Each subtask control unit 111 receives a subtask trigger signal and a subtask priority value from the corresponding task configuration interface 12 each time it triggers its own subtask to be executed. The subtask trigger signal, subtask priority value, subtask arbitration request signal, and subtask arbitration request masking signal all correspond one-to-one with the subtask to be executed by that subtask control unit 111 at that time. The subtask control unit 111 can determine the validity of the subtask arbitration request signal based on the subtask trigger signal. It can also determine the validity of the corresponding subtask arbitration request masking signal based on the subtask priority value, the task priority of the currently processed subtask, and its execution status. Therefore, if the priority of its own subtask to be executed is higher than the priority of the currently processed subtask, the subtask to be executed is temporarily masked. Once the currently processed subtask sends a signal indicating the end of its current processing, the subtask to be executed is released, allowing it to participate in the arbitration of the multi-task arbitration unit.

[0111] Step S302: The subtasks of the subtask control unit 111 that have valid subtask arbitration request signals and invalid subtask arbitration request masking signals are designated as valid subtasks in the multitask queue.

[0112] The subtasks whose corresponding subtask arbitration request signals are valid and whose subtask arbitration request masking signals are invalid are the subtasks for which the multitask arbitration control unit 112 needs to respond to the arbitration request. At this time, the multitask arbitration control unit 112 can refer to the subtask as a valid subtask.

[0113] Step S303: Based on the subtask priority value of each valid subtask, select the highest priority valid subtask from the multitask queue as the target subtask.

[0114] The higher the priority value of a subtask, the higher its priority. The multitask arbitration control unit 112 can determine the valid subtask with the highest priority value in the multitask queue as the highest priority valid subtask; it can also use the highest priority valid subtask as the target subtask.

[0115] Step S304: Generate a configuration parameter read signal for the target subtask, and output the configuration parameter read signal and the base address of the subtask configuration parameter storage to the subtask configuration parameter read / write unit 113 so that the subtask configuration parameter read / write unit 113 triggers the accelerator 13 to process the target subtask.

[0116] After determining the target subtask, the multi-task arbitration control unit 112 can generate a configuration parameter read signal for the target subtask. This configuration parameter read signal can also be referred to as the configuration parameter read trigger signal.

[0117] The multi-task arbitration control unit 112 can output the target sub-task configuration parameter read signal and the sub-task configuration parameter storage base address to the sub-task configuration parameter read / write unit 113.

[0118] The subtask configuration parameter read / write unit 113 can read the corresponding configuration parameters and write them to the accelerator 13 according to the configuration parameter read signal and the subtask configuration parameter storage base address of the target subtask, generate a configuration completion trigger signal, and trigger the accelerator 13 to process the target subtask.

[0119] In the above-mentioned multi-task queue management method, by setting the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal, the hardware supports the software configuration of high-priority subtasks interrupting the currently processed subtasks, which can ensure the processing efficiency of high-priority subtasks.

[0120] In one embodiment, the accelerator 13 is triggered to process the target subtask, and the specific steps are as follows: according to the configuration parameter read signal of the target subtask and the subtask configuration parameter storage base address, the configuration parameters stored at the subtask configuration parameter storage base address are read from the configuration parameter storage source 14 and written to the accelerator 13; after the configuration parameters are read and written to the accelerator 13, a configuration completion trigger signal is generated; according to the configuration completion trigger signal, the accelerator 13 is triggered to process the target subtask.

[0121] The subtask configuration parameter read / write unit 113 can write configuration parameters into the configuration register inside the accelerator 13.

[0122] In this embodiment, the subtask configuration parameter read / write unit 113 reads the configuration parameters stored at the subtask configuration parameter storage base address from the configuration parameter storage source 14 and writes them to the accelerator 13, triggering the accelerator 13 to process the target subtask. This enables the hardware to automatically read configuration parameters from the configuration parameter storage source 14 and write them to the accelerator 13, effectively reducing the computational power consumption of reading configuration parameters.

[0123] To better understand the above method, an application embodiment of the multi-task queue management method of this application is described in detail below.

[0124] In wireless communication, cell search tasks are configured in both idle mode (IDLE state) and idle mode (Connect state) when a user equipment (UE) initially joins the network. In dual-SIM multi-mode scenarios, the software needs to maintain unified task scheduling for both SIMs, doubling the complexity. If prior cell information is unknown or channel conditions are poor, some cell search tasks may experience severe accelerator processing delays. In such cases, it's necessary to stop the currently time-consuming cell search tasks to allow higher-priority cell search tasks to preempt accelerator hardware resources and process them as quickly as possible.

[0125] Traditional software scheduling technology primarily uses two independent software architectures for 4G and 5G, maintaining and scheduling cell search tasks separately for two independent accelerator hardware sets. Taking 5G as an example, the software prioritizes the highest-priority cell search tasks based on the current network configuration and writes configuration parameters to the accelerator via the bus. The software configures the next task only after receiving an interrupt from the end of the previous task. This approach has the following drawbacks: each accelerator can only access one task configuration interface, making cell search tasks entirely dependent on sequential software scheduling; the software's method of writing configuration parameters via the bus consumes a large number of MIPS, reducing software scheduling efficiency; and hardware processing is difficult to intervene in, resulting in low software-hardware interaction efficiency. With the trend of 4G / 5G hardware convergence, the two independent software architectures still require task maintenance, scheduling, and parameter configuration for a single hardware accelerator, significantly increasing software design complexity. MIPS stands for Million Instructions Per Second, representing the number of instructions a Central Processing Unit (CPU) can execute per unit of time, reflecting the CPU's performance.

[0126] The convergence of 4G / 5G in the physical layer hardware of wireless communication chips is an effective way to significantly reduce chip costs. Before convergence, 4G and 5G have two independent sets of hardware resources, which are independently scheduled by software. After convergence, 4G and 5G have only one set of hardware resources. The software needs to be flexibly deployed in advance according to the current network conditions, while ensuring that the task configurations of 4G / 5G are arranged serially to avoid conflicts, which greatly increases the complexity of software design. To reduce the software complexity in situations such as dual-SIM multi-mode, the hardware needs to undertake part of the maintenance of the multi-task queue. Furthermore, the hardware and software interfaces can be flexibly expanded to adapt to various future communication chip specifications. In this regard, this embodiment provides a scalable multi-task queue management method, which can be applied to applications such as... Figure 4The queue manager 11 shown is a component of the terminal device 1. The terminal device 1 also includes an accelerator 13 and a configuration parameter storage source 14. The queue manager 11 includes multiple subtask control units 111, a multi-task arbitration control unit 112, and a subtask configuration parameter read / write unit 113. Each subtask control unit 111 is connected to a corresponding task configuration interface 12. The multi-task arbitration control unit 112 is used to connect to each subtask control unit 111, the subtask configuration parameter read / write unit 113, and the accelerator 13. The subtask configuration parameter read / write unit 113 is used to connect to the accelerator 13 and the configuration parameter storage source 14. The configuration parameter storage source 14 can be a configuration parameter storage unit.

[0127] Each subtask control unit 111 receives the subtask trigger signal and subtask priority value input from the corresponding software configuration interface. Based on the task trigger signal, subtask priority value, current subtask processing status, and control information fed back by the multi-task arbitration control unit 112, it outputs the following main control information:

[0128] (1) Subtask Arbitration Request Signal: This indicates that the subtask has been triggered and initiates an arbitration request to the multitask arbitration control unit 112. The subtask arbitration request signal includes validity information. When the subtask arbitration request signal is valid, the multitask arbitration control unit 112 can respond to the subtask arbitration request signal. When the subtask arbitration request signal is invalid, the multitask arbitration control unit 112 can ignore the subtask arbitration request signal.

[0129] (2) Subtask Arbitration Request Masking Signal: Instructs the multitask arbitration control unit 112 to temporarily mask the arbitration request of the subtask. The subtask arbitration request masking signal includes validity information. When the subtask arbitration request masking signal is valid, the multitask arbitration control unit 112 can respond to the subtask arbitration request masking signal. When the subtask arbitration request masking signal is invalid, the multitask arbitration control unit 112 can ignore the subtask arbitration request masking signal.

[0130] When a subtask has a higher priority than the currently processed subtask, the currently processed subtask should be interrupted. However, to ensure hardware control stability, the higher-priority subtask's request can be temporarily masked. This means the subtask arbitration request masking signal can be made valid. Once the currently processed subtask sends a signal indicating that it has finished processing, the masking signal can be released, thus invalidating the subtask arbitration request masking signal and allowing the higher-priority subtask to participate in the arbitration of the multi-task arbitration unit.

[0131] (3) Interruption signal (which can be called subtask interruption signal): indicates that the subtask is being processed, but a higher priority subtask configuration is triggered. The interrupt signal is output to the accelerator 13. After receiving the interrupt signal, the accelerator 13 will stop the current processing task in advance at the constraint time and feed back the current processing subtask end signal to each subtask control unit 111.

[0132] The internal control logic of each subtask control unit 111 is completely equivalent, and their number can be flexibly expanded or reduced according to the complexity of the current task. This facilitates the development, verification, and maintenance of communication chips of different specifications.

[0133] The multi-task arbitration control unit 112 receives subtask arbitration request signals, subtask arbitration request masking signals, subtask priority values, and subtask configuration parameter storage base addresses from each subtask control unit 111. Based on the arbitration of the highest-priority valid subtask in the dequeue, the target subtask is obtained, and a configuration parameter read signal for the target subtask is generated. The target subtask's configuration parameter read signal and subtask configuration parameter storage base address are then output to the subtask configuration parameter read / write unit 113. A valid subtask refers to one whose corresponding subtask arbitration request signal is valid and whose subtask arbitration masking signal is invalid.

[0134] The subtask configuration parameter read / write unit 113 is used to receive the target subtask configuration parameter read signal and the subtask configuration parameter storage base address output by the multi-task arbitration control unit 112, read the configuration parameters stored at the subtask configuration parameter storage base address from the configuration parameter storage source 14, write them into the configuration register inside the accelerator 13, and generate a configuration completion trigger signal to trigger the accelerator 13 to start processing the latest configured target subtask.

[0135] The control flow of each subtask control unit 111, the collaborative multi-task arbitration control unit 112, and the subtask configuration parameter read / write unit 113 is as follows: Figure 5 As shown, different control processes are labeled S501, S502, S503, and S504. Taking subtask control unit 111A (newly triggered subtask) and subtask control unit 111B (currently processing subtask, i.e., accelerator 13 is processing the subtask) as examples, after being triggered in process S501, subtask control unit 111A enters process S502. Subtask control unit 111A performs the following key control actions in process S501:

[0136] (1) The subtask arbitration request signal of the subtask control unit 111A is activated.

[0137] (2) Subtask arbitration request masking signal control of subtask control unit 111A: The accelerator 13 is currently processing a subtask of subtask unit 2, which is called the currently processed subtask. Subtask control unit 111A determines whether the priority of its own subtask to be executed is higher than the priority of the currently processed subtask:

[0138] 1) When the priority of its own subtask to be executed is higher than the priority of the currently processed subtask, in order to ensure hardware stability, new task arbitration is only performed after the current task processed by accelerator 13 has stabilized. The subtask control unit 111A controls the subtask arbitration request masking signal to take effect. In this way, even if the priority of the subtask to be executed by the subtask control unit 111A is higher, and the subtask arbitration request signal of the subtask control unit 111A is controlled to take effect, the subtask to be executed by the subtask control unit 111A does not actually participate in the arbitration of the multi-task arbitration unit, and will not affect the output of the multi-task arbitration unit, thus avoiding conflicts.

[0139] 2) If the priority of its own subtask to be executed is lower than the priority of the currently processed subtask, the subtask control unit 111A invalidates the subtask arbitration request masking signal and processes it normally in the queue according to priority. Alternatively, upon receiving the end signal of the currently processed subtask, the subtask control unit 111A invalidates the subtask arbitration request masking signal, allowing its own subtask to be executed to actually participate in the arbitration of the multi-task arbitration unit.

[0140] (3) Interrupt signal control of subtask control unit 111B: Subtask control unit 111B is in process S503 and monitors the task status of each task configuration interface 12 in real time:

[0141] 1) If the priority of the subtask of the subtask control unit 111A is detected to be higher than the priority of the currently processed subtask, an interrupt signal of the subtask control unit 111B is generated and output to the accelerator 13 to interrupt the current processing of the accelerator 13, instructing the accelerator 13 to stop processing the currently processed subtask, and generating a current processing subtask end signal and outputting it to the multi-task arbitration control unit 112, so that the multi-task arbitration control unit 112 will feed back the current processing subtask end signal to each subtask control unit 111;

[0142] 2) If no subtask with a higher priority than the current subtask is detected, the accelerator 13 will complete the current subtask normally. After completing the current subtask, the accelerator 13 generates a current subtask completion signal and outputs it to the multi-task arbitration control unit 112, so that the multi-task arbitration control unit 112 will feed back the current subtask completion signal to each subtask control unit 111.

[0143] Regardless of the scenario, the subtask control unit 111B will eventually receive the end signal for the currently processed subtask. The subtask control unit 111B will then jump from process S503 to process S503, and the subtask arbitration request signal will be invalidated, thus removing the currently processed subtask from the multitasking queue. Combined with (2) above, at this point, the subtask to be executed by the subtask control unit 111A will be arbitrated by the multitasking arbitration unit, and the process will jump from process S502 to process S503.

[0144] After the subtask control unit 111A enters process S503, the following key control actions are performed:

[0145] (1) The subtask arbitration request signal of the subtask control unit 111A continues to be effective;

[0146] (2) Based on the judgment of the current new arbitration task, the multi-task arbitration control unit 112 determines the subtask to be executed by the subtask control unit 111A as the target subtask and generates a configuration parameter read signal for the target subtask. This configuration parameter read signal can be called a configuration parameter read trigger signal. The multi-task arbitration control unit 112 can output the target subtask configuration parameter read signal and the subtask configuration parameter storage base address to the subtask configuration parameter read / write unit 113. The subtask configuration parameter read / write unit 113 can read the configuration parameters of the target subtask from the configuration parameter storage source 14, write them into the configuration register inside the accelerator 13, and generate a configuration completion trigger signal to trigger the accelerator 13 to start processing the target subtask. At this time, the target subtask can be called the currently processed subtask.

[0147] (3) After the accelerator 13 finishes processing the subtask to be executed by the subtask control unit 111A, it generates a signal indicating the end of the current subtask. The subtask control unit 111A jumps from process S503 to process S504.

[0148] After the subtask control unit 111A enters process S504, its subtask arbitration request signal becomes invalid, and it removes its currently processed subtask from the multitasking queue. It then jumps from process S504 to process S501, waiting for the next subtask to be triggered.

[0149] The scalable multi-task queue management method provided in this embodiment can be applied to cell search scenarios, where the subtask can be a cell search task. In this scenario, accelerator 13 can be a 4G / 5G converged accelerator 13. However, it should be understood that in other application scenarios, accelerator 13 can also be other modules such as cell measurement and downlink main path processing.

[0150] The scalable multi-task queue management method provided in this embodiment can be applied to the software and hardware interaction of the 4G / 5G accelerator 13. The design of the multi-task configuration interface 12 supports the software to pre-issue multiple sub-tasks, transferring the complex multi-task queue maintenance work brought about by dual-SIM multi-mode to hardware implementation, which can effectively reduce the complexity of software design. The hardware supports reading configuration parameters from the storage unit and writing them into the accelerator 13, which can effectively reduce the computing power consumption of software configuration parameters. The hardware supports the software to configure high-priority sub-tasks to interrupt the currently processed sub-tasks, maximizing the scheduling efficiency of high-priority sub-tasks and ensuring the processing efficiency of high-priority sub-tasks.

[0151] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0152] Based on the same inventive concept, this application also provides a multi-task queue management device for implementing the multi-task queue management method described above. It includes sub-task control units applied to a queue manager on the terminal side, each sub-task control unit being connected to a corresponding task configuration interface. The queue manager further includes a multi-task arbitration control unit and a sub-task configuration parameter read / write unit, the multi-task arbitration control unit being connected to the sub-task control units and the sub-task configuration parameter read / write unit. Furthermore, this device can be applied to or integrated into a chip or chip module, for example. The solution provided by this device is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more embodiments of the multi-task queue management device provided below can be found in the limitations of the multi-task queue management method described above, and will not be repeated here.

[0153] In one exemplary embodiment, such as Figure 6 As shown, a multi-task queue management device is provided, wherein:

[0154] The signal and priority value receiving module 601 is used to receive the subtask trigger signal and subtask priority value input from the corresponding task configuration interface;

[0155] The signal validity determination module 602 is used to determine the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal based on the subtask trigger signal, the subtask priority value and the current processing subtask status;

[0156] The validity and priority value output module 603 is used to output the validity of the subtask arbitration request signal, the validity of the subtask arbitration request masking signal, the subtask priority value, and the storage base address of the subtask configuration parameters to the multitask arbitration control unit. This allows the multitask arbitration control unit to treat the subtasks of the corresponding subtask control unit with valid subtask arbitration request signals and invalid subtask arbitration request masking signals as valid subtasks in the multitask queue. Based on the subtask priority values ​​of each valid subtask, the module selects the highest priority valid subtask from the multitask queue as the target subtask. The module generates a configuration parameter read signal for the target subtask and outputs the configuration parameter read signal and the storage base address of the subtask configuration parameters to the subtask configuration parameter read / write unit. This allows the subtask configuration parameter read / write unit to trigger the accelerator to process the target subtask.

[0157] In one embodiment, the signal validity determination module 602 is further configured to: control the subtask arbitration request signal to take effect according to the subtask trigger signal; determine whether the priority of the subtask to be executed is higher than the priority of the currently processed subtask based on the subtask priority value of the subtask to be executed and the subtask priority value of the currently processed subtask; control the subtask arbitration request masking signal to take effect if the task priority of the subtask to be executed is higher than the task priority of the currently processed subtask; and control the subtask arbitration request masking signal to be invalid if the task priority of the subtask to be executed is lower than the task priority of the currently processed subtask, or if a current processed subtask end signal is received.

[0158] In one embodiment, when the subtask of the subtask control unit is the currently processed subtask, the device further includes an interrupt signal generation module, configured to: generate an interrupt signal and output it to the accelerator when it is detected that the priority of the subtask of another subtask control unit is higher than the priority of the currently processed subtask; the interrupt signal is used to instruct the accelerator to stop processing the currently processed subtask, generate the current processed subtask end signal and feed it back to each subtask control unit.

[0159] In one embodiment, the apparatus further includes a task exit module, configured to: invalidate the subtask arbitration request signal and exit the current processing subtask from the multitask queue upon receiving the current processing subtask end signal.

[0160] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0161] Based on the same inventive concept, this application also provides another multi-task queue management device for implementing the multi-task queue management method described above. This device is applied to a multi-task arbitration control unit in a queue manager on the terminal side. The queue manager further includes multiple sub-task control units and a sub-task configuration parameter read / write unit connected to the multi-task arbitration control unit. Furthermore, this device can be applied to or integrated into a chip or chip module, for example. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more multi-task queue management device embodiments provided below can be found in the limitations of the multi-task queue management method described above, and will not be repeated here.

[0162] In one exemplary embodiment, such as Figure 7 As shown, another multi-task queue management device is provided, wherein:

[0163] The validity and priority value receiving module 701 is used to receive the validity of the subtask arbitration request signal, the validity of the subtask arbitration request masking signal, the subtask priority value, and the storage base address of the subtask configuration parameters from each subtask control unit; wherein, the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal are determined by each subtask control unit based on the subtask trigger signal, the subtask priority value, and the current state of the subtask being processed;

[0164] The valid subtask determination module 702 is used to identify the subtasks of the subtask control unit whose corresponding subtask arbitration request signal is valid and subtask arbitration request masking signal is invalid as valid subtasks in the multitask queue.

[0165] The target subtask determination module 703 is used to select the highest priority valid subtask from the multi-task queue based on the subtask priority value of each valid subtask, and use it as the target subtask.

[0166] The read signal and address output module 704 is used to generate a configuration parameter read signal for the target subtask, and output the configuration parameter read signal and the subtask configuration parameter storage base address to the subtask configuration parameter read / write unit so that the subtask configuration parameter read / write unit triggers the accelerator to process the target subtask.

[0167] In one embodiment, the read signal and address output module 704 is further configured to: read the configuration parameters stored at the subtask configuration parameter storage base address from the configuration parameter storage source and write the configuration parameters stored at the subtask configuration parameter storage base address to the accelerator according to the configuration parameter read signal and the subtask configuration parameter storage base address; after reading the configuration parameters and writing them to the accelerator, generate a configuration completion trigger signal; and trigger the accelerator to process the target subtask according to the configuration completion trigger signal.

[0168] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0169] In one embodiment, a method such as Figure 1 The terminal device 1 shown includes a queue manager 11, an accelerator 13, and multiple task configuration interfaces 12;

[0170] The queue manager 11 includes:

[0171] Multiple subtask control units 111, each subtask control unit 111 is connected to the task configuration interface 12, and the subtask control unit 111 is used to execute the steps of the above method;

[0172] Subtask configuration parameter read / write unit 113 is used to connect to multitask arbitration control unit 112;

[0173] The multi-task arbitration control unit 112 is used to connect with multiple sub-task control units 111 and the sub-task configuration parameter read / write unit 113, and is also used to perform the steps of the above method.

[0174] In one embodiment, a chip is also provided, configured with a plurality of first pins for connecting to a task configuration interface 12, and second and third pins for connecting to an accelerator 13, the chip comprising:

[0175] Multiple subtask control units 111, each subtask control unit 111 is connected to the first pin in a one-to-one correspondence, and the subtask control unit 111 is used to execute the steps of the above method;

[0176] Subtask configuration parameter read / write unit 113 is used to connect to multitask arbitration control unit 112 and second pin;

[0177] The multi-task arbitration control unit 112 is used to connect with multiple sub-task control units 111, sub-task configuration parameter read / write unit 113 and third pin, and is also used to perform the steps of the above method.

[0178] It is understood that the chip involved in the embodiments of this application may be a field-programmable gate array (FPGA), may be an application-specific integrated circuit (ASIC), may be a system on chip (SoC), may be a central processor unit (CPU), may be a network processor (NP), may be a digital signal processor (DSP), may be a microcontroller unit (MCU), may be a programmable logic device (PLD) or other integrated chips, etc.

[0179] In one embodiment, a method such as Figure 8 The chip module shown includes a communication module, a power module, a storage module, and a chip as described in the above embodiments, wherein:

[0180] The power module is used to provide power to the chip module;

[0181] Storage modules are used to store data and instructions;

[0182] The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices.

[0183] The implementation method of this chip module can be found in the relevant content of the above chip embodiment, and will not be repeated here.

[0184] In one embodiment, a computer-readable storage medium is also provided. The computer-readable storage medium stores a computer program thereon, the computer program being executed by a processor using the methods described above.

[0185] In one embodiment, a computer program product is also provided. The computer program product includes a computer program that is executed by a processor using the methods described above.

[0186] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0187] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0188] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0189] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A multi-task queue management method, characterized in that, The method includes subtask control units applied in a queue manager on the terminal side, each subtask control unit being connected to a corresponding task configuration interface. The queue manager also includes a multi-task arbitration control unit and a subtask configuration parameter read / write unit. The multi-task arbitration control unit is used to connect to each subtask control unit and the subtask configuration parameter read / write unit. Receive the subtask trigger signal and subtask priority value input from the corresponding task configuration interface; Based on the subtask trigger signal, the subtask priority value, and the current state of the processed subtask, determine the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal; The validity of the subtask arbitration request signal, the validity of the subtask arbitration request masking signal, the subtask priority value, and the storage base address of the subtask configuration parameters are output to the multitask arbitration control unit. This allows the multitask arbitration control unit to treat the subtasks of the corresponding subtask control unit with valid subtask arbitration request signals and invalid subtask arbitration request masking signals as valid subtasks in the multitask queue. Based on the subtask priority values ​​of each valid subtask, the highest priority valid subtask is selected from the multitask queue as the target subtask. A configuration parameter read signal for the target subtask is generated, and the configuration parameter read signal and the storage base address of the subtask configuration parameters are output to the subtask configuration parameter read / write unit. This allows the subtask configuration parameter read / write unit to trigger the accelerator to process the target subtask.

2. The method according to claim 1, characterized in that, The step of determining the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal based on the subtask trigger signal, the subtask priority value, and the current state of the processed subtask includes: Based on the subtask trigger signal, control the subtask arbitration request signal to take effect; Based on the priority values ​​of the subtasks to be executed and the priority values ​​of the currently processed subtasks, determine whether the priority of the subtask to be executed is higher than the priority of the currently processed subtask. When the priority of the subtask to be executed is higher than the priority of the currently processed subtask, the control subtask arbitration request masking signal takes effect. If the priority of the subtask to be executed is lower than the priority of the currently processed subtask, or if the current processed subtask ends, the control subtask arbitration request masking signal is invalid.

3. The method according to claim 2, characterized in that, When the subtask in the subtask control unit is the currently processed subtask, the method further includes: If it is detected that the priority of a subtask of another subtask control unit is higher than the priority of the currently processed subtask, an interrupt signal is generated and output to the accelerator; the interrupt signal is used to instruct the accelerator to stop processing the currently processed subtask, generate the current processing subtask end signal and feed it back to each subtask control unit.

4. The method according to claim 3, characterized in that, The method further includes: Upon receiving the signal indicating the end of the current processing subtask, the control subtask arbitration request signal is invalidated, and the current processing subtask is removed from the multitask queue.

5. A multi-task queue management method, characterized in that, A multi-task arbitration control unit applied in a queue manager on the terminal side, wherein the queue manager further includes multiple sub-task control units and a sub-task configuration parameter read / write unit connected to the multi-task arbitration control unit, the method comprising: The system receives the validity of the subtask arbitration request signal, the validity of the subtask arbitration request masking signal, the subtask priority value, and the base address for storing subtask configuration parameters from each subtask control unit. The validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal are determined by each subtask control unit based on the subtask trigger signal, the subtask priority value, and the current state of the subtask being processed. Subtasks of the subtask control unit whose corresponding subtask arbitration request signal is valid and subtask arbitration request masking signal is invalid are considered as valid subtasks in the multitask queue. Based on the subtask priority value of each valid subtask, the highest priority valid subtask is selected from the multitask queue and used as the target subtask. A configuration parameter read signal for the target subtask is generated, and the configuration parameter read signal and the base address of the subtask configuration parameter storage are output to the subtask configuration parameter read / write unit so that the subtask configuration parameter read / write unit triggers the accelerator to process the target subtask.

6. The method according to claim 5, characterized in that, The trigger accelerator processes the target subtask, including: Based on the configuration parameter read signal of the target subtask and the subtask configuration parameter storage base address, the configuration parameters stored at the subtask configuration parameter storage base address are read from the configuration parameter storage source and written to the accelerator. After reading the configuration parameters and writing them to the accelerator, a configuration completion trigger signal is generated. Upon completion of the configuration, a trigger signal is sent to trigger the accelerator to process the target subtask.

7. A multi-task queue management device, characterized in that, The device includes subtask control units in a queue manager applied on the terminal side, each subtask control unit being connected to a corresponding task configuration interface. The queue manager also includes a multi-task arbitration control unit and a subtask configuration parameter read / write unit. The multi-task arbitration control unit is used to connect to each subtask control unit and the subtask configuration parameter read / write unit. The signal and priority value receiving module is used to receive the subtask trigger signal and subtask priority value input from the corresponding task configuration interface; The signal validity determination module is used to determine the validity of the subtask arbitration request signal and the validity of the subtask arbitration request masking signal based on the subtask trigger signal, the subtask priority value, and the current processing subtask status. The validity and priority value output module is used to output the validity of the subtask arbitration request signal, the validity of the subtask arbitration request masking signal, the subtask priority value, and the storage base address of the subtask configuration parameters to the multitask arbitration control unit. This allows the multitask arbitration control unit to treat the subtasks of the corresponding subtask control unit with valid subtask arbitration request signals and invalid subtask arbitration request masking signals as valid subtasks in the multitask queue. Based on the subtask priority values ​​of each valid subtask, the module selects the highest priority valid subtask from the multitask queue as the target subtask. It then generates a configuration parameter read signal for the target subtask and outputs the target subtask configuration parameter read signal and the subtask configuration parameter storage base address to the subtask configuration parameter read / write unit. This allows the subtask configuration parameter read / write unit to trigger the accelerator to process the target subtask.

8. A terminal device, characterized in that, Includes a queue manager, accelerator, and multiple task configuration interfaces; The queue manager includes: Multiple subtask control units, each of which is connected to the task configuration interface, wherein the subtask control unit is used to execute the steps of the method described in any one of claims 1 to 4; Subtask configuration parameter read / write unit, used to connect to the multitask arbitration control unit; The multi-task arbitration control unit is used to connect to the plurality of sub-task control units and the sub-task configuration parameter read / write unit, and is also used to perform the steps of the method described in any one of claims 5 to 6.

9. A chip, characterized in that, The chip is configured with multiple first pins for connecting to a task configuration interface, and second and third pins for connecting to an accelerator. Multiple subtask control units, each of which is connected to the first pin in a one-to-one correspondence, wherein the subtask control unit is used to execute the steps of the method described in any one of claims 1 to 4; The subtask configuration parameter read / write unit is used to connect to the multitask arbitration control unit and the second pin; A multi-task arbitration control unit is used to connect to the plurality of sub-task control units, the sub-task configuration parameter read / write unit, and the third pin, and is also used to perform the steps of any one of the methods described in 5 to 6.

10. A chip module, characterized in that, It includes a communication module, a power module, a storage module, and the chip as described in claim 9, wherein: The power module is used to provide power to the chip module; The storage module is used to store data and instructions; The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices.

Images