A block memory and FPGA system based on a pipelined state machine

Abstract

This invention discloses a block memory and FPGA system based on a pipelined state machine, comprising: a program counter, a workload estimator, a pipelined register set, and a block memory. During the instruction fetch phase, the program counter indicates the address of the next instruction. The instruction is fetched from the block memory according to the indicated address, stored in the pipelined register set, and the program counter is updated. During the decoding phase, the pipelined register set parses the fetched instruction into a decoded stream. Based on the workload estimator in the pipelined state machine, the load intensity in the decoded stream is predicted. Based on the predicted load intensity, the occupancy of the decoded stream is predicted. Combined with a dynamic pipeline balancing mechanism, the pipeline depth is adjusted, and control signals are generated and stored in the pipelined registers. During the execution phase, the pipelined register set performs corresponding read and write operations on the block memory according to the control signals. This invention improves the real-time performance and throughput of the block memory.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, and more specifically, to a block memory and FPGA system based on a pipelined state machine. Background Technology

[0002] In Field-Programmable Gate Array (FPGA) systems, Block RAM is a critical component for storing and quickly accessing data, especially in scenarios requiring real-time processing of multi-channel phase and amplitude changes, where its performance directly impacts the overall system efficiency. However, traditional block RAM control logic typically employs simple state machine designs, failing to fully consider the parallel processing requirements of multi-channel systems. This results in issues such as high state transition latency and low throughput, making it difficult to meet the demands of high-precision real-time playback.

[0003] In recent years, research on optimizing FPGA control logic has made some progress. For example, pipelined state machine architectures have been proposed to reduce control logic latency and improve throughput through overlapping operations; in addition, hardware description language (HDL) optimization tools are widely used to automatically generate efficient control logic. These methods provide a theoretical basis and technical support for optimizing block memory control logic, but the following shortcomings still exist: existing pipelined state machine implementations often lack dynamic adjustment mechanisms and cannot optimize performance according to actual workloads; while existing HDL optimization tools can generate efficient control logic, their performance in complex application scenarios such as real-time phase and amplitude changes still needs improvement. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention provides a block memory and FPGA system based on a pipelined state machine. By introducing a dynamic pipeline balancing mechanism, the pipeline depth is automatically adjusted according to the current load, enabling the block memory to have real-time and high throughput characteristics, thereby improving the working efficiency of the FPGA system.

[0005] To achieve the above technical objectives, the present invention adopts the following technical solution:

[0006] A block memory based on a pipelined state machine includes: a program counter, a workload estimator, a pipelined register set, and a block memory; During the instruction fetch phase, the program counter is used to indicate the address of the next instruction. The instruction is read from the block memory according to the indicated address, stored in the pipeline register set, and the program counter is updated. During the decoding phase, the pipeline register set parses the read instructions into a decode stream, predicts the load intensity in the decode stream based on the workload estimator, predicts the occupancy of the decode stream based on the predicted load intensity, adjusts the pipeline depth in combination with the dynamic pipeline balancing mechanism, generates control signals, and stores them in the pipeline register. During the execution phase, the pipeline register set performs corresponding read and write operations on the block memory according to the control signals.

[0007] Furthermore, the prediction process for the load strength in the decoded stream is as follows: i: Calculate the number of control atoms of the instruction based on the number of channels and opcode type of the instruction in the decoded stream; ii: Determine the number of complete instructions that can be parsed within the window based on the length of the instructions in the decoded stream and the window length preset by the workload estimator; iii: Predict the load intensity in the decode stream based on the number of complete instructions that can be resolved within the window and the number of control atoms per instruction.

[0008] Furthermore, the calculation process for the number of control atoms in the instruction is as follows:

[0009] in, Indicates the first The first decoded stream The number of control atoms expanded by each instruction Indicates the first The first decoded stream Number of channels per instruction Indicates the first The first decoded stream Does the instruction carry a write / read phase field? , express The corresponding number of control atoms; Indicates the first The first decoded stream Does the instruction carry a write / read range field? , express The corresponding number of control atoms; Indicates the first The first decoded stream Does this instruction require readback, verification, and CRC steps? , express The corresponding number of control atoms; Indicates the first The first decoded stream The opcode category of the instruction. Indicates and Related constant terms.

[0010] Furthermore, the calculation process for the number of complete instructions that can be parsed within the window is as follows:

[0011] in, This indicates the number of complete instructions that can be parsed within the window. Indicates the number of instructions. express index, Indicates the first The first decoded stream The length of the instruction This indicates the preset window length for the workload estimator.

[0012] Furthermore, the prediction process for the load strength in the decoded stream is as follows:

[0013] in, Indicates the first The predicted load intensity in each decoded stream, This indicates the number of complete instructions that can be parsed within the window. Indicates the first The first decoded stream The number of control atoms expanded by each instruction Indicates the length of the prediction window.

[0014] Furthermore, the process of predicting the occupancy of the decoding stream based on the predicted load intensity is as follows:

[0015] in, Indicates the first Predicted occupancy in each decoded stream Indicates the first Current occupancy in the decoded stream, Indicates the first The ability of each execution end to consume control atoms.

[0016] Furthermore, the process of adjusting the assembly line depth is as follows: i: Calculate the pipeline overflow prevention depth based on the predicted decoding stream occupancy. ,in, Indicates the first Safety margin for each decoded stream Indicates rounding up; ii: Based on the current occupancy of the decode stream and the set minimum occupancy threshold. Calculate the depth required for the pipeline to prevent starvation. ; iii: Calculate the target depth of the production line based on the depth required to prevent overflow and the depth required to prevent starvation. ,in, Indicates the minimum allowable depth of the pipeline. Indicates the maximum allowable depth of the pipeline. Represents the amplitude limiting function; iv: Adjust the pipeline depth by setting hysteresis trigger constraints, minimum hold time constraints, and safety switching barrier constraints according to the target depth of the pipeline.

[0017] Furthermore: The hysteresis triggering constraint is When this occurs, a depth update of the pipeline is triggered, wherein, Indicates the current depth of the pipeline. Indicates the hysteresis threshold; The minimum hold time constraint means that the current pipeline depth must be maintained for at least a minimum hold time before the pipeline depth can be adjusted again; The security switching barrier constraint is as follows: like This directly increases the depth of the production line; like Furthermore, the high-order segments to be clipped must be empty, and the depth of the pipeline should be shortened directly. Otherwise, the distribution rate of the decoding stream should be reduced, and the pipeline depth should be shortened only after the high-order segments have been naturally emptied.

[0018] Furthermore, it also includes: calibrating based on the error between the actual number of control atoms generated by the instruction in the decoded stream and the calculated number of control atoms for the corresponding instruction. , , and .

[0019] Furthermore, the present invention also provides an FPGA system using the aforementioned pipelined state machine-based block memory, characterized in that it includes: a reconfigurable logic unit, a DSP module, a pipelined state machine-based block memory, and an I / O interface module; The reconfigurable logic unit is used to configure the logic functions of the FPGA; The DSP module is used to process digital signals transmitted from the reconfigurable logic unit. The block memory based on the pipelined state machine is used to perform read and write operations according to the processed data signal task; The IO interface module is used to enable communication between the block memory based on the pipelined state machine and external devices.

[0020] Compared with the prior art, the present invention has the following beneficial effects: (1) The block memory based on pipelined state machine of this invention uses pipelined state machine to divide the control logic into instruction fetch operation stage, decoding operation stage and execution operation stage, and stores the results of each operation stage through pipelined register group, so as to realize seamless connection and efficient processing of each operation stage, significantly reduce latency and improve throughput. (2) The block memory based on the pipeline state machine of this invention predicts the load intensity and occupancy of the decoding stream according to the workload estimator, accurately predicts the performance requirements of the decoding stream, and adjusts the pipeline depth in combination with the dynamic pipeline balancing mechanism to avoid the bottleneck of fixed pipeline depth when resources are idle under light load or under heavy load. Through load sensing and real-time adjustment, pipeline stalls can be avoided and throughput can be improved.

[0021] Applying the block memory based on the pipelined state machine of this invention to FPGA systems can greatly improve the real-time performance and throughput of FPGA systems, thereby improving the working efficiency of FPGA systems. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the block memory based on a pipelined state machine according to the present invention; Figure 2 This is a schematic diagram of the FPGA system of the present invention. Detailed Implementation

[0023] The technical solution of the present invention will be further explained and described below with reference to the accompanying drawings.

[0024] like Figure 1 This is a schematic diagram of the block memory based on a pipelined state machine according to the present invention. The block memory includes a program counter, a workload estimator, a pipelined register set, and the block memory. The present invention uses a pipelined state machine to divide the control logic into an instruction fetch operation stage, an instruction decode operation stage, and an instruction execution operation stage, and stores the results of each operation stage through the pipelined register set, thereby achieving seamless connection and efficient processing of each operation stage, significantly reducing latency and improving throughput.

[0025] During the instruction fetch phase, the program counter is used to indicate the address of the next instruction. The instruction is then read from the block memory according to the indicated address, stored in the pipeline register set, and the program counter is updated.

[0026] During the decoding phase, the pipeline register set parses the read instructions into a decoded stream, predicts the load intensity in the decoded stream based on the workload estimator, predicts the occupancy of the decoded stream based on the predicted load intensity, accurately predicts the performance requirements of the decoded stream, and adjusts the pipeline depth in conjunction with a dynamic pipeline balancing mechanism, generating control signals and storing them in the pipeline registers. This avoids bottlenecks caused by a fixed pipeline depth when resources are idle under light load or under heavy load. Through load sensing and real-time adjustment, pipeline stalls can be avoided, and throughput can be improved.

[0027] During the execution phase, the pipelined register set performs corresponding read and write operations on the block memory according to control signals. The memory access unit interacts directly with the block memory, ensuring minimal latency for read and write operations. For read operations, the data retrieved from the block memory is stored in the pipelined register set for use in subsequent stages; for write operations, the data is directly written to the block memory.

[0028] In one technical solution of this invention, for instructions in the decoded stream, the workload estimator does not directly measure the load by the number of instructions, but instead maps each instruction to several control atoms, with each control atom representing a control action of the smallest granularity output by the channel. Therefore, the load intensity prediction process in the decoded stream of this invention is as follows: i: The workload estimator parses the instruction header or field digest of the decoded stream, extracting the instruction length, number of channels, opcode type, whether it carries a write / read amplitude field, whether it carries a write / read phase field, and whether readback, checksum, and CRC steps are required. The number of channels and opcode type are used to calculate the number of control atoms in the instruction.

[0029] in, Indicates the first The first decoded stream The number of control atoms expanded by each instruction Indicates the first The first decoded stream Number of channels per instruction Indicates the first The first decoded stream Does the instruction carry a write / read phase field? , express The corresponding number of control atoms; Indicates the first The first decoded stream Does the instruction carry a write / read range field? , express The corresponding number of control atoms; Indicates the first The first decoded stream Does this instruction require readback, verification, and CRC steps? , express The corresponding number of control atoms; Indicates the first The first decoded stream The opcode category of the instruction. Indicates and Related constant terms.

[0030] ii: Since the instructions are variable length, the number of complete instructions that can be parsed within the window needs to be determined based on the instruction length and the window length preset by the workload estimator.

[0031] in, This indicates the number of complete instructions that can be parsed within the window. Indicates the number of instructions. express index, Indicates the first The first decoded stream The length of the instruction This indicates the preset window length for the workload estimator.

[0032] iii: Predict the load intensity in the decode stream based on the number of complete instructions that can be resolved within the window and the number of control atoms per instruction:

[0033] in, Indicates the first The predicted load intensity in each decoded stream, This indicates the number of complete instructions that can be parsed within the window. Indicates the first The first decoded stream The number of control atoms expanded by each instruction Indicates the length of the prediction window.

[0034] In one technical solution of the present invention, the process of predicting the occupancy of the decoding stream based on the predicted load intensity is as follows:

[0035] in, Indicates the first Predicted occupancy in each decoded stream Indicates the first Current occupancy in the decoded stream, Indicates the first The ability of each execution end to consume control atoms.

[0036] In one technical solution of the present invention, the process of adjusting the production line depth is as follows: i: Calculate the pipeline overflow prevention depth based on the predicted decoding stream occupancy. ,in, Indicates the first Safety margin for each decoded stream Indicates rounding up; ii: Based on the current occupancy of the decode stream and the set minimum occupancy threshold. Calculate the depth required for the pipeline to prevent starvation. ; iii: Calculate the target depth of the pipeline based on the depth required to prevent overflow and the depth required to prevent starvation. ,in, Indicates the minimum allowable depth of the pipeline. Indicates the maximum allowable depth of the pipeline. Represents the amplitude limiting function; iv: To avoid jitter or data loss caused by dynamically adjusting the pipeline depth, the pipeline depth is adjusted based on the target pipeline depth using hysteresis trigger constraints, minimum hold time constraints, and safe switching barrier constraints. This maintains high pipeline throughput under real high loads while avoiding performance fluctuations caused by ineffective adjustments. Specifically: Hysteresis triggering constraint is At that time, a deep update of the pipeline is triggered to avoid frequent switching jitter caused by load fluctuations and reduce overhead. Indicates the current depth of the pipeline. Indicates the hysteresis threshold; The minimum hold time constraint requires that the current pipeline depth must be held for at least a minimum hold time before the pipeline depth can be adjusted again, in order to avoid data corruption or performance degradation due to excessively rapid adjustments. The safety handover barrier constraints are: like This directly increases the depth of the production line; like Furthermore, the high-order bits to be clipped must be empty, and the pipeline depth must be shortened directly. Otherwise, the distribution rate of the decoding stream should be reduced, and the pipeline depth should be shortened only after the high-order bits have been naturally emptied, to ensure data consistency and functional correctness during the pipeline depth adjustment process.

[0037] In one technical solution of the present invention, the method further includes: calibrating based on the error between the actual number of control atoms generated by the instruction in the decoded stream and the calculated number of control atoms of the corresponding instruction. , , and This enables feedback self-calibration to ensure engineering consistency. The calibration process for each parameter is as follows:

[0038] in, express , , and One of them, Indicates the first The error between the actual number of control atoms generated by an instruction in a decoded stream and the calculated number of control atoms for the corresponding instruction. Indicates and The corresponding triggering features, Represents the saturation function. This represents the learning rate shift factor. This indicates an arithmetic right shift.

[0039] like Figure 2 In one technical solution of the present invention, an FPGA system using a block memory based on a pipelined state machine is also provided, including: a reconfigurable logic unit, a DSP module, a block memory based on a pipelined state machine, and an IO interface module. Reconfigurable logic units are used to configure the logic functions of the FPGA; The DSP module is used to process digital signals transmitted from the reconfigurable logic unit. Block memory based on pipelined state machines is used to perform read and write operations according to the data signal task being processed; The IO interface module is used to enable communication between the block memory based on the pipelined state machine and external devices.

[0040] Applying the block memory based on the pipelined state machine of this invention to FPGA systems can greatly improve the real-time performance and throughput of FPGA systems, thereby improving the working efficiency of FPGA systems.

[0041] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A block memory based on a pipelined state machine, characterized in that, include: Program counter, workload estimator, pipelined register set, and block memory; During the instruction fetch phase, the program counter is used to indicate the address of the next instruction. The instruction is read from the block memory according to the indicated address, stored in the pipeline register set, and the program counter is updated. During the decoding phase, the pipeline register set parses the read instructions into a decode stream, predicts the load intensity in the decode stream based on the workload estimator, predicts the occupancy of the decode stream based on the predicted load intensity, adjusts the pipeline depth in combination with the dynamic pipeline balancing mechanism, generates control signals, and stores them in the pipeline register. During the execution phase, the pipeline register set performs corresponding read and write operations on the block memory according to the control signals.

2. The block memory based on a pipelined state machine according to claim 1, characterized in that, The process of predicting the load strength in the decoded stream is as follows: i: Calculate the number of control atoms of the instruction based on the number of channels and opcode type of the instruction in the decoded stream; ii: Determine the number of complete instructions that can be parsed within the window based on the length of the instructions in the decoded stream and the window length preset by the workload estimator; iii: Predict the load intensity in the decode stream based on the number of complete instructions that can be resolved within the window and the number of control atoms per instruction.

3. A block memory based on a pipelined state machine according to claim 2, characterized in that, The calculation process for the number of control atoms in the instruction is as follows: in, Indicates the first The first decoded stream The number of control atoms expanded by each instruction Indicates the first The first decoded stream Number of channels per instruction Indicates the first The first decoded stream Does the instruction carry a write / read phase field? , express The corresponding number of control atoms; Indicates the first The first decoded stream Does the instruction carry a write / read range field? , express The corresponding number of control atoms; Indicates the first The first decoded stream Does this instruction require readback, verification, and CRC steps? , express The corresponding number of control atoms; Indicates the first The first decoded stream The opcode category of the instruction. Indicates and Related constant terms.

4. A block memory based on a pipelined state machine according to claim 2, characterized in that, The calculation process for the number of complete instructions that can be parsed within the window is as follows: in, This indicates the number of complete instructions that can be parsed within the window. Indicates the number of instructions. express index, Indicates the first The first decoded stream The length of the instruction This indicates the preset window length for the workload estimator.

5. A block memory based on a pipelined state machine according to claim 2, characterized in that, The process of predicting the load strength in the decoded stream is as follows: in, Indicates the first The predicted load intensity in each decoded stream, This indicates the number of complete instructions that can be parsed within the window. Indicates the first The first decoded stream The number of control atoms expanded by each instruction Indicates the length of the prediction window.

6. A block memory based on a pipelined state machine according to claim 5, characterized in that, The process of predicting the occupancy of the decoding stream based on the predicted load intensity is as follows: in, Indicates the first Predicted occupancy in each decoded stream Indicates the first Current occupancy in the decoded stream, Indicates the first The ability of each execution end to consume control atoms.

7. A block memory based on a pipelined state machine according to claim 6, characterized in that, The process for adjusting the pipeline depth is as follows: i: Calculate the pipeline overflow prevention depth based on the predicted decoding stream occupancy. ,in, Indicates the first Safety margin for each decoded stream Indicates rounding up; ii: Based on the current occupancy of the decode stream and the set minimum occupancy threshold. Calculate the depth required for the pipeline to prevent starvation. ; iii: Calculate the target depth of the production line based on the depth required to prevent overflow and the depth required to prevent starvation. ,in, Indicates the minimum allowable depth of the pipeline. Indicates the maximum allowable depth of the pipeline. Represents the amplitude limiting function; iv: Adjust the pipeline depth by setting hysteresis trigger constraints, minimum hold time constraints, and safety switching barrier constraints according to the target depth of the pipeline.

8. A block memory based on a pipelined state machine according to claim 7, characterized in that: The hysteresis triggering constraint is When this occurs, a depth update of the pipeline is triggered, wherein, Indicates the current depth of the pipeline. Indicates the hysteresis threshold; The minimum hold time constraint means that the current pipeline depth must be maintained for at least a minimum hold time before the pipeline depth can be adjusted again; The security switching barrier constraint is as follows: like This directly increases the depth of the production line; like Furthermore, the high-order segments to be clipped must be empty, and the depth of the pipeline should be shortened directly. Otherwise, the distribution rate of the decoding stream should be reduced, and the pipeline depth should be shortened only after the high-order segments have been naturally emptied.

9. A block memory based on a pipelined state machine according to claim 3, characterized in that, Also includes: Based on the error between the actual number of control atoms generated by the instructions in the decoded stream and the calculated number of control atoms for the corresponding instructions, calibration is performed. , , and .

10. An FPGA system employing the block memory based on a pipelined state machine as described in any one of claims 1-9, characterized in that, include: Reconfigurable logic units, DSP modules, pipelined state machine-based block memory, and I / O interface modules; The reconfigurable logic unit is used to configure the logic functions of the FPGA; The DSP module is used to process digital signals transmitted from the reconfigurable logic unit. The block memory based on the pipelined state machine is used to perform read and write operations according to the processed data signal task; The IO interface module is used to enable communication between the block memory based on the pipelined state machine and external devices.

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