Multilayer ceramic capacitors and their manufacturing methods

Abstract

This disclosure provides a multilayer ceramic capacitor and a method for manufacturing the same. The multilayer ceramic capacitor includes: a capacitor body comprising a dielectric layer and an inner electrode layer; and an outer electrode disposed on the outer surface of the capacitor body. The dielectric layer comprises a plurality of dielectric grains, at least one of which has a core-shell structure. The core-shell structure includes a core and a shell surrounding at least a portion of the core. The core comprises barium (Ba) and titanium (Ti), and the shell comprises zirconium (Zr) and calcium (Ca) and / or strontium (Sr).

Description

Technical Field

[0001] This disclosure relates to a multilayer ceramic capacitor and a method for manufacturing the same. Background Technology

[0002] Electronic components that use ceramic materials include capacitors, inductors, piezoelectric elements, varistors, and thermistors. Among these ceramic-based electronic components, multilayer ceramic capacitors (MLCCs) are used in various electronic devices due to their advantages such as small size, high capacitance, and ease of installation.

[0003] For example, a multilayer ceramic capacitor (MLCC) can be a chip capacitor mounted on a printed circuit board of various electronic products, such as imaging devices (e.g., liquid crystal displays (LCDs), plasma display panels (PDPs), organic light-emitting diodes (OLEDs), etc.), computers, personal portable terminals, smartphones, etc.) for charging or discharging from them.

[0004] To ensure high functionality and stability in electrical and information technology (IT) industrial installations, the demand for miniaturized, high-capacitance, and high-guarantee voltage multilayer ceramic capacitors is expected to continue to increase. Summary of the Invention

[0005] This disclosure provides a high-voltage multilayer ceramic capacitor with excellent temperature characteristics, withstand voltage characteristics, and DC bias characteristics.

[0006] Some embodiments of this disclosure provide a method for manufacturing a multilayer ceramic capacitor.

[0007] Embodiments of this disclosure provide a multilayer ceramic capacitor, the multilayer ceramic capacitor comprising: a capacitor body including a dielectric layer and an inner electrode layer; and an outer electrode disposed on the outer surface of the capacitor body, wherein the dielectric layer includes a plurality of dielectric grains, at least one of the plurality of dielectric grains having a core-shell structure, the core-shell structure including a core and a shell surrounding at least a portion of the core, the core including barium (Ba) and titanium (Ti), the shell including zirconium (Zr) and calcium (Ca) and / or strontium (Sr), and in TEM-EDS (transmission electron microscopy-energy dispersive spectroscopy) line analysis of a long axis straight segment passing through the center of the dielectric grain having the core-shell structure, the core is a region based on 100 moles of titanium (Ti) with a zirconium (Zr) content of less than about 3 moles, and the shell is a region based on 100 moles of titanium (Ti) with a zirconium (Zr) content of greater than or equal to about 3 moles.

[0008] The shell portion, based on 100 moles of titanium (Ti), may include a total of about 2.5 moles to about 40 moles of calcium (Ca) and / or strontium (Sr).

[0009] The shell portion, based on 100 moles of titanium (Ti), may include approximately 3 moles to approximately 150 moles of zirconium (Zr).

[0010] The shell portion, based on 100 moles of titanium (Ti), may include about 2.5 moles to about 40 moles of calcium (Ca), and the shell portion, based on 100 moles of titanium (Ti), may include about 3 moles to about 150 moles of zirconium (Zr).

[0011] The shell portion, based on 100 moles of titanium (Ti), may include about 2.5 moles to about 40 moles of strontium (Sr), and the shell portion, based on 100 moles of titanium (Ti), may include about 3 moles to about 150 moles of zirconium (Zr).

[0012] The shell may also include rare earth elements.

[0013] The rare earth elements may include elements with ionic radii larger than that of yttrium (Y).

[0014] The rare earth element may include at least one selected from the group consisting of dysprosium (Dy), gadolinium (Gd), lanthanum (La) and cerium (Ce).

[0015] The shell portion, based on 100 moles of titanium (Ti), may include approximately 0.5 moles to approximately 10 moles of the rare earth element.

[0016] The shell may also include a transition metal.

[0017] The transition metal may include at least one selected from the group consisting of manganese (Mn), vanadium (V) and chromium (Cr).

[0018] The shell may also include rare earth elements and transition metals.

[0019] The rare earth element includes at least one selected from the group consisting of dysprosium (Dy), gadolinium (Gd), lanthanum (La) and cerium (Ce), and the transition metal includes at least one selected from the group consisting of manganese (Mn), vanadium (V) and chromium (Cr).

[0020] The dielectric layer may further include grain boundaries disposed between the plurality of dielectric grains, and the grain boundaries may include silicon (Si).

[0021] The grain boundary, based on 100 moles of titanium (Ti), may include about 2.5 moles to about 20 moles of silicon (Si).

[0022] The grain boundaries may also include rare earth elements.

[0023] The rare earth element may include at least one selected from the group consisting of dysprosium (Dy), gadolinium (Gd), lanthanum (La) and cerium (Ce).

[0024] The grain boundary, based on 100 moles of titanium (Ti), may include approximately 3 moles to approximately 30 moles of the rare earth element.

[0025] The diameter of the core portion of the at least one dielectric grain can be from about 15% to about 85% of the diameter of the at least one dielectric grain.

[0026] The number of dielectric grains having the core-shell structure can be from about 5% to about 100% of the total number of dielectric grains present in the dielectric layer.

[0027] Another embodiment provides a method for manufacturing a multilayer ceramic capacitor, the method comprising: preparing a dielectric paste comprising a main component powder, the main component powder comprising a barium titanate-based compound and a zirconium-based compound; manufacturing a dielectric green sheet from the dielectric paste and forming a conductive paste layer on the surface of the dielectric green sheet; manufacturing a dielectric green sheet stack by stacking a plurality of the dielectric green sheets on which the conductive paste layer is formed; manufacturing a capacitor body comprising a dielectric layer and an inner electrode layer by firing the dielectric green sheet stack; and forming an outer electrode on the outer surface of the capacitor body, wherein the zirconium-based compound comprises at least one selected from the group consisting of compounds comprising Zr and Ca and compounds comprising Zr and Sr, the dielectric layer comprises a plurality of dielectric grains, at least one of the plurality of dielectric grains having a core-shell structure, the core-shell structure comprising a core and a shell surrounding at least a portion of the core, the core comprising barium (Ba) and titanium (Ti), and the shell comprising zirconium (Zr) and calcium (Ca) and / or strontium (Sr).

[0028] The main component powder may include a mixture of the barium titanate-based compound and the zirconium-based compound, or may include a composite of the zirconium-based compound coated on the surface of the barium titanate-based compound.

[0029] The zirconium-based compound may include at least one selected from CaZrO3 and SrZrO3.

[0030] The dielectric paste may further include secondary component powders, which include at least one selected from the group consisting of silicon (Si) compounds, rare earth element compounds, and transition metal compounds.

[0031] The rare earth element-containing compound may include at least one selected from the group consisting of dysprosium (Dy)-containing compounds, gadolinium (Gd)-containing compounds, lanthanum (La)-containing compounds, and cerium (Ce)-containing compounds.

[0032] The transition metal compound may include at least one selected from the group consisting of manganese (Mn) compounds, vanadium (V) compounds, and chromium (Cr) compounds.

[0033] The byproduct powder may include at least one selected from the group consisting of the silicon (Si)-containing compound, the rare earth element-containing compound, and the transition metal-containing compound. In some embodiments, the byproduct powder may include the silicon (Si)-containing compound, the rare earth element-containing compound, and the transition metal-containing compound.

[0034] Based on the total amount of the barium titanate-based compound and the zirconium-based compound, the zirconium-based compound may be included in an amount of about 1 mol% to about 20 mol%.

[0035] The multilayer ceramic capacitor according to the embodiment not only has high capacitance and high voltage characteristics, but also excellent temperature characteristics, withstand voltage characteristics and DC bias characteristics. Attached Figure Description

[0036] Figure 1 This is a perspective view showing a multilayer ceramic capacitor according to an embodiment.

[0037] Figure 2 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken by line I-I'.

[0038] Figure 3 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken from line II-II'.

[0039] Figure 4 It is shown Figure 1 An exploded perspective view of the stacked structure of the capacitor body.

[0040] Figure 5 This is a schematic diagram showing the dielectric layer according to an embodiment.

[0041] Figures 6A to 6G It is based on the TEM-EDS (transmission electron microscopy-energy dispersive spectroscopy) surface scan analysis image of the dielectric layer in Example 3.

[0042] Figure 7A and Figure 7B The image is based on the TEM-EDS (transmission electron microscopy-energy dispersive spectroscopy) line analysis image of the dielectric layer in Example 3.

[0043] Figure 8 This is a graph showing the temperature coefficient of capacitance (TCC) of the multilayer ceramic capacitors according to Examples 1 to 4 and Comparative Example 1.

[0044] Figure 9 This is a graph showing the step insulation resistance (STEP-IR) characteristics of the multilayer ceramic capacitors according to Examples 2 to 5 and Comparative Example 1.

[0045] Figure 10 The graph shows the DC bias characteristics of the multilayer ceramic capacitors according to Examples 1 to 5 and Comparative Example 1. Detailed Implementation

[0046] The present disclosure will now be described in detail with reference to the accompanying drawings, in which embodiments of the disclosure are illustrated. The drawings and description are to be considered illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals denote the same elements. In the drawings, some components are exaggerated, omitted, or shown schematically, and the dimensions of each component do not perfectly reflect actual dimensions.

[0047] The accompanying drawings are intended only to facilitate understanding of the embodiments disclosed in this specification, and it will be understood that the technical concepts disclosed herein are not limited to the drawings, and all variations, equivalents or alternatives within the scope of the technical concepts of this disclosure are included within the scope of this disclosure.

[0048] Although terms such as "first," "second," etc., are used to describe various components, the component is not limited by these terms. These terms are only used to distinguish one component from another.

[0049] Furthermore, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be an intermediate element present. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element present. Additionally, when an element is referred to as being "on" or "above" a reference element, it may be located "above" or "below" the reference element, and does not necessarily mean that it is located "on" or "above" the reference element in a direction opposite to the direction of gravity.

[0050] Throughout this specification, the terms “comprising” or “having” are intended to specify the presence of the stated features, quantities, steps, operations, constituent elements, components, or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, constituent elements, components, or combinations thereof. Therefore, unless explicitly stated otherwise, the words “comprising” and variations such as “including” or “having” will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0051] Furthermore, throughout the specification, the phrase "in plan view" or "on a plane" indicates the target portion as viewed from the top, and the phrase "in section view" or "on a section" indicates the section formed by vertically cutting the target portion as viewed from the side.

[0052] Throughout this specification, the term "connection" may mean not only a direct connection between two or more constituent elements, but also an indirect connection between two or more constituent elements through another constituent element, an electrical and / or physical connection between two or more constituent elements, or two or more constituent elements that are represented by different names according to their location or function but are integral.

[0053] In the following text, reference will be made to Figures 1 to 4 A multilayer ceramic capacitor according to an embodiment is described.

[0054] Figure 1 This is a perspective view showing a multilayer ceramic capacitor according to an embodiment. Figure 2 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken by line I-I'. Figure 3 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken from line II-II', and Figure 4 It is shown Figure 1 An exploded perspective view of the stacked structure of the capacitor body.

[0055] Figures 1 to 4 The L-axis, W-axis, and T-axis directions shown represent the length, width, and thickness directions of the capacitor body 110, respectively. Here, the thickness direction (T-axis) can be perpendicular to the wide surface (main surface) of the sheet assembly; for example, it can be used as the same concept as the stacking direction along which the stacked dielectric layers 111 are aligned. The length direction (L-axis) can be parallel to the wide surface (main surface) of the sheet assembly and can be approximately perpendicular to the thickness direction (T-axis). For example, the length direction (L-axis) can be the direction along which the first external electrode 131 and the second external electrode 132 are positioned relative to each other. The width direction (W-axis) can be parallel to the wide surface (main surface) of the sheet assembly and can be approximately perpendicular to both the thickness direction (T-axis) and the length direction (L-axis). The length of the sheet assembly in the length direction (L-axis) can be longer than its width in the width direction (W-axis).

[0056] Reference Figures 1 to 4According to some embodiments, a multilayer ceramic capacitor 100 includes a capacitor body 110 and external electrodes 131 and 132 disposed on the outer surface of the capacitor body 110. The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132 disposed at opposite ends of the capacitor body 110 in the longitudinal direction (L-axis direction).

[0057] For example, the capacitor body 110 may have a generally hexahedral shape.

[0058] For ease of description of this embodiment, the two surfaces of the capacitor body 110 that are opposite to each other in the thickness direction (T-axis direction) are referred to as the first surface and the second surface, the two surfaces of the capacitor body 110 that are connected to the first surface and the second surface and are opposite to each other in the length direction (L-axis direction) are referred to as the third surface and the fourth surface, and the two surfaces of the capacitor body 110 that are connected to the first surface and the second surface and connected to the third surface and the fourth surface and are opposite to each other in the width direction (W-axis direction) are referred to as the fifth surface and the sixth surface.

[0059] As an example, the first surface, which serves as the lower surface, can be a mounting surface. Alternatively, the first to sixth surfaces can be flat, but this embodiment is not limited to this. For example, the first to sixth surfaces can be curved surfaces with a convex central portion, and the edges of each surface (the boundaries between the surfaces) can be rounded.

[0060] The shape and size of the capacitor body 110 and the number of stacked dielectric layers 111 are not limited to the shape and size of the capacitor body 110 and the number of stacked dielectric layers 111 shown in the accompanying drawings of the embodiment.

[0061] The capacitor body 110 includes a plurality of dielectric layers 111 and a plurality of internal electrode layers 121 and 122. Specifically, the capacitor body 110 includes a plurality of dielectric layers 111 and a first internal electrode layer 121 and a second internal electrode layer 122, the first internal electrode layer 121 and the second internal electrode layer 122 are alternately arranged in the thickness direction (T-axis direction), and the dielectric layer 111 is located between the first internal electrode layer 121 and the second internal electrode layer 122.

[0062] At this point, the adjacent dielectric layers 111 of the capacitor body 110 can be integrated to such an extent that the boundaries between them are difficult to identify without using a scanning electron microscope (SEM).

[0063] The capacitor body 110 may include an effective area and coverage areas 112 and 113.

[0064] The effective region is the area where dielectric layer 111 and inner electrode layers 121 and 122 are alternately stacked in the thickness direction (T-axis direction), which contributes to the capacitance of the multilayer capacitor 100. Specifically, the effective region may be the area where the first inner electrode layer 121 and the second inner electrode layer 122 are stacked along the thickness direction (T-axis direction).

[0065] Cover regions 112 and 113 are thickness-direction edges and may be located on the upper and lower surfaces of the effective region in the thickness direction (T-axis direction), respectively. Cover regions 112 and 113 may be a single dielectric layer or two or more dielectric layers stacked on the upper and lower surfaces of the effective region, respectively.

[0066] In addition, the capacitor body 110 may also include a side edge region.

[0067] The side edge region is the edge portion in the width direction. The side edge regions can be located on the side surfaces of the effective region that are opposite to each other in the width direction (W-axis direction) (i.e., on the surfaces corresponding to the fifth and sixth surfaces). The side edge regions can be formed as follows: when a conductive paste for the inner electrode layer is coated on the surface of the dielectric green sheet, the conductive paste is only coated on a portion of the surface of the dielectric green sheet, and not on both sides of the surface of the dielectric green sheet in the width direction. Then the obtained dielectric green sheets are stacked and fired, but the formation method is not limited to this.

[0068] Coverage areas 112 and 113, as well as side edge areas, can be used to prevent damage to the first inner electrode layer 121 and the second inner electrode layer 122 due to physical stress and / or chemical stress.

[0069] dielectric layer Reference Figure 5 Describes dielectric layer 111 according to some embodiments.

[0070] Figure 5 This is a schematic diagram illustrating a dielectric layer according to some embodiments of the present disclosure.

[0071] Reference Figure 5 The dielectric layer 111 includes a plurality of dielectric grains 10. In addition, the dielectric layer 111 may also include grain boundaries 20 disposed between the plurality of dielectric grains 10.

[0072] At least one of the plurality of dielectric grains 10 may have a core-shell structure, the core-shell structure including a core 12 and a shell 14 surrounding at least a portion of the core 12.

[0073] The core 12 may include barium (Ba) and titanium (Ti), and the shell 14 may include zirconium (Zr) and calcium (Ca) and / or strontium (Sr).

[0074] The Ba and Ti in the core 12 may be derived from barium titanate-based compounds used as dielectric matrix materials. Barium titanate-based compounds may be ferroelectric materials with high dielectric constants and stable temperature characteristics. For example, barium titanate-based compounds may include one or more selected from the group consisting of BaTiO3, Ba(Ti, Sn)O3, (Ba, Ca)TiO3, and (Ba, Sr)TiO3.

[0075] The Zr, Ca, and / or Sr in the shell 14 may be derived from a zirconium-based compound used as a dielectric matrix material. The zirconium-based compound may be a paraelectric material with high withstand voltage characteristics and excellent resistance to electrical distortion. For example, the zirconium-based compound may include one or more selected from the group consisting of CaZrO3, SrZrO3, (Ba, Ca)ZrO3, and (Ba, Sr)ZrO3, for instance, it may include one or both selected from CaZrO3 and SrZrO3.

[0076] According to some embodiments, by mixing a barium titanate-based compound as a dielectric matrix material with a zirconium-based compound as a dielectric matrix material, the multilayer ceramic capacitor satisfies the X7R-level temperature characteristics in the medium dielectric constant range of 1500 to 2000 due to the material properties of the core portion 12, and the multilayer ceramic capacitor can achieve excellent reduction resistance, reliability and withstand voltage characteristics due to the material properties of the shell portion 14.

[0077] In addition, the Ca and / or Sr included in the shell 14 can prevent the degradation of temperature characteristics by minimizing the shift of the Curie temperature (Tc) to a lower temperature due to Zr.

[0078] Barium titanate-based compounds, as ferroelectric materials, exhibit both electrical distortion and piezoelectric properties. Therefore, when a high electric field is applied, stress and structural deformation may occur, potentially leading to physical and mechanical defects within the chip. Consequently, high-voltage products are being developed using design methods that minimize the applied high voltage, such as shielding stacking and voltage division. However, these methods make it difficult to ensure capacitance in multilayer ceramic capacitors while maintaining the same dielectric constant, particularly causing a reduction in DC bias characteristics, which lowers product competitiveness. Another strategy is to minimize design methods that reduce the applied voltage (such as shielding stacking and voltage division) by increasing the material's withstand voltage, thereby ensuring capacitance and improving DC bias characteristics. However, these methods suffer from deterioration in temperature characteristics and low dielectric constants, limiting the development of models that simultaneously meet high capacitance and high voltage requirements.

[0079] According to some embodiments, when the dielectric layer 111 has dielectric grains 10, the dielectric grains 10 include Ba and Ti derived from ferroelectric materials in the core portion 12 and Zr and Ca and / or Sr derived from paraelectric materials in the case portion 14, the degradation of temperature characteristics can be minimized. Simultaneously, the design method for reducing boost voltage can be minimized by the case portion 14 having a high withstand voltage. That is, since the temperature characteristics meet the X7R level and the withstand voltage is increased simultaneously, design factors (such as voltage divider designs) that hinder capacitance and DC bias characteristics can be minimized. Furthermore, excellent reliability and resistance to reduction can be achieved by the case portion 14 having a high withstand voltage, thus enabling the multilayer ceramic capacitor to be used in high-voltage models requiring a voltage guarantee greater than or equal to 250V. Additionally, technological competitiveness can be improved by minimizing the temperature drop that accompanies the improvement in withstand voltage characteristics. Therefore, a multilayer ceramic capacitor that not only has high capacitance and high voltage characteristics but also excellent temperature characteristics, withstand voltage characteristics, and DC bias characteristics can be obtained.

[0080] In the dielectric grain 10 with a core-shell structure, in TEM-EDS (transmission electron microscopy-energy dispersive spectroscopy) line analysis of the long axis straight segment passing through the center of the dielectric grain 10 with a core-shell structure, the core 12 can be a region based on 100 moles of titanium (Ti) with a zirconium (Zr) content of less than about 3 moles, and the shell 14 can be a region based on 100 moles of titanium (Ti) with a zirconium (Zr) content of greater than or equal to about 3 moles. For example, the Zr content in the core 12, based on 100 molar parts of Ti, can be greater than about 0 molar parts, about 0.5 molar parts, about 1 molar parts, about 1.5 molar parts, about 2 molar parts, or about 2.5 molar parts and less than about 3 molar parts, about 2.5 molar parts, about 2 molar parts, about 1.5 molar parts, about 1 molar parts, or about 0.5 molar parts, and the Zr content in the shell 14, based on 100 molar parts of Ti, can be greater than or equal to about 3 molar parts, about 4 molar parts, about 5 molar parts, about 6 molar parts, about 7 molar parts, about 8 molar parts, about 9 molar parts, about 10 molar parts, about 50 molar parts, about 100 molar parts, or about 200 molar parts and less than about 300 molar parts, about 200 molar parts, about 100 molar parts, about 50 molar parts, about 10 molar parts, about 9 molar parts, about 8 molar parts, about 7 molar parts, about 6 molar parts, about 5 molar parts, or about 4 molar parts.

[0081] The shell portion 14 may include Ca and Zr, or may include Sr and Zr, or may include Ca, Sr and Zr.

[0082] Based on 100 moles of Ti, the total content of Ca and / or Sr in the case 14 can be from about 2.5 moles to about 40 moles, for example, from about 2.8 moles to about 35 moles or from about 3.0 moles to about 30 moles based on 100 moles of Ti. When the total content of Ca and / or Sr in the case 14 is within the above range, the degradation of temperature characteristics can be minimized and the design method for reducing boost voltage can be reduced. Therefore, a multilayer ceramic capacitor that not only has high capacitance and high voltage characteristics but also excellent temperature characteristics, withstand voltage characteristics, and DC bias characteristics can be obtained.

[0083] Furthermore, based on 100 moles of Ti, the Zr content in the case 14 can be from about 3 moles to about 150 moles. For example, based on 100 moles of Ti, the Zr content in the case 14 can be from about 5 moles to about 140 moles, from about 7 moles to about 130 moles, or from about 10 moles to about 120 moles. When the Zr content in the case 14 is within the above range, the degradation of temperature characteristics can be minimized and the design method for reducing boost voltage can be minimized, thereby ensuring that the multilayer ceramic capacitor not only has high capacitance and high voltage characteristics but also excellent temperature characteristics, withstand voltage characteristics, and DC bias characteristics.

[0084] According to some embodiments, the shell portion 14 may also include rare earth elements.

[0085] Rare earth elements may include elements with ionic radii larger than that of yttrium (Y). For example, rare earth elements may include one or more selected from the group consisting of dysprosium (Dy), gadolinium (Gd), lanthanum (La), and cerium (Ce). Elements with ionic radii larger than that of Y tend to substitute at A sites in dielectric matrix materials represented by the chemical formula ABO3. In some embodiments, the dielectric grains or shells may not include holmium (Ho).

[0086] The rare earth elements included in the shell 14 may be derived from rare earth element compounds added to the dielectric matrix material as additives during the formation of the dielectric layer.

[0087] When the shell 14 includes rare earth elements in addition to Zr, Ca and / or Sr, the withstand voltage characteristics (i.e., reliability) can be improved by substituting the A sites of the rare earth elements to induce n-type semiconductor characteristics and suppressing oxygen vacancies.

[0088] Based on 100 moles of Ti, the total content of rare earth elements in the shell 14 can be from about 0.5 moles to about 10 moles. For example, based on 100 moles of Ti, the total content of rare earth elements in the shell 14 can be from about 0.7 moles to about 9 moles, or from about 1 mole to about 7 moles. When the total content of rare earth elements in the shell 14 is within the above range, a multilayer ceramic capacitor with high capacitance and high voltage characteristics, as well as excellent temperature characteristics, withstand voltage characteristics, and DC bias characteristics can be obtained. When the total content of rare earth elements in the shell 14 based on 100 moles of Ti is less than about 0.5 moles, the withstand voltage characteristics may deteriorate, making it difficult for the multilayer ceramic capacitor to be used at high voltages. Furthermore, when the total content of rare earth elements in the shell 14 based on 100 moles of Ti exceeds about 10 moles, the temperature characteristics may deteriorate.

[0089] According to some embodiments, the housing 14 may also include a transition metal.

[0090] For example, transition metals may include one or more selected from the group consisting of manganese (Mn), vanadium (V), and chromium (Cr).

[0091] The transition metal included in the shell 14 may be derived from a transition metal-containing compound that is added to the dielectric substrate material as an additive when forming the dielectric layer.

[0092] When the case 14 includes a transition metal in addition to Zr, Ca and / or Sr, the multilayer ceramic capacitor can have excellent temperature characteristics and high capacitance and high voltage characteristics.

[0093] For example, shell 14 may include Ca and / or Sr, Zr, rare earth elements and transition metals.

[0094] The grain boundaries 20 disposed between the plurality of dielectric grains 10 may include silicon (Si).

[0095] Silicon (Si) can be derived from silicon-containing compounds added to dielectric matrix materials as additives.

[0096] When the grain boundary 20 includes Si, the reliability of the multilayer ceramic capacitor can be improved due to the increased grain boundary resistance.

[0097] Based on 100 mol parts of Ti, the Si content in grain boundary 20 can be from about 2.5 mol parts to about 20 mol parts. For example, based on 100 mol parts of Ti, the Si content in grain boundary 20 can be from about 2.8 mol parts to about 19 mol parts, from about 3.0 mol parts to about 18 mol parts, or from about 3.5 mol parts to about 17 mol parts. When the Si content in grain boundary 20 is within the above range, the reliability of the multilayer ceramic capacitor can be improved.

[0098] When TEM-EDS (transmission electron microscopy-energy dispersive spectroscopy) line analysis is performed within the dielectric layer 111 along a straight line segment passing through the long axis of the dielectric grain 10 with a core-shell structure, the grain boundary 20 can be a region based on 100 moles of Ti and Si with a content of about 2.5 moles to about 20 moles.

[0099] In addition to Si, grain boundaries 20 may also include rare earth elements.

[0100] The rare earth elements included in the grain boundary 20 may be derived from rare earth element compounds added to the dielectric matrix material as additives during the formation of the dielectric layer. That is, the rare earth elements included in the grain boundary 20 may be the same as those included in the shell portion 14.

[0101] Specifically, rare earth elements may include elements with ionic radii larger than that of yttrium (Y), such as one or more selected from the group consisting of Dy, Gd, La and Ce.

[0102] When rare earth elements are included in addition to Si in the grain boundary 20, the insulation effect can be further enhanced.

[0103] Based on 100 moles of Ti, the total content of rare earth elements in grain boundary 20 can be from about 3 moles to about 30 moles. For example, based on 100 moles of Ti, the total content of rare earth elements in grain boundary 20 can be from about 4 moles to about 29 moles, from about 5 moles to about 28 moles, or from about 6 moles to about 27 moles. When the total content of rare earth elements in grain boundary 20 is within the above range, the multilayer ceramic capacitor can exhibit excellent temperature characteristics as well as high capacitance and high voltage characteristics.

[0104] The structure, composition, and structure of the aforementioned dielectric layer 111 can be confirmed by TEM-EDS (transmission electron microscopy-energy dispersive spectroscopy). TEM-EDS can be performed using the following methods.

[0105] After the multilayer ceramic capacitor 100 is immersed in an epoxy mixture and cured, the L-axis and T-axis surfaces (LT surfaces) of the capacitor body 110 are polished to half the length of the capacitor body 110 in the W-axis direction to obtain a cross-sectional sample, allowing observation of the effective region where dielectric layers 111 and inner electrode layers 121 and 122 are alternately stacked. Next, when the effective region of the cross-sectional sample is divided into three regions (upper region, central region, and lower region), TEM (transmission electron microscopy) measurements are performed so that at least one dielectric layer 111 and at least one inner electrode layer 121 or 122 are visible in each region. TEM measurements can be performed using Xe-FIB (focused ion beam) at an accelerating voltage of 200 kV and a magnification of 50,000x.

[0106] Next, EDS (energy-dispersive spectroscopy) surface scan analysis was performed on the dielectric layer in the TEM image of the measured cross-sectional sample. The EDS surface scan analysis confirmed the structure and composition of the grain boundaries 20 and the core-shell structured dielectric grains 10. Specifically, it was confirmed that Ba and Ti are present in the core 12 of the dielectric grains 10, and Zr, as well as Ca and / or Sr, are present in the shell 14 of the dielectric grains 10. Furthermore, it was confirmed that Si is present at the grain boundaries 20.

[0107] Furthermore, by performing EDS (energy-dispersive spectroscopy) line analysis on the dielectric layer in the measured TEM image of the cross-sectional sample, the compositional content within the grain boundary 20 and the core-shell structured dielectric grains 10 can be confirmed. That is, the content of Ca and / or Sr, Zr, etc. in the aforementioned shell 14 and the content of Si, etc. in the grain boundary 20 can be confirmed.

[0108] Specifically, in each TEM image of the upper, central, and lower regions, at least one dielectric layer 111 is arbitrarily selected for each region. Then, at least one grain boundary 20 and at least one dielectric grain 10 with a core-shell structure can be selected within the selected dielectric layer 111. EDS line analysis can be performed on the straight line segment passing through the center of the selected dielectric grain with a core-shell structure. For example, by randomly selecting one dielectric layer for each region and five grain boundaries and five dielectric grains with core-shell structures for each dielectric layer, EDS line analysis can be performed for each of a total of 15 dielectric grains and 15 grain boundaries. That is, the content of Ca and / or Sr, Zr, etc. in the shell 14 and the content of Si, etc. in the grain boundary 20 can be the average of the contents obtained from the total of 15 EDS line analyses.

[0109] Furthermore, as described above, the core 12 and shell 14 in the dielectric grain 10 can be distinguished by EDS line analysis. For example, the core 12 can be a region based on 100 moles of Ti with a Zr content of less than about 3 moles, and the shell 14 can be a region based on 100 moles of Ti with a Zr content of greater than or equal to about 3 moles.

[0110] According to some embodiments, the diameter of the core 12 can be about 15% to about 85% of the diameter of the dielectric grain 10 (e.g., about 18% to about 82%, about 20% to about 80%, about 23% to about 77%, or about 25% to about 75%). When the diameter of the core is within the above range, the multilayer ceramic capacitor can not only have excellent temperature characteristics, but also high capacitance and high voltage characteristics.

[0111] The ratio of the diameter of the core 12 to the diameter of the dielectric grain 10 can be measured by the following method.

[0112] In each TEM image of the upper, central, and lower regions, for each region, at least one dielectric layer 111 is randomly selected, and then at least one dielectric grain 10 with a core-shell structure is selected from the selected dielectric layer 111. The diameter of the dielectric grain 10 and the diameter of the core 12 are then measured to obtain the ratio of the diameter of the core 12 to the diameter of the dielectric grain 10. For example, by randomly selecting one dielectric layer for each region and selecting five dielectric grains with a core-shell structure for each dielectric layer, the average ratio of the diameter of the core to the diameter of the dielectric grain of a total of 15 dielectric grains can be calculated. At this time, the diameter of the dielectric grain 10 can be the average of the length of the major axis with the largest diameter passing through the center of the dielectric grain 10 and the length of the minor axis with the smallest diameter. In addition, the diameter of the core 12 can be the average of the length of the core 12 obtained at the length of the major axis with the largest diameter passing through the center of the dielectric grain 10 and the length of the core 12 obtained at the length of the minor axis with the smallest diameter passing through the center of the dielectric grain 10.

[0113] The number of dielectric grains 10 with a core-shell structure can be from about 5% to about 100% of the total number of dielectric grains present in the dielectric layer 111 (e.g., from about 10% to about 95%, from about 15% to about 90%, or from about 20% to about 85%). When the number of dielectric grains 10 with a core-shell structure is within the above range, the multilayer ceramic capacitor can not only have excellent temperature characteristics, but also high capacitance and high voltage characteristics.

[0114] The ratio of the number of core-shell structured dielectric grains 10 to the total number of dielectric grains can be measured by the following method.

[0115] In each TEM image of the upper, central, and lower regions, at least one dielectric layer 111 is randomly selected for each region, and the total number of dielectric grains present in the dielectric layer 111 and the number of dielectric grains 10 with core-shell structures are measured to obtain the ratio of the number of dielectric grains 10 with core-shell structures to the total number of dielectric grains. For example, by randomly selecting two dielectric layers for each region, the average ratio of the number of dielectric grains 10 with core-shell structures to the total number of dielectric grains in a total of six dielectric layers can be calculated.

[0116] The average thickness (average dimension in the T-axis direction) of the dielectric layer 111 can be from about 0.1 μm to about 8.0 μm, for example, from about 0.1 μm to about 6.0 μm. When the average thickness of the dielectric layer 111 is within the above range, the reliability of the multilayer ceramic capacitor can be improved.

[0117] The average thickness of dielectric layer 111 can be measured by immersing the multilayer ceramic capacitor 100 in an epoxy mixture, curing it, polishing it, then ion-milling it, and finally analyzing it using a scanning electron microscope (SEM). For example, SEM measurements can be performed at a voltage of 10 kV and a magnification of 100x, and can be measured in the effective region where dielectric layer 111 is alternately stacked with inner electrode layers 121 and 122, such that at least one layer of dielectric layer 111 (e.g., 3, 5, or 10 layers) is visible. In the SEM image, the average thickness of the dielectric layer can be obtained by taking the center point of the dielectric layer 111 along its length direction (L-axis direction) or width direction (W-axis direction) as a reference point in the scanning electron microscope (SEM) image, and calculating the average thickness of dielectric layer 111 at 10 points spaced at predetermined intervals from the reference point. The spacing between any two adjacent points among the 10 points can be adjusted according to the scale of the SEM image, for example, it can be adjusted to approximately 1 μm to approximately 100 μm, approximately 1 μm to approximately 50 μm, or approximately 1 μm to approximately 10 μm. In this case, all 10 points must be located within the dielectric layer 111, and if not all 10 points are located within the dielectric layer 111, the position of the reference point can be changed, or the spacing between any two adjacent points among the 10 points can be adjusted. Furthermore, by extending this average measurement to 10 dielectric layers and then averaging the results, the average thickness of the dielectric layers can be more generalized.

[0118] Inner electrode layer The inner electrode layers 121 and 122 (i.e., the first inner electrode layer 121 and the second inner electrode layer 122) are electrode layers with different polarities and are alternately arranged to be opposite each other along the T-axis direction, with the dielectric layer 111 located between the inner electrode layers 121 and 122. One end of the first inner electrode layer 121 and one end of the second inner electrode layer 122 can be exposed through the third surface and the fourth surface of the capacitor body 110, respectively.

[0119] The first inner electrode layer 121 and the second inner electrode layer 122 are electrically insulated from each other by a dielectric layer 111 disposed between them.

[0120] One end of the first inner electrode layer 121 and one end of the second inner electrode layer 122, which are alternately exposed through the third and fourth surfaces of the capacitor body 110, can be electrically connected to the first outer electrode 131 and the second outer electrode 132, respectively.

[0121] The inner electrode layers 121 and 122 comprise a conductive metal and may include at least one metal selected from the group consisting of Ni, Cu, Ag, Pd, Au, and alloys thereof.

[0122] Additionally, inner electrode layers 121 and 122 may include dielectric particles having the same composition as the ceramic material included in dielectric layer 111.

[0123] The inner electrode layers 121 and 122 can be formed using a conductive paste comprising a conductive metal. The printing method for the conductive paste can be screen printing or gravure printing.

[0124] The average thickness of each of the first inner electrode layer 121 and the second inner electrode layer 122 can be from about 0.1 μm to about 2.0 μm.

[0125] The average thickness of the first inner electrode layer 121 and the second inner electrode layer 122 can be measured by scanning electron microscopy (SEM) analysis. Specifically, in the SEM image of a cross-sectional sample obtained by the same method used to measure the average thickness of the dielectric layer 111, the average thickness of the inner electrode layer can be obtained by taking the center point of the inner electrode layer 121 or 122 along its length direction (L-axis direction) or width direction (W-axis direction) as a reference point, and calculating the average thickness of the inner electrode layer 121 or 122 at 10 points spaced apart from the reference point at predetermined intervals. The interval between any two adjacent points among the 10 points can be adjusted according to the scale of the SEM image, for example, it can be adjusted to about 1 μm to about 100 μm, about 1 μm to about 50 μm, or about 1 μm to about 10 μm. At this point, all 10 points must be located within the inner electrode layer 121 or 122. If not all 10 points are located within the inner electrode layer 121 or 122, the position of the reference point can be changed, or the interval between any two adjacent points can be adjusted. Furthermore, by extending this average measurement to all 10 inner electrode layers and then averaging the results, the average thickness of the inner electrode layers can be more generalized.

[0126] The capacitor body 110 can be formed by firing a stacked structure having multiple dielectric layers 111 and multiple internal electrode layers 121 and 122.

[0127] external electrode The external electrodes 131 and 132 (i.e., the first external electrode 131 and the second external electrode 132) are provided with voltages of different polarities and can be electrically connected to the exposed portions of the first inner electrode layer 121 and the second inner electrode layer 122, respectively.

[0128] According to the above structure, when a predetermined voltage is applied to the first external electrode 131 and the second external electrode 132, charge accumulates between the first inner electrode layer 121 and the second inner electrode layer 122 that are opposite to each other. At this time, the capacitance of the multilayer capacitor 100 is proportional to the stacked area of ​​the first inner electrode layer 121 and the second inner electrode layer 122 that are stacked together along the T-axis direction in the effective region.

[0129] The first external electrode 131 may include a first connecting portion disposed on the third surface of the capacitor body 110 and connected to the first inner electrode layer 121, and a first strip portion disposed on the edge where the third surface of the capacitor body 110 intersects with the first surface and the second surface and / or the fifth surface and the sixth surface. The second external electrode 132 may include a second connecting portion disposed on the fourth surface of the capacitor body 110 and connected to the second inner electrode layer 122, and a second strip portion disposed on the edge where the fourth surface of the capacitor body 110 intersects with the first surface and the second surface and / or the fifth surface and the sixth surface.

[0130] The first strip may extend from the first connecting portion to a portion of the first surface, a portion of the second surface, and / or a portion of the fifth surface and a portion of the sixth surface of the capacitor body 110. The second strip may extend from the second connecting portion to a portion of the first surface, a portion of the second surface, and / or a portion of the fifth surface and a portion of the sixth surface of the capacitor body 110. The first strip and the second strip may be used to improve the bonding strength between the first external electrode 131 and the second external electrode 132 and the capacitor body 110, respectively.

[0131] The external electrodes 131 and 132 may include a sintered metal layer in contact with the capacitor body 110, a conductive resin layer configured to cover the sintered metal layer, and a plating layer configured to cover the conductive resin layer.

[0132] The sintered metal layer may include conductive metals and glass.

[0133] The conductive metal may include one or more selected from copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof. For example, "conductive metal includes copper (Cu)" may mean that the conductive metal includes elemental copper (Cu) and / or copper (Cu) alloys. When the conductive metal includes copper (Cu), based on 100 molar parts of copper (Cu), other metals may be included in an amount of less than or equal to about 5 molar parts.

[0134] The glass may comprise a composition of mixed oxides (e.g., one or more selected from the group consisting of silicon oxides, boron oxides, aluminum oxides, transition metal oxides, alkali metal oxides, and alkaline earth metal oxides). The transition metals may include at least one selected from the group consisting of zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), and nickel (Ni); the alkali metals may include at least one selected from the group consisting of lithium (Li), sodium (Na), and potassium (K); and the alkaline earth metals may include at least one selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).

[0135] Optionally, the conductive resin layer may be formed on the sintered metal layer, for example, it may be formed in a shape that completely covers the sintered metal layer. Furthermore, the external electrodes 131 and 132 may not include the sintered metal layer, and in this case, the conductive resin layer may directly contact the capacitor body 110.

[0136] The conductive resin layer extends to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110, and the length of the region (i.e., the strip portion) where the conductive resin layer extends and is disposed on the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110 may be longer than the length of the region (i.e., the strip portion) where the sintered metal layer extends and is disposed on the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110. In other words, the conductive resin layer may be formed on the sintered metal layer and may be formed in a shape that completely covers the sintered metal layer.

[0137] The conductive resin layer may include resin and conductive metal.

[0138] The resin included in the conductive resin layer can be, but is not limited to, a material that has adhesive and shock-absorbing properties and can form a paste when mixed with conductive metal powder. For example, the resin may include phenolic resin, acrylic resin, silicone resin, epoxy resin, or polyimide resin.

[0139] The conductive metal included in the conductive resin layer is used to electrically connect the inner electrode layers 121 and 122 or the sintered metal layer to the plating described below.

[0140] The conductive metal included in the conductive resin layer may have a spherical shape, a sheet shape, or a combination thereof. That is, the conductive metal may be formed only as a sheet shape, or only as a spherical shape, or a mixture of sheet and spherical shapes.

[0141] Here, spherical shape can also include shapes that are not perfect spheres. For example, a spherical shape can refer to a shape whose length ratio of the major axis to the minor axis (major axis / minor axis) is less than or equal to about 1.45. A sheet shape refers to a flat and elongated shape, and there are no particular limitations. For example, a sheet shape can refer to a shape whose length ratio of the major axis to the minor axis (major axis / minor axis) is greater than or equal to about 1.95.

[0142] The external electrodes 131 and 132 may also include a plating layer disposed outside the conductive resin layer.

[0143] The coating may include at least one selected from the group consisting of nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof. For example, the coating may be a Ni coating or a Sn coating, or a Ni coating and a Sn coating stacked sequentially, or a Sn coating, a Ni coating, and a Sn coating stacked sequentially. Additionally, the coating may include multiple Ni coatings and / or multiple Sn coatings.

[0144] The coating can improve the mountability, structural reliability, external durability, heat resistance and equivalent series resistance (ESR) of the multilayer ceramic capacitor 100 on the substrate.

[0145] Methods for manufacturing multilayer ceramic capacitors The following describes a method for manufacturing a multilayer ceramic capacitor 100 according to some embodiments.

[0146] The multilayer ceramic capacitor 100 according to the embodiment can be manufactured by: preparing a dielectric paste comprising a main component powder (including a barium titanate-based compound and a zirconium-based compound); manufacturing a dielectric green sheet from the dielectric paste and forming a conductive paste layer on the surface of the dielectric green sheet; manufacturing a dielectric green sheet stack by stacking a plurality of dielectric green sheets on which the conductive paste layer is formed; manufacturing a capacitor body comprising a dielectric layer and an inner electrode layer by firing the dielectric green sheet stack; and forming an outer electrode on the outer surface of the capacitor body.

[0147] Barium titanate-based compounds may include at least one selected from the group consisting of BaTiO3, Ba(Ti, Sn)O3, (Ba, Ca)TiO3 and (Ba, Sr)TiO3.

[0148] Zirconium-based compounds may include at least one selected from the group consisting of compounds containing Zr and Ca and compounds containing Zr and Sr.

[0149] For example, zirconium-based compounds may include one or more selected from the group consisting of CaZrO3, SrZrO3, (Ba, Ca)ZrO3, and (Ba, Sr)ZrO3. For example, zirconium-based compounds may include one or both selected from CaZrO3 and SrZrO3.

[0150] Barium titanate-based compounds and zirconium-based compounds can be used in a mixed form or as a coating. That is, the main component powder includes a mixture of barium titanate-based compounds and zirconium-based compounds, or a composite in which a zirconium-based compound is coated on the surface of a barium titanate-based compound.

[0151] For example, the complex can be a complex that forms a core and a shell, with the core being a barium titanate-based compound (as a ferroelectric) and the shell being coated on the surface of the core using a zirconium-based compound (as a paraelectric).

[0152] Based on the total amount of barium titanate-based compounds and zirconium-based compounds, zirconium-based compounds can be included in amounts from about 1 mol% to about 20 mol% (e.g., from about 2 mol% to about 19 mol%, from about 3 mol% to about 18 mol%, or from about 4 mol% to about 17 mol%). When zirconium-based compounds are included within the above content range, multilayer ceramic capacitors can exhibit excellent temperature characteristics as well as high capacitance and high voltage characteristics.

[0153] Dielectric pastes may also include by-product powders.

[0154] The secondary component powder may include at least one selected from the group consisting of silicon (Si) compounds, rare earth element compounds, and transition metal compounds.

[0155] For example, rare earth element compounds may include at least one selected from the group consisting of dysprosium (Dy) compounds, gadolinium (Gd) compounds, lanthanum (La) compounds, and cerium (Ce) compounds.

[0156] Based on 100 molar parts of the main component powder, rare earth element compounds may be included in amounts from about 0.5 molar parts to about 10 molar parts.

[0157] For example, transition metal compounds may include at least one selected from the group consisting of manganese (Mn) compounds, vanadium (V) compounds, and chromium (Cr) compounds.

[0158] For example, the secondary component powder may include silicon (Si) compounds, rare earth element compounds, and transition metal compounds.

[0159] Dielectric pastes can be prepared by further mixing additives (such as dispersants, binders, plasticizers, lubricants, and antistatic agents) and solvents.

[0160] For example, the dispersant may include at least one selected from the group consisting of phosphate ester dispersants and polycarboxylic acid dispersants. Based on 100 parts by weight of the barium titanate-based compound, the dispersant can be mixed in amounts from about 0.1 parts by weight to about 5 parts by weight (e.g., from about 0.3 parts by weight to about 3 parts by weight). When the dispersant is mixed within the above-mentioned content range, the dielectric paste exhibits excellent dispersibility and the amount of impurities included in the manufactured dielectric layer can be reduced.

[0161] For example, the binder can be acrylic resin, polyvinyl butyral resin, polyvinyl acetal resin, ethyl cellulose resin, etc. Based on 100 parts by weight of barium titanate-based compound, the binder can be added in amounts from about 0.1 parts by weight to about 50 parts by weight (e.g., from about 3 parts by weight to about 30 parts by weight). When the binder is mixed within the above content range, the dielectric paste exhibits excellent dispersibility and reduces the amount of impurities included in the manufactured dielectric layer.

[0162] For example, plasticizers can be: phthalic acid compounds (such as dioctyl phthalate, butyl benzyl phthalate, dibutyl phthalate, dihexyl phthalate, di(2-ethylhexyl) phthalate, and di(2-ethylbutyl) phthalate); adipate compounds (such as dihexyl adipate and di(2-ethylhexyl) adipate); glycol compounds (such as ethylene glycol, diethylene glycol, and triethylene glycol); glycol ester compounds (such as triethylene glycol dibutyrate, triethylene glycol di(2-ethylbutyrate), and triethylene glycol di(2-ethylhexanoate)), etc. Based on 100 parts by weight of barium titanate compound, the plasticizer can be added in an amount of about 0.1 parts by weight to about 20 parts by weight (e.g., about 1 part by weight to about 10 parts by weight). When plasticizers are mixed within the above-mentioned content range, the dielectric paste exhibits excellent dispersibility and reduces the amount of impurities included in the manufactured dielectric layer.

[0163] Solvents can be: aqueous solvents (such as water); alcohol solvents (such as ethanol, methanol, benzyl alcohol, and methoxyethanol); glycol solvents (such as ethylene glycol and diethylene glycol); ketone solvents (such as acetone, methyl ethyl ketone, methyl isobutyl ketone, and cyclohexanone); ester solvents (such as butyl acetate, ethyl acetate, carbitol acetate, and butyl carbitol acetate); ether solvents (such as methyl cellosolve, ethyl cellosolve, butyl ether, and tetrahydrofuran); aromatic solvents (such as benzene, toluene, and xylene), etc. For example, considering the solubility or dispersibility of the various additives included in the dielectric paste, the solvent can be an alcohol solvent or an aromatic solvent. Based on 100 parts by weight of barium titanate compound, the solvent can be mixed in an amount of about 50 parts by weight to about 1000 parts by weight (e.g., about 100 parts by weight to about 500 parts by weight). When the solvent is mixed within the above-mentioned content range, the various components of the dielectric paste can be sufficiently mixed, and the solvent can be easily removed subsequently.

[0164] The dielectric slurry described above can be mixed using a wet ball mill or a stirred mill. When using zirconia balls in a wet ball mill, multiple zirconia balls with a diameter of about 0.1 mm to about 10 mm can be used for wet mixing for about 8 hours to about 48 hours, for example, about 10 hours to about 24 hours.

[0165] The prepared dielectric paste forms a dielectric layer after firing.

[0166] Methods such as strip forming (e.g., doctor blade method) and casting roll method (e.g., using a coating head discharge type roller forming coating machine) can be used to form the prepared dielectric paste into a sheet-like molded body, which can then be dried to obtain a dielectric green sheet.

[0167] To form a conductive paste layer that becomes the inner electrode layer after firing, the conductive paste can be prepared by mixing conductive powder made from conductive metals or alloys thereof, a binder, and a solvent. Additionally, barium titanate powder can be mixed in as a co-material if desired. The co-material can be used to suppress the sintering of the conductive powder during the firing process. The conductive paste layer is formed by applying the conductive paste in a predetermined pattern to the surface of the dielectric sheet using various printing methods (such as screen printing) or transfer printing.

[0168] The conductive powder may include nickel (Ni) or nickel (Ni) alloys.

[0169] Next, a dielectric green sheet stack is prepared by stacking multiple dielectric green sheets on which conductive paste layers are formed, and then pressing the multiple dielectric green sheets in the stacking direction. At this time, dielectric green sheets without conductive paste layers can be stacked on top of each other, such that the dielectric green sheets without conductive paste layers are disposed at the upper and lower parts of the dielectric green sheet stack in the stacking direction.

[0170] Optionally, the process of cutting the manufactured dielectric wafer stack into a predetermined size by means of cutting or the like can be performed.

[0171] Additionally, if necessary, the dielectric green sheet stack can be cured and dried to remove plasticizers, etc., and after curing and drying, the dielectric green sheet stack can be tumble polished using a horizontal centrifugal tumbler or similar device. During tumble polishing, the dielectric green sheet stack, along with the dielectric and polishing fluid, is placed in a tumbler container, and rotational motion or vibration is applied to the tumbler container to polish unwanted parts (such as burrs generated during cutting). After tumble polishing, the dielectric green sheet stack can be washed with a cleaning solution (such as water) and then dried.

[0172] Subsequently, the capacitor body can be obtained after adhesive removal (calcination) and firing treatment of the dielectric green sheet stack.

[0173] The conditions for adhesive removal processing can be appropriately adjusted according to the composition of the dielectric layer and / or the composition of the internal electrode layer. For example, the heating rate during adhesive removal processing can be from about 5°C / hour to about 300°C / hour, the holding temperature can be from about 180°C to about 400°C, and the holding time can be from about 0.5 hours to about 24 hours. Adhesive removal processing can be performed in an air atmosphere or a reducing atmosphere.

[0174] The firing conditions can be appropriately adjusted according to the main component composition of the dielectric layer and / or the main component composition of the inner electrode layer. For example, firing can be performed at a temperature of about 1100°C to about 1400°C, or, for example, at a temperature of about 1200°C to about 1350°C. Additionally, firing can be performed for about 0.5 hours to about 8 hours (e.g., about 1 hour to about 3 hours). Furthermore, firing can be performed in a reducing atmosphere (e.g., in a mixture of nitrogen and hydrogen), for example, under conditions such as a hydrogen concentration (volume concentration) less than or equal to about 1.0%. When the inner electrode layer comprises nickel (Ni) or a nickel (Ni) alloy, the oxygen partial pressure in the firing atmosphere can be about 1.0 × 10⁻⁶. -14 MPa to approximately 1.0 × 10 -10 MPa.

[0175] After firing, annealing may be performed as needed. Annealing is a process that re-oxidizes the dielectric layer, and it can be performed if firing is carried out in a reducing atmosphere. The annealing conditions can also be appropriately adjusted according to the composition of the dielectric layer. For example, the annealing temperature can be from about 950°C to about 1150°C, the annealing time can be greater than 0 hours and less than or equal to about 20 hours, and the heating rate can be from about 50°C / hour to about 500°C / hour. The annealing atmosphere can be a moistened nitrogen (N2) atmosphere, and the oxygen partial pressure can be about 1.0 × 10⁻⁶. -9 MPa to approximately 1.0 × 10 -5 MPa.

[0176] In adhesive removal, firing, or annealing processes, a wetting agent may be used, for example, to wet nitrogen or a mixture of gases. In this case, the temperature of the wetting agent may be from about 5°C to about 75°C. Adhesive removal, firing, and annealing processes may be performed sequentially or independently.

[0177] Optionally, the third and fourth surfaces of the prepared capacitor body 110 can be surface-treated (such as by sandblasting, laser irradiation, or tumble polishing). By performing this surface treatment, the ends of the first inner electrode layer and the second inner electrode layer can be exposed to the third and fourth surfaces, respectively, thereby improving the electrical connection between the first outer electrode and the first inner electrode layer, as well as the electrical connection between the second outer electrode and the second inner electrode layer, and facilitating the formation of alloy portions.

[0178] Subsequently, an external electrode is formed on the surface of the manufactured capacitor body 110.

[0179] According to some embodiments, a paste for forming a sintered metal layer can be applied to the surface of the manufactured capacitor body and then sintered to form the sintered metal layer.

[0180] The paste used to form the sintered metal layer may include conductive metals and glass. Since the description of conductive metals and glass is the same as that described above, repeated descriptions will be omitted. Alternatively, the paste used to form the sintered metal layer may include binders, solvents, dispersants, plasticizers, oxide powders, etc. The binder may be, for example, ethyl cellulose resin, acrylic resin, butyral resin, etc., and the solvent may be, for example, an organic solvent (such as terpineol, butyl carbitol, ethanol, methyl ethyl ketone, acetone, toluene, etc.) or an aqueous solvent.

[0181] Methods for applying a paste for forming a sintered metal layer to the outer surface of the capacitor body 110 may include dipping, various printing methods (such as screen printing), coating methods using a dispenser, and spraying methods using a spray gun. The paste for forming the sintered metal layer may be applied to at least the third and fourth surfaces of the capacitor body 110, and optionally to portions of the first, second, fifth, and / or sixth surfaces on which the strips of the first and second external electrodes will be formed.

[0182] Subsequently, the capacitor body 110 coated with paste for forming a sintered metal layer is dried and sintered at a temperature of about 700°C to about 1000°C for about 0.1 hours to about 3 hours to form a sintered metal layer.

[0183] Optionally, a paste for forming a conductive resin layer is coated onto the outer surface of the obtained capacitor body 110 and then cured to form a conductive resin layer.

[0184] The paste used to form the conductive resin layer may include a resin and a conductive metal, and optionally, a non-conductive filler. Since the description of the conductive metal and resin is the same as that described above, repeated descriptions will be omitted. Additionally, the paste used to form the conductive resin layer may optionally include an adhesive, solvent, dispersant, plasticizer, oxide powder, etc. The adhesive may include, for example, ethyl cellulose resin, acrylic resin, butyral resin, etc., and the solvent may include organic solvents (such as terpineol, butyl carbitol, ethanol, methyl ethyl ketone, acetone, and toluene) or aqueous solvents.

[0185] For example, the conductive resin layer can be formed by immersing the capacitor body 110 in a paste for forming the conductive resin layer and then curing it, or by printing the paste for forming the conductive resin layer onto the surface of the capacitor body 110 by screen printing or gravure printing and then curing it, or by applying the paste for forming the conductive resin layer onto the surface of the capacitor body 110 and then curing it.

[0186] Next, a plating layer is formed on the outside of the conductive resin layer.

[0187] For example, the coating can be formed by plating (e.g., electroplating (electrodeposition)) or sputtering.

[0188] In the following description, embodiments will be illustrated in more detail with reference to examples. However, these examples are exemplary, and the scope of this disclosure is not limited thereto.

[0189] (Manufacturing of multilayer ceramic capacitors) Examples 1 to 5 Dielectric pastes are prepared by mixing main component powders with secondary component powders. The main component powders consist of barium titanate (BaTiO3) and calcium zirconate (CaZrO3) in a molar ratio of 9:1. The secondary component powders are mixtures of rare earth element oxides (including dysprosium oxide (Dy2O3) and gadolinium oxide (Gd2O3)), silicon dioxide (SiO2), and transition metal oxides (including manganese dioxide (MnO2), vanadium oxide (V2O5), and chromium oxide (Cr2O3)). Based on 100 molar parts of the main component powder, rare earth element oxides are mixed in amounts of 0.1 molar parts (Example 1), 0.5 molar parts (Example 2), 5.0 molar parts (Example 3), 10.0 molar parts (Example 4), and 13.0 molar parts (Example 5), respectively. Based on 100 molar parts of the main component powder, SiO2 is mixed in an amount of 2 molar parts. Based on 100 molar parts of the main component powder, transition metal oxides are mixed in an amount of 0.4 molar parts. Among them, the amount of rare earth element oxides refers to the total content of rare earth elements, the amount of SiO2 refers to the content of Si, and the amount of transition metal oxides refers to the total content of transition metals.

[0190] In addition, the dielectric paste is prepared by mechanically grinding zirconia balls (ZrO2 balls) as a dispersion medium after adding ethanol / toluene, a wetting and dispersing agent and polyvinyl butyral (PVB) as a binder to the main component powder and the secondary component powder.

[0191] Dielectric green sheets are manufactured using a coating head discharge roller forming coating machine with prepared dielectric paste.

[0192] A conductive paste layer including nickel (Ni) is printed on the surface of a dielectric green sheet, and dielectric green sheets with the conductive paste layer formed thereon are stacked and pressed to manufacture a dielectric green sheet stack.

[0193] The dielectric green sheet stack is calcined in a nitrogen atmosphere at a temperature of 400°C or lower, and then calcined at a temperature of less than or equal to 1300°C and a hydrogen (H2) concentration (volume concentration) of less than or equal to 1.0% to form the capacitor body.

[0194] Next, an external electrode is formed on the surface of the capacitor body through processes such as plating, thereby obtaining a multilayer ceramic capacitor.

[0195] Comparative Example 1 In addition to using BaTiO3 alone as the main component powder, multilayer ceramic capacitors are manufactured in the same manner as in Example 3.

[0196] Evaluation 1: TEM-EDS Analysis The multilayer ceramic capacitors manufactured in Examples 1 to 5 and Comparative Example 1 were analyzed by TEM-EDS (transmission electron microscopy-energy dispersive spectroscopy) using the following methods, and the results are presented below. Figures 6A to 6G , Figure 7A and Figure 7B And in Table 1 below.

[0197] Each multilayer ceramic capacitor was immersed in an epoxy mixture and cured. The L-axis and T-axis surfaces (LT surfaces) of the capacitor body were then polished to half the length of the capacitor body along the W-axis to obtain a cross-sectional sample, allowing observation of the effective region where dielectric and inner electrode layers are alternately stacked. Next, when the effective region of the cross-sectional sample was divided into three regions (upper, central, and lower), each region was measured using transmission electron microscopy (TEM) to ensure that at least one dielectric layer and at least one inner electrode layer were visible in each region. TEM measurements were performed using Xe-FIB (focused ion beam) at an accelerating voltage of 200 kV and a magnification of 50,000x. Finally, EDS (energy-dispersive spectroscopy) surface scanning analysis was performed on the dielectric layers of the measured TEM images of the cross-sectional sample.

[0198] Figures 6A to 6G It is based on the TEM-EDS (transmission electron microscopy-energy dispersive spectroscopy) surface scan analysis image of the dielectric layer in Example 3.

[0199] Reference Figures 6A to 6G As shown in Table 1 below, the dielectric layer according to Example 3 comprises grain boundaries and dielectric grains with a core-shell structure. Furthermore, it is confirmed that Ba and Ti are present in the core of the dielectric grains, and Ca and Zr are present in the shell of the dielectric grains. Additionally, it is confirmed that Si is present at the grain boundaries.

[0200] In addition, in each TEM image of the measured upper, central, and lower regions, a dielectric layer was randomly selected for each region, and for each dielectric layer, five grain boundaries and five dielectric grains with core-shell structures were selected. EDS line analysis was performed on each of the 15 dielectric grains and 15 grain boundaries in total. EDS line analysis was performed on the long axis straight segment passing through the center of the dielectric grain with core-shell structure.

[0201] Figure 7A and Figure 7B The image is based on the TEM-EDS (transmission electron microscopy-energy dispersive spectroscopy) line analysis image of the dielectric layer in Example 3.

[0202] Reference Figure 7A and Figure 7B In Example 3, the core within the dielectric grain can be a region based on 100 moles of Ti with a Zr content of less than 3 moles, and the shell can be a region based on 100 moles of Ti with a Zr content of greater than or equal to 3 moles.

[0203] In addition, the total content of rare earth elements present in the shell of the dielectric grains was measured by TEM-EDS line analysis, and the results are shown in Table 1 below. In Table 1, the total content of rare earth elements is the average value of the rare earth element content obtained from the EDS line analysis of the above 15 dielectric grains, and the total content of rare earth elements is expressed based on 100 moles of Ti.

[0204] (Table 1)

[0205] As can be seen from the TEM-EDS analysis above, in the cases of Examples 1 to 5, Ba and Ti are present in the core of the dielectric grain, and Ca and Zr are present in the shell of the dielectric grain. However, in the case of Comparative Example 1, Ca and Zr are not present in the dielectric grain.

[0206] Evaluation 2: Temperature Characteristics (TCC) The temperature coefficient of capacitance (TCC) of the multilayer ceramic capacitors manufactured in Examples 1 to 4 and Comparative Example 1 were measured using the following method, and the results are presented below. Figure 8 middle.

[0207] The capacitance was measured at 2°C intervals over a temperature range of -55°C to 150°C at a frequency of 1 kHz and an AC voltage of 1 V. Using the measured capacitance, the rate of change of capacitance at each temperature relative to the capacitance at 25°C was calculated according to Equation 1 below.

[0208] [Formula 1] Capacitance change rate (%) = [(C - CRT) / CRT] × 100% In Equation 1, C is the capacitance measured in the temperature range of -55℃ to 150℃, and CRT is the capacitance measured at 25℃.

[0209] Figure 8 This is a graph showing the temperature coefficient of capacitance (TCC) of the multilayer ceramic capacitors according to Examples 1 to 4 and Comparative Example 1.

[0210] Reference Figure 8 In Examples 1 to 4, where Ba and Ti are included in the core and Ca and Zr are included in the shell, it can be seen that the capacitance changes little between -55°C and 125°C, so that the temperature characteristics meet the X7R grade (i.e., the temperature characteristics are excellent).

[0211] Evaluation 3: Step-Insulation Resistance (STEP-IR) Measurement The STER-IR (i.e., resistance degradation behavior according to voltage step increase) of the multilayer ceramic capacitors manufactured in Examples 2 to 5 and Comparative Example 1 was evaluated using the following method, and the results are presented in [the table / document]. Figure 9 middle.

[0212] STEP-IR measurements are performed by increasing the voltage by 50V increments at 150°C for 5 minutes at 10-second intervals to measure the resistance degradation behavior.

[0213] In addition, the withstand voltage characteristics were evaluated by STEP-IR measurement. This means that when measured by applying a DC 50V voltage step at 150°C for 5 minutes and continuously increasing the voltage step, the withstand voltage is 10V under IR resistance. 5 Voltage at Ω or greater.

[0214] Figure 9 The graph shows the STEP-IR characteristics of the multilayer ceramic capacitors according to Examples 2 to 5 and Comparative Example 1.

[0215] Reference Figure 9 As can be seen, compared with Comparative Example 1, Examples 2 to 5, in which Ba and Ti are included in the core and Ca and Zr are included in the shell, exhibit better withstand voltage characteristics.

[0216] Evaluation 4: DC bias characteristics The DC bias characteristics of the multilayer ceramic capacitors manufactured in Examples 1 to 5 and Comparative Example 1 were evaluated using the following methods, and the results are presented in [the table / document]. Figure 10 middle.

[0217] At 1 kHz and AC 1 V, DC 0 V / μm, 1.0 V / μm, 4.8 V / μm, 9.6 V / μm, 14.3 V / μm, 19.1 V / μm and 23.9 V / μm were held for 60 seconds, and then each dielectric constant was measured.

[0218] Figure 10 The graph shows the DC bias characteristics of the multilayer ceramic capacitors according to Examples 1 to 5 and Comparative Example 1.

[0219] Reference Figure 10 As can be seen, the DC bias characteristics of Examples 1 to 5, in which Ba and Ti are included in the core and Ca and Zr are included in the shell, are better than those of Comparative Example 1.

[0220] While this disclosure has been described in conjunction with embodiments now considered practical, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather, on the contrary, is intended to cover various variations and equivalents included within the spirit and scope of the appended claims.

[0221] <Explanation of reference numerals in the attached figures> 10: Dielectric grains 12: Core 14: Shell 20: Grain boundary 100: Multilayer ceramic capacitor 110: Capacitor body 111: Dielectric layer 121: First inner electrode layer 122: Second inner electrode layer 131: First external electrode 132: Second external electrode.

Claims

1. A multilayer ceramic capacitor comprising: a capacitor body including dielectric layers and internal electrode layers; and an external electrode provided on an outer surface of the capacitor body, wherein the dielectric layers include a plurality of dielectric grains, at least one of the plurality of dielectric grains has a core-shell structure including a core portion and a shell portion surrounding at least a portion of the core portion, the core portion includes Ba and Ti, the shell portion includes Zr and Ca and / or Sr, and in a transmission electron microscope-energy dispersive spectroscopy line analysis across a long axis straight line segment passing through a center of the at least one dielectric grain having the core-shell structure, the core portion includes less than 3 moles of Zr per 100 moles of Ti, and the shell portion includes 3 moles or more of Zr per 100 moles of Ti.

2. The multilayer ceramic capacitor according to claim 1, wherein the shell portion includes 2.5 moles to 40 moles of Ca or 2.5 moles to 40 moles of Sr, or a total amount of 2.5 moles to 40 moles of Ca and Sr, per 100 moles of Ti.

3. The multilayer ceramic capacitor according to claim 1, wherein the shell portion includes Zr in an amount of 3 moles to 150 moles per 100 moles of Ti.

4. The multilayer ceramic capacitor according to claim 1, wherein the shell portion includes Ca in an amount of 2.5 moles to 40 moles per 100 moles of Ti, and the shell portion includes Zr in an amount of 3 moles to 150 moles per 100 moles of Ti.

5. The multilayer ceramic capacitor according to claim 1, wherein the shell portion includes Sr in an amount of 2.5 moles to 40 moles per 100 moles of Ti, and the shell portion includes Zr in an amount of 3 moles to 150 moles per 100 moles of Ti.

6. The multilayer ceramic capacitor according to claim 1, wherein the shell portion further includes a rare earth element.

7. The multilayer ceramic capacitor according to claim 6, wherein the rare earth element includes a rare earth element having an ionic radius larger than that of Y.

8. The multilayer ceramic capacitor according to claim 6, wherein the rare earth element includes at least one selected from the group consisting of Dy, Gd, La, and Ce.

9. The multilayer ceramic capacitor according to claim 6, wherein the shell portion includes the rare earth element in an amount of 0.5 moles to 10 moles per 100 moles of Ti.

10. The multilayer ceramic capacitor according to claim 1, wherein the shell portion further includes a transition metal.

11. The multilayer ceramic capacitor according to claim 10, wherein the transition metal includes at least one selected from the group consisting of Mn, V, and Cr.

12. The multilayer ceramic capacitor according to claim 1, wherein the shell portion further includes a rare earth element and a transition metal.

13. The multilayer ceramic capacitor according to claim 12, wherein ​ The rare earth element includes at least one selected from the group consisting of Dy, Gd, La, and Ce, and the transition metal includes at least one selected from Mn, V, and Cr.

14. The multilayer ceramic capacitor according to claim 1, wherein, the dielectric layer further includes grain boundaries disposed between the plurality of dielectric grains, and the grain boundaries include Si.

15. The multilayer ceramic capacitor according to claim 14, wherein, the grain boundaries include Si in an amount of 2.5 to 20 moles per 100 moles of Ti.

16. The multilayer ceramic capacitor according to claim 14, wherein, the grain boundaries further include rare earth elements.

17. The multilayer ceramic capacitor according to claim 16, wherein, the rare earth element includes at least one selected from the group consisting of Dy, Gd, La, and Ce.

18. The multilayer ceramic capacitor according to claim 16, wherein, the grain boundaries include the rare earth element in an amount of 3 to 30 moles per 100 moles of Ti.

19. The multilayer ceramic capacitor according to claim 1, wherein, the diameter of the core portion of the at least one dielectric grain is 15% to 85% of the diameter of the at least one dielectric grain.

20. The multilayer ceramic capacitor according to claim 1, wherein, the number of dielectric grains having the core-shell structure is 5% to 100% of the total number of dielectric grains present in the dielectric layer.

21. A method of manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 20, comprising: preparing a dielectric paste including a main component powder, the main component powder including a barium titanate-based compound and a zirconium-based compound; manufacturing a dielectric green sheet from the dielectric paste, and forming a conductive paste layer on the surface of the dielectric green sheet; manufacturing a dielectric green sheet stack by stacking a plurality of the dielectric green sheets on which the conductive paste layer is formed; manufacturing the capacitor body including the dielectric layer and the internal electrode layer by firing the dielectric green sheet stack; and forming the external electrode on the outer surface of the capacitor body, wherein the zirconium-based compound includes at least one selected from the group consisting of a compound containing Zr and Ca and a compound containing Zr and Sr.

22. The method according to claim 21, wherein, the main component powder includes a mixture of the barium titanate-based compound and the zirconium-based compound, or includes a composite in which the zirconium-based compound is coated on the surface of the barium titanate-based compound.

23. The method according to claim 21, wherein, the zirconium-based compound includes at least one selected from CaZrO3 and SrZrO3.

24. The method according to claim 21, wherein, the dielectric paste further includes an auxiliary component powder, the auxiliary component powder including at least one selected from the group consisting of a Si-containing compound, a rare earth element-containing compound, and a transition metal-containing compound.

25. The method according to claim 24, wherein, The rare earth element-containing compound includes at least one selected from the group consisting of Dy-containing compounds, Gd-containing compounds, La-containing compounds, and Ce-containing compounds.

26. The method according to claim 24, wherein, The transition metal compound includes at least one selected from the group consisting of Mn-containing compounds, V-containing compounds, and Cr-containing compounds.

27. The method according to claim 24, wherein, The by-component powder includes the Si-containing compound, the rare earth element-containing compound, and the transition metal-containing compound.

28. The method according to claim 21, wherein, The zirconium-based compound is included in an amount of 1 mol% to 20 mol% based on the total amount of the barium titanate-based compound and the zirconium-based compound.

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