High-speed voltage comparator

Abstract

The invention discloses a high-speed voltage comparator which is additionally provided with an edge quick response circuit, and then when an input signal of the comparator jumps from a low level to a high level or from the high level to the low level, the edge quick response circuit is switched to the edge quick response circuit. The edge quick response circuit controls the voltage quick change of the control ends of the pull-up device and the pull-down device in the comparator, and accelerates the switching process of the pull-up device and the pull-down device, so that the comparator can finish level judgment more quickly. According to the invention, the response speed of the comparator can be optimized on the premise that the circuit power consumption and the circuit complexity are not obviously increased.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more specifically to a high-speed voltage comparator. Background Technology

[0002] Voltage comparators are one of the core fundamental modules in analog integrated circuits and mixed-signal systems. Their function is to compare the magnitudes of two input voltages in real time and output the comparison result in digital form as either a high or low level. The performance of the comparator directly determines the key indicators of the entire system, such as speed, accuracy, and power consumption. They are widely used in high-speed analog-to-digital converters (ADCs), digital-to-analog converters (DACs), memory read circuits, clock data recovery circuits, and various amplitude and phase detection scenarios.

[0003] Figure 1 This is a circuit schematic of a typical high-speed voltage comparator in existing technology, as shown in the figure. It adopts a pre-amplifier + latch structure. The pre-amplifier stage is used to amplify the small input differential voltage to improve the comparator's resolution and suppress latch kickback noise. The latch stage regenerates through a positive feedback mechanism to achieve fast level decision. The inverter buffer stage is used to convert the latch output to a standard logic level.

[0004] This classic structure still faces challenges when pursuing higher speeds. Its latch uses a positive feedback mechanism to control the sway of the pre-amplified signal, accelerating the rise of one input path while decreasing the rise of another, ultimately stabilizing the output. The delay of this process is as follows: Figure 2 As shown. Figure 2 The simulation diagram shows the delay time of the comparator at a power consumption of 122uA. It can be seen that the rise time delay is 10.2ns and the fall time delay is 9.3ns. To achieve higher comparison speeds, existing technologies typically require increasing the bias current of the preamplifier and latch, which directly leads to a significant increase in comparator power consumption. This invention aims to propose a better solution. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a solution that optimizes the comparator speed without significantly increasing the comparator power consumption and circuit complexity.

[0006] The specific details of this invention are as follows: A high-speed voltage comparator includes a differential input amplifier stage, a latch stage, and an output buffer stage. The differential input amplifier stage pre-amplifies the differential voltage of two input signals. The latch stage includes pull-up and pull-down devices. It receives the pre-amplified signal and outputs it as a high or low level through the pull-up and pull-down devices, and then outputs it through the output buffer stage. The high-speed voltage comparator further includes an edge-fast response circuit, whose input terminal is connected to the input of the differential input amplifier stage. When the input signal transitions from low to high or from high to low, the edge-fast response circuit controls the voltage at the control terminals of the pull-up and pull-down devices to change rapidly, accelerating the switching process of the pull-up and pull-down devices, thereby completing the level decision faster than using the original positive feedback mechanism of the latch.

[0007] As a preferred embodiment: the edge fast response circuit includes a rising edge fast response circuit and a falling edge fast response circuit, both of which are composed of capacitors and semiconductor transistors. One end of the capacitor is connected to the control terminal of the semiconductor transistor, and the other end is connected to the input of the differential input amplifier stage. The output terminal of the semiconductor transistor is connected to the control terminal of the pull-up device or pull-down device.

[0008] The inputs of the rising edge fast response circuit and the falling edge fast response circuit are connected in parallel.

[0009] The input signal is connected to the input terminal of the differential input amplifier stage through resistor R5, and the input terminals of the rising edge fast response circuit and the falling edge fast response circuit are connected to the negative terminal of resistor R5.

[0010] The semiconductor transistor is an NMOS or PMOS device.

[0011] Preferably, the high-speed voltage comparator further includes a bias circuit, which includes PMOS transistors P1, PMOS transistors P2, PMOS transistors P3, PMOS transistors P4, PMOS transistors P5, PMOS transistors P6, PMOS transistors P7, NMOS transistors N1, NMOS transistors N2, NMOS transistors N3, NMOS transistors N4, NMOS transistors N5, resistors R1 and R2, and capacitor C1. The sources of PMOS transistors P1, P3, P5, and P6, and the upper plate of capacitor C1 are connected to the power supply terminal VDD. The gate of PMOS transistor P1 is connected to the lower plate of capacitor C1, the gate of PMOS transistor P3, the gate of PMOS transistor P6, the drain of PMOS transistor P2, and the positive terminal of resistor R1, simultaneously serving as the output terminal of the bias circuit, outputting the bias voltage VBIAS1. The drain of PMOS transistor P1 is connected to the source of PMOS transistor P2. The gates of PMOS transistors P2, P4, and P7, and the negative terminal of resistor R1 are connected, simultaneously serving as the input terminal IBIAS of the bias circuit. The drain of PMOS transistor P3 is connected to the source of PMOS transistor P4. The drain of PMOS transistor P4 is connected to the positive terminal of resistor R2 and the gate of NMOS transistor N1. The negative terminal of resistor R2 is connected to the drain of NMOS transistor N1, the gate of NMOS transistor N2, and the gate of NMOS transistor N4; the source of NMOS transistor N1 is connected to the drain of NMOS transistor N2; the gate of PMOS transistor P5 is connected to the drain of PMOS transistor P5 and the drain of NMOS transistor N3, and also serves as the output terminal of the bias circuit, outputting the bias voltage VBIAS2; the source of NMOS transistor N3 is connected to the drain of NMOS transistor N4; the drain of PMOS transistor P6 is connected to the source of PMOS transistor P7; the drain of PMOS transistor P7 is connected to the drain of NMOS transistor N5 and the gate of NMOS transistor N5, and also serves as the output terminal of the bias circuit, outputting the bias voltage VBIAS3; the sources of NMOS transistors N2, NMOS transistor N4, and NMOS transistor N5 are connected to ground GND.

[0012] The differential input amplifier stage adopts a high-bandwidth, low-gain cascaded structure.

[0013] The differential input amplifier stage employs one or more PMOS transistor differential amplifier structures with resistive loads and one or more PMOS transistor differential amplifier structures with active loads cascaded together.

[0014] The differential input amplifier stage includes PMOS transistors P8, P9, P10, P11, P12, P13, P14, P15, P16, NMOS transistors N6, NMOS transistors N7, NMOS transistors N8, NMOS transistors N9, resistors R3, R4, R6, R7, and R5; The sources of PMOS transistors P8, P11, and P14 are connected to the power supply terminal VDD; the gates of PMOS transistors P8, P11, and P14 are connected to the bias voltage VBIAS1; the drain of PMOS transistor P8 is connected to the source of PMOS transistors P9 and P10; the gate of PMOS transistor P9 serves as one input terminal of the differential input amplifier stage, i.e., the high-speed voltage comparator, receiving the input signal VIN; the drain of PMOS transistor P9 is connected to the positive terminal of resistor R3 and the gate of PMOS transistor P12; the gate of PMOS transistor P10 serves as the other input terminal of the differential input amplifier stage, i.e., the high-speed voltage comparator, receiving the input signal VIP through resistor R5; the drain of PMOS transistor P10 is connected to the positive terminal of resistor R4 and the gate of PMOS transistor P13; the drain of PMOS transistor P11 is connected to the source of PMOS transistors P12 and P13; PMOS transistor P12... The drain of PMOS transistor P13 is connected to the positive terminal of resistor R6 and the gate of PMOS transistor P15; the drain of PMOS transistor P13 is connected to the positive terminal of resistor R7 and the gate of PMOS transistor P16; the drain of PMOS transistor P14 is connected to the source of PMOS transistors P15 and P16; the drain of PMOS transistor P15 is connected to the drain and gate of NMOS transistor N6, the drain of NMOS transistor N7, and the gate of NMOS transistor N8, and simultaneously serves as the differential input amplifier. One output terminal of the large stage is VCO2; the drain of PMOS transistor P16 is connected to the gate of NMOS transistor N7, the drain of NMOS transistor N8, the gate of NMOS transistor N9, and the drain of NMOS transistor N9. At the same time, it serves as another output terminal of the differential input amplifier stage, VCO3; the negative terminals of resistors R3, R4, R6, and R7, and the sources of NMOS transistors N6, NMOS transistor N7, NMOS transistor N8, and NMOS transistor N9 are connected to ground GND. PMOS transistors P8, PMOS transistors P9, PMOS transistors P10, resistors R3 and R4 constitute the first-stage PMOS transistor differential amplifier structure, and PMOS transistors P11, PMOS transistors P12, PMOS transistors P13, resistors R6 and R7 constitute the second-stage PMOS transistor differential amplifier structure. The two stages are identical. PMOS transistors P14, P15, P16, NMOS transistors N6, NMOS transistors N7, NMOS transistors N8, and NMOS transistors N9 constitute the third-stage PMOS differential amplifier structure, which includes two feedback paths: one is a cross-coupled positive feedback composed of NMOS transistors N7 and NMOS transistors N8, and the other is a common-source negative feedback composed of PMOS transistors P15 and P16, with the transconductance of the negative feedback being greater than that of the positive feedback.

[0015] The latch stage includes PMOS transistors P17, PMOS transistor P18, PMOS transistor P20, NMOS transistor N10, NMOS transistor N11, NMOS transistor N12, NMOS transistor N13, NMOS transistor N14, and NMOS transistor N15; The sources of PMOS transistors P17, P18, and P20 are connected to the power supply terminal VDD; the gate of PMOS transistor P17 is connected to the bias voltage VBIAS1; the drain of PMOS transistor P17 is connected to the drain, gate, NMOS transistor N12, and gate of NMOS transistor N14; the source of NMOS transistor N10 is connected to the drain and gate of NMOS transistor N11; the gate of PMOS transistor P18 is connected to the drain of PMOS transistor P18, the drain of NMOS transistor N12, and PM... The gate of PMOS transistor P20 is connected to the gate of NMOS transistor N12; the source of NMOS transistor N12 is connected to the drain of NMOS transistor N13; the drain of PMOS transistor P20 is connected to the drain of NMOS transistor N14 and the input terminal of the output buffer stage; the gate of NMOS transistor N13 is connected to one output terminal VCO2 of the differential input amplifier stage, and the gate of NMOS transistor N15 is connected to the other output terminal VCO3 of the differential input amplifier stage; the source of NMOS transistor N14 is connected to the drain of NMOS transistor N15; the sources of NMOS transistors N11, NMOS transistor N13, and NMOS transistor N15 are connected to ground GND.

[0016] The falling edge fast response circuit includes capacitor C2, PMOS transistor P19 and resistor R8; The rising edge fast response circuit includes capacitor C3, NMOS transistor N16 and resistor R9; The positive terminal of resistor R8 is connected to the bias voltage VBIAS2, and the negative terminal is connected to the gate of PMOS transistor P19 and the lower plate of capacitor C2. The upper plate of capacitor C2 is connected to the upper plate of capacitor C3 and is also connected to the inverting input of the differential input amplifier stage. The lower plate of capacitor C3 is connected to the negative terminal of resistor R9 and the gate of NMOS transistor N16. The positive terminal of resistor R9 is connected to the bias voltage VBIAS3. The drain of PMOS transistor P19 is connected to the gate of NMOS transistor N15. The source of PMOS transistor P19 is connected to the power supply terminal VDD. The drain of NMOS transistor N16 is connected to the gate of PMOS transistor P20. The source of NMOS transistor N16 is connected to the ground terminal GND.

[0017] Beneficial effects: The high-speed voltage comparator of this invention adds an edge-fast response circuit. This circuit directly controls the conduction of the pull-up and pull-down devices of the latch based on the rising and falling edges of the comparator input signal. Compared with the original positive feedback regulation mechanism of the latch, the method of this invention is more direct and can complete the level decision more quickly without significantly increasing the power consumption and circuit complexity of the comparator. Attached Figure Description

[0018] Figure 1 This is the circuit schematic of a traditional high-speed voltage comparator. Figure 2 for Figure 1 Simulation diagram of the delay time of a high-speed voltage comparator with a power consumption of 122uA; Figure 3 This is a circuit diagram of a high-speed voltage comparator according to a preferred embodiment of the present invention; Figure 4 for Figure 3 Simulation diagram of the delay time of a high-speed voltage comparator with a power consumption of 100uA; Figure 5 This is a circuit diagram of a high-speed voltage comparator according to another preferred embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0020] The present invention aims to optimize the speed of existing high-speed voltage comparators without significantly increasing their power consumption and circuit complexity.

[0021] High-speed voltage comparators typically consist of a differential input amplifier stage, a latch stage, and an output buffer stage connected in sequence. The differential input amplifier stage pre-amplifies the differential voltage of the two input signals. The latch stage uses a positive feedback mechanism to quickly determine whether the pre-amplified signal is high or low by controlling its pull-up and pull-down devices, and then outputs the signal through the output buffer stage. The overall concept of this invention is to use an edge-fast response circuit to rapidly change the voltage at the control terminals of the pull-up and pull-down devices of the latch when it senses a transition from low to high or from high to low in the comparator input signal. This accelerates their switching process, eliminating their reliance on the original circuitous positive feedback mechanism of the latch to change the voltage at their control terminals, thus allowing the comparator to complete the level decision more quickly.

[0022] against Figure 1 The conventional high-speed voltage comparator shown in this embodiment has an optimized solution as follows: Figure 3 As shown.

[0023] Figure 3 The high-speed voltage comparator in the circuit can be roughly divided into five parts: bias circuit, differential input amplifier stage, latch stage, output buffer stage, and edge fast response circuit. Its main improvement lies in the addition of edge fast response circuit and bias circuit.

[0024] The bias circuit in this embodiment is configured as follows: it includes PMOS transistors P1~P7, NMOS transistors N1~N5, resistors R1~R2 and capacitor C1; The sources of PMOS transistors P1, P3, P5, and P6, and the upper plate of capacitor C1 are connected to the power supply terminal VDD; the gate of PMOS transistor P1 is connected to the lower plate of capacitor C1, the gate of PMOS transistor P3, the gate of PMOS transistor P6, the drain of PMOS transistor P2, and the positive terminal of resistor R1, and simultaneously serves as the output terminal of the bias circuit, outputting the bias voltage VBIAS1; the drain of PMOS transistor P1 is connected to the source of PMOS transistor P2; the gates of PMOS transistors P2, P4, and P7, and the negative terminal of resistor R1 are connected, and simultaneously serve as the input terminal IBIAS of the bias circuit; the drain of PMOS transistor P3 is connected to the source of PMOS transistor P4; the drain of PMOS transistor P4 is connected to the positive terminal of resistor R2, the gate of NMOS transistor N1, and N... The gate of MOSFET N3; the negative terminal of resistor R2 is connected to the drain of NMOS transistor N1, the gate of NMOS transistor N2, and the gate of NMOS transistor N4; the source of NMOS transistor N1 is connected to the drain of NMOS transistor N2; the gate of PMOS transistor P5 is connected to the drain of PMOS transistor P5 and the drain of NMOS transistor N3, and also serves as the output terminal of the bias circuit, outputting the bias voltage VBIAS2; the source of NMOS transistor N3 is connected to the drain of NMOS transistor N4; the drain of PMOS transistor P6 is connected to the source of PMOS transistor P7; the drain of PMOS transistor P7 is connected to the drain of NMOS transistor N5 and the gate of NMOS transistor N5, and also serves as the output terminal of the bias circuit, outputting the bias voltage VBIAS3; the sources of NMOS transistors N2, N4, and N5 are connected to ground GND.

[0025] In this embodiment, the bias circuit uses a low-dropout current mirror with a common-source, common-gate structure composed of PMOS transistors P1-P4 and resistor R1. This improves output impedance, enhances matching accuracy, and strengthens anti-interference capabilities. P6 and P7 form the current mirror branch, which replicates the current and provides voltage bias VBIAS3 to subsequent circuits through NMOS transistor N5 (connected as a diode). NMOS transistors N1-N4 and resistor R2 also form a low-dropout current mirror, replicating the current and providing voltage bias VBIAS2 to subsequent circuits through PMOS transistor P5 (connected as a diode). Capacitor C1 suppresses power supply noise coupling and improves the power supply rejection ratio.

[0026] The differential input amplifier stage structure in this embodiment is as follows: it includes PMOS transistors P8~P16, NMOS transistors N6~N9, resistors R3, R4, R6, R7 and resistor R5; The sources of PMOS transistors P8, P11, and P14 are connected to the power supply terminal VDD; the gates of PMOS transistors P8, P11, and P14 are connected to the bias voltage VBIAS1; the drain of PMOS transistor P8 is connected to the source of PMOS transistors P9 and P10; the gate of PMOS transistor P9 serves as one input terminal of the differential input amplifier stage, i.e., the high-speed voltage comparator, receiving the input signal VIN; the drain of PMOS transistor P9 is connected to the positive terminal of resistor R3 and the gate of PMOS transistor P12; the gate of PMOS transistor P10 serves as the other input terminal of the differential input amplifier stage, i.e., the high-speed voltage comparator, receiving the input signal VIP through resistor R5; the drain of PMOS transistor P10 is connected to the positive terminal of resistor R4 and the gate of PMOS transistor P13; the drain of PMOS transistor P11 is connected to the source of PMOS transistors P12 and P13; PMOS transistor P12... The drain of PMOS transistor P13 is connected to the positive terminal of resistor R6 and the gate of PMOS transistor P15; the drain of PMOS transistor P13 is connected to the positive terminal of resistor R7 and the gate of PMOS transistor P16; the drain of PMOS transistor P14 is connected to the source of PMOS transistors P15 and P16; the drain of PMOS transistor P15 is connected to the drain, gate, drain of NMOS transistor N6, drain of NMOS transistor N7 and gate of NMOS transistor N8, and also serves as one output terminal VCO2 of the differential input amplifier stage; the drain of PMOS transistor P16 is connected to the gate, drain of NMOS transistor N7, drain of NMOS transistor N8, gate of NMOS transistor N9 and drain of NMOS transistor N9, and also serves as another output terminal VCO3 of the differential input amplifier stage; the negative terminals of resistors R3 and R4, the negative terminals of resistors R6 and R7, and the sources of NMOS transistors N6 to N9 are connected to ground GND.

[0027] This embodiment employs a high-bandwidth, low-gain cascaded differential input amplifier stage, aiming to achieve higher bandwidth with lower single-stage gain, thereby improving overall response speed. PMOS transistors P8-P10 and resistors R3 and R4 constitute the first stage. The gates of PMOS transistors P10 and P11-P13, along with resistors R6 and R7, constitute the second stage. The first stage uses a PMOS differential amplifier structure with resistive loads, allowing its input common-mode range to approach the power supply voltage VDD, which is beneficial for low-voltage designs. While using resistors as loads sacrifices some gain, it avoids introducing nonlinearity and harmonic distortion into the transistors and simplifies the bias circuitry. The second stage also uses a PMOS differential amplifier structure with resistive loads, providing an extremely wide input common-mode range, particularly for high-voltage signal processing capabilities close to VDD. Resistive loads eliminate flicker noise (1 / f noise) across all processes, helping to avoid the impact of noise from the first stage on overall comparison accuracy. The use of the same structure for both stages facilitates layout matching. The third stage consists of PMOS transistors P14-P16 and NMOS transistors N6-N9. This third stage employs a high-gain active load PMOS differential amplifier structure. The high-gain active load includes two feedback paths: one is a cross-coupled positive feedback circuit composed of NMOS transistors N7-N8, and the other is a common-source negative feedback circuit composed of PMOS transistors P15-P16. When the transconductance of the negative feedback is greater than that of the positive feedback, the entire circuit exhibits negative feedback, achieving high output impedance, increasing the comparator gain, and improving comparison accuracy. When the gate voltage of P15 increases, according to the principle of common-source amplifier circuit, the drain voltage of P15 decreases, the gate voltage of N8 decreases, the drain voltage of N8 increases, and the drain voltage of P16 increases. Since the signals of P15 and P16 are opposite, the gate voltage of P16 decreases. According to the principle of common-source amplifier circuit, the drain voltage of P16 increases, so N7 plays a positive feedback role. Similarly, when the voltage of P16 increases, according to the principle of common-source amplifier circuit, the drain voltage of P16 decreases, the gate voltage of N7 decreases, the drain voltage of N7 increases, and the drain voltage of P15 increases. Since the signals of P15 and P16 are opposite, the gate voltage of P15 decreases, and the drain voltage of P15 also increases, so N8 also plays a positive feedback role.

[0028] The latch stage structure in this embodiment is as follows: including PMOS transistors P17, P18, and P20, and NMOS transistors N10 to N15; The sources of PMOS transistors P17, P18, and P20 are connected to the power supply terminal VDD; the gate of PMOS transistor P17 is connected to the bias voltage VBIAS1; the drain of PMOS transistor P17 is connected to the drain, gate, NMOS transistor N10, gate of NMOS transistor N12, and gate of NMOS transistor N14; the source of NMOS transistor N10 is connected to the drain and gate of NMOS transistor N11; the gate of PMOS transistor P18 is connected to the drain of PMOS transistor P18 and the NMOS transistor N14. The drain of transistor N12 and the gate of PMOS transistor P20 are connected; the source of NMOS transistor N12 is connected to the drain of NMOS transistor N13; the drain of PMOS transistor P20 is connected to the drain of NMOS transistor N14 and the input terminal of the output buffer stage; the gate of NMOS transistor N13 is connected to the output terminal VCO2, and the gate of NMOS transistor N15 is connected to the output terminal VCO3; the source of NMOS transistor N14 is connected to the drain of NMOS transistor N15; the sources of NMOS transistors N11, N13, and N15 are connected to ground GND.

[0029] The edge-fast response circuit structure in this embodiment is as follows: It includes a falling edge fast response circuit and a rising edge fast response circuit. The falling edge fast response circuit consists of capacitor C2, PMOS transistor P19, and resistor R8. The rising edge fast response circuit consists of capacitor C3, NMOS transistor P16, and resistor R9. The positive terminal of resistor R8 is connected to the bias voltage VBIAS2, and the negative terminal is connected to the gate of PMOS transistor P19 and the lower plate of capacitor C2. The upper plate of capacitor C2 is connected to the upper plate of capacitor C3 and also to the negative terminal of resistor R5. The lower plate of capacitor C3 is connected to the negative terminal of resistor R9 and the gate of NMOS transistor N16. The positive terminal of resistor R9 is connected to the bias voltage VBIAS3. The drain of PMOS transistor P19 is connected to the gate of NMOS transistor N15, and the source of PMOS transistor P19 is connected to the power supply terminal VDD. The drain of NMOS transistor N16 is connected to the gate of PMOS transistor P20, and the source of NMOS transistor N16 is connected to the ground terminal GND.

[0030] The latch utilizes its inherent positive feedback mechanism to control its pull-up device PMOS transistor P20 and pull-down device NMOS transistor N15 to quickly determine whether the pre-amplified signal is high or low. The process is as follows: like Figure 3As shown, when VIP gradually increases and VIN gradually decreases, due to the common-source differential pair formed by PMOS transistors P9~P10, the drain voltage of PMOS transistor P10 gradually decreases, while the drain voltage of PMOS transistor P9 gradually increases; due to the common-source differential pair formed by PMOS transistors P12~P13, the drain voltage of PMOS transistor P13 gradually increases, while the drain voltage of PMOS transistor P12 gradually decreases; due to the common-source differential pair formed by PMOS transistors P15~P16, the drain voltage of PMOS transistor P16 gradually decreases, while the drain voltage of PMOS transistor P15 gradually increases; according to the common-source characteristics of MOS transistors, the drain voltage of NMOS transistor N15 gradually increases, while the drain voltage of NMOS transistor N13 gradually decreases; according to the common-gate characteristics of MOS transistors, the drain voltage of NMOS transistor N14 gradually increases, while the drain voltage of NMOS transistor N12 gradually decreases; according to the common-source characteristics of MOS transistors, the drain voltage of PMOS transistor P20 gradually increases.

[0031] That is, when VIP > VIN, the drain of PMOS transistor P20 will gradually increase to the power supply voltage VDD. After passing through two cascaded inverters INV1 and INV2, VOUT will output a high level.

[0032] like Figure 3 As shown, when VIN gradually increases and VIP gradually decreases, since PMOS transistors P9-P10 form a common-source differential pair, the drain voltage of PMOS transistor P9 gradually decreases, while the drain voltage of PMOS transistor P10 gradually increases; since PMOS transistors P12-P13 form a common-source differential pair, the drain voltage of PMOS transistor P12 gradually increases, while the drain voltage of PMOS transistor P13 gradually decreases; since PMOS transistors P15-P16 form a common-source differential pair, the drain voltage of PMOS transistor P15 gradually decreases, while the drain voltage of PMOS transistor P16 gradually increases; according to the common-source characteristics of MOS transistors, the drain voltage of NMOS transistor N13 gradually increases, while the drain voltage of NMOS transistor N15 gradually decreases; according to the common-gate characteristics of MOS transistors, the drain voltage of NMOS transistor N12 gradually increases, while the drain voltage of NMOS transistor N14 gradually decreases; according to the common-source characteristics of MOS transistors, the drain voltage of PMOS transistor P20 gradually decreases.

[0033] That is, when VIN > VIP, the drain voltage of NMOS transistor N14 will gradually decrease to the ground voltage. After passing through two cascaded inverters INV1 and INV2, VOUT will output a low level.

[0034] With the addition of an edge-fast response circuit, the decision mechanism is optimized as follows: When VIP transitions from low to high, capacitor C3 is charged through resistor R5, causing the gate voltage of NMOS transistor N16 to increase rapidly. Due to the common-source characteristic of MOS transistors, the drain voltage of NMOS transistor N16 decreases rapidly, and the gate voltage of PMOS transistor P20 decreases rapidly. The drain of PMOS transistor P20 is quickly pulled high, accelerating the conduction process of P20, improving the comparator's response speed, and enabling the comparator to output a high level quickly. Here, resistor R5 and capacitor C3 also form a filter network, effectively filtering out high-frequency noise and glitches at the input, preventing the comparator from being falsely triggered due to noise interference.

[0035] When VIP transitions from high to low, the voltage across the upper plate of capacitor C2 drops sharply. Since capacitor voltage cannot change abruptly, the voltage across its lower plate will follow the same negative transition. According to the common-source characteristic of MOSFETs, the drain voltage of PMOS transistor P19 rises rapidly, and the drain of NMOS transistor N15 is quickly pulled low, accelerating the conduction process of N15, improving the comparator's response speed, and enabling the comparator to quickly output a low level. Here, resistor R5 and capacitor C2 also form a filter network.

[0036] In conclusion, Figure 3 The proposed solution not only further optimizes... Figure 1 The speed of the high-speed voltage comparator shown is improved, and its decision accuracy is also improved to a certain extent.

[0037] Figure 4 for Figure 3 The simulation diagram shows the delay time of the high-speed voltage comparator in the illustrated embodiment at a power consumption of 100µA. As can be seen from the figure, at a power consumption of 100µA, its rise time delay is 4.6ns and its fall time delay is 3.9ns. Compared to... Figure 2 The comparator has a rise time of 10.2ns and a fall time of 9.3ns at a power consumption of 122uA. This demonstrates that the proposed solution is effective in improving the speed of high-speed voltage comparators, and its efficiency is comparable to... Figure 2 The number of plans did not increase significantly, and even decreased slightly.

[0038] It should be noted that the edge-fast response circuit in this embodiment is versatile in improving the decision speed of the latch and is not limited to this. Figure 2 The latch structure shown is less affected by Figure 2 The differential input amplifier stage shown has limitations.

[0039] Those skilled in the art, after understanding the concept of the present invention, will realize that the edge-fast response circuit of the present invention is not limited to... Figure 3The structure and connection method shown are not limited to this capacitor and semiconductor transistor structure. For example, the edge fast response circuit is not limited to acquiring VIP, but can also acquire VIN, or acquire bilateral signals. Of course, the connection method of its rising and falling edge fast response circuit also needs to be adjusted accordingly, which is within the scope of the expectations of those skilled in the art.

[0040] Figure 5 This is a circuit schematic diagram of a high-speed voltage comparator according to another preferred embodiment of the present invention, which is related to... Figure 3 The main difference between medium- and high-speed voltage comparators lies in the structure of their differential input amplifier stages. For example... Figure 5 As shown, in this embodiment, a current mirror composed of NMOS transistors N6 and N7 is used as the load for the differential input pair PMOS transistors P9 and P10.

[0041] For those skilled in the art, various improvements and modifications can be made without departing from the spirit and scope of the present invention. These improvements and modifications should also be considered within the scope of protection of the present invention. Further details will not be provided here, and the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A high speed voltage comparator comprising a differential input amplification stage, a latch stage and an output buffer stage, said differential input amplification stage pre-amplifying a differential voltage of two input signals, said latch stage comprising a pull-up device and a pull-down device, which receive the pre-amplified signals and output as a high or low level through said pull-up device and pull-down device, and then output through said output buffer stage, characterized in that, The high-speed voltage comparator further comprises an edge fast response circuit, an input end of which is connected with the input of the differential input amplification stage, and an output end of which is connected with the control end of the pull-up device and the pull-down device, when the input signal jumps from low level to high level or from high level to low level, the edge fast response circuit controls the voltage of the control end of the pull-up device and the pull-down device to change rapidly, and accelerates the switching process of the pull-up device and the pull-down device. ​ 2. The high-speed voltage comparator of claim 1, wherein, The edge fast response circuit comprises a rising edge fast response circuit and a falling edge fast response circuit, both of which are composed of a capacitor and a semiconductor triode, one end of the capacitor is connected with the control end of the semiconductor triode, the other end is connected with the input of the differential input amplification stage, and the output end of the semiconductor triode is connected with the control end of the pull-up device or the pull-down device.

3. The high-speed voltage comparator of claim 2, wherein, The input ends of the rising edge fast response circuit and the falling edge fast response circuit are connected in parallel.

4. The high-speed voltage comparator of claim 3, wherein, The input signal is connected with the input end of the differential input amplification stage through a resistor R5, and the input ends of the rising edge fast response circuit and the falling edge fast response circuit are connected with the negative pole of the resistor R5.

5. The high-speed voltage comparator of claim 1, wherein, The high-speed voltage comparator further comprises a bias circuit, the bias circuit comprises PMOS tubes P1, P2, P3, P4, P5, P6, P7, NMOS tubes N1, N2, N3, N4, N5, resistors R1 and R2, and a capacitor C1. The source of PMOS tube P1, PMOS tube P3, PMOS tube P5, PMOS tube P6 and the upper plate of capacitor C1 are connected to power terminal VDD; the gate of PMOS tube P1 is connected to the lower plate of capacitor C1, the gate of PMOS tube P3, the gate of PMOS tube P6, the drain of PMOS tube P2 and the positive pole of resistor R1, and simultaneously outputs bias voltage VBIAS1 as the output terminal of the bias circuit; the drain of PMOS tube P1 is connected to the source of PMOS tube P2; the gate of PMOS tube P2, the gate of PMOS tube P4, the gate of PMOS tube P7 and the negative pole of resistor R1 are connected, and simultaneously, IBIAS is the input terminal of the bias circuit; the drain of PMOS tube P3 is connected to the source of PMOS tube P4; the drain of PMOS tube P4 is connected to the positive pole of resistor R2, the gate of NMOS tube N1 and the gate of NMOS tube N3; the negative pole of resistor R2 is connected to the drain of NMOS tube N1, the gate of NMOS tube N2 and the gate of NMOS tube N4; the source of NMOS tube N1 is connected to the drain of NMOS tube N2; the gate of PMOS tube P5 is connected to the drain of PMOS tube P5 and the drain of NMOS tube N3, and simultaneously, VBIAS2 is output as the output terminal of the bias circuit; the source of NMOS tube N3 is connected to the drain of NMOS tube N4; the drain of PMOS tube P6 is connected to the source of PMOS tube P7; the drain of PMOS tube P7 is connected to the drain of NMOS tube N5 and the gate of NMOS tube N5, and simultaneously, VBIAS3 is output as the output terminal of the bias circuit; the sources of NMOS tube N2, NMOS tube N4 and NMOS tube N5 are connected to ground terminal GND.

6. The high-speed voltage comparator of claim 1, wherein, The differential input amplification stage adopts a high-bandwidth low-gain cascade structure.

7. The high-speed voltage comparator of claim 6, wherein, The differential input amplification stage adopts a PMOS differential amplification structure with more than one PMOS tube with resistance load and a PMOS differential amplification structure with more than one PMOS tube with source load for cascade.

8. The high-speed voltage comparator of claim 7, wherein, The differential input amplification stage comprises PMOS tube P8, PMOS tube P9, PMOS tube P10, PMOS tube P11, PMOS tube P12, PMOS tube P13, PMOS tube P14, PMOS tube P15, PMOS tube P16, NMOS tube N6, NMOS tube N7, NMOS tube N8, NMOS tube N9, resistor R3, resistor R4, resistor R6, resistor R7 and resistor R5. The sources of PMOS transistors P8, P11, and P14 are connected to the power supply terminal VDD; the gates of PMOS transistors P8, P11, and P14 are connected to the bias voltage VBIAS1; the drain of PMOS transistor P8 is connected to the source of PMOS transistors P9 and P10; the gate of PMOS transistor P9 serves as one input terminal of the differential input amplifier stage, i.e., the high-speed voltage comparator, receiving the input signal VIN; the drain of PMOS transistor P9 is connected to the positive terminal of resistor R3 and the gate of PMOS transistor P12; the gate of PMOS transistor P10 serves as the other input terminal of the differential input amplifier stage, i.e., the high-speed voltage comparator, receiving the input signal VIP through resistor R5; the drain of PMOS transistor P10 is connected to the positive terminal of resistor R4 and the gate of PMOS transistor P13; the drain of PMOS transistor P11 is connected to the source of PMOS transistors P12 and P13; PMOS transistor P12... The drain of PMOS transistor P13 is connected to the positive terminal of resistor R6 and the gate of PMOS transistor P15; the drain of PMOS transistor P13 is connected to the positive terminal of resistor R7 and the gate of PMOS transistor P16; the drain of PMOS transistor P14 is connected to the source of PMOS transistors P15 and P16; the drain of PMOS transistor P15 is connected to the drain and gate of NMOS transistor N6, the drain of NMOS transistor N7, and the gate of NMOS transistor N8, and simultaneously serves as the differential input amplifier. One output terminal of the large-scale stage is VCO2; the drain of PMOS transistor P16 is connected to the gate of NMOS transistor N7, the drain of NMOS transistor N8, the gate of NMOS transistor N9, and the drain of NMOS transistor N9. Simultaneously, VCO3 serves as another output terminal of the differential input amplifier stage; the negative terminals of resistors R3, R4, R6, and R7, and the sources of NMOS transistors N6, N7, N8, and N9 are connected to ground GND. PMOS transistors P8, PMOS transistors P9, PMOS transistors P10, resistors R3 and R4 constitute the first-stage PMOS transistor differential amplifier structure, and PMOS transistors P11, PMOS transistors P12, PMOS transistors P13, resistors R6 and R7 constitute the second-stage PMOS transistor differential amplifier structure. The two stages are identical. PMOS transistors P14, P15, P16, NMOS transistors N6, NMOS transistors N7, NMOS transistors N8, and NMOS transistors N9 constitute the third-stage PMOS differential amplifier structure, which includes two feedback paths: one is a cross-coupled positive feedback composed of NMOS transistors N7 and NMOS transistors N8, and the other is a common-source negative feedback composed of PMOS transistors P15 and P16, with the transconductance of the negative feedback being greater than that of the positive feedback.

9. The high-speed voltage comparator of claim 1, wherein, The latch stage includes PMOS transistors P17, PMOS transistor P18, PMOS transistor P20, NMOS transistor N10, NMOS transistor N11, NMOS transistor N12, NMOS transistor N13, NMOS transistor N14, and NMOS transistor N15; The sources of PMOS transistors P17, P18, and P20 are connected to the power supply terminal VDD; the gate of PMOS transistor P17 is connected to the bias voltage VBIAS1; the drain of PMOS transistor P17 is connected to the drain, gate, NMOS transistor N12, and gate of NMOS transistor N14; the source of NMOS transistor N10 is connected to the drain and gate of NMOS transistor N11; the gate of PMOS transistor P18 is connected to the drain of PMOS transistor P18, the drain of NMOS transistor N12, and PM... The gate of PMOS transistor P20 is connected to the gate of NMOS transistor N12; the source of NMOS transistor N12 is connected to the drain of NMOS transistor N13; the drain of PMOS transistor P20 is connected to the drain of NMOS transistor N14 and the input terminal of the output buffer stage; the gate of NMOS transistor N13 is connected to one output terminal VCO2 of the differential input amplifier stage, and the gate of NMOS transistor N15 is connected to the other output terminal VCO3 of the differential input amplifier stage; the source of NMOS transistor N14 is connected to the drain of NMOS transistor N15; the sources of NMOS transistors N11, NMOS transistor N13, and NMOS transistor N15 are connected to ground GND.

10. The high-speed voltage comparator of claim 9, wherein, The falling edge fast response circuit includes capacitor C2, PMOS transistor P19 and resistor R8; The rising edge fast response circuit includes capacitor C3, NMOS transistor N16 and resistor R9; The positive terminal of resistor R8 is connected to the bias voltage VBIAS2, and the negative terminal is connected to the gate of PMOS transistor P19 and the lower plate of capacitor C2. The upper plate of capacitor C2 is connected to the upper plate of capacitor C3 and is also connected to the inverting input of the differential input amplifier stage. The lower plate of capacitor C3 is connected to the negative terminal of resistor R9 and the gate of NMOS transistor N16. The positive terminal of resistor R9 is connected to the bias voltage VBIAS3. The drain of PMOS transistor P19 is connected to the gate of NMOS transistor N15. The source of PMOS transistor P19 is connected to the power supply terminal VDD. The drain of NMOS transistor N16 is connected to the gate of PMOS transistor P20. The source of NMOS transistor N16 is connected to the ground terminal GND.

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