Digital-to-analog converter

Abstract

A digital-to-analog converter includes multiple current conversion units, a current compensation unit, and a first amplifier. Each current conversion unit includes a first differential switch pair, a first stacked transistor, and a first current source transistor. The first differential switch pair is controlled by a first control signal and a first inverting control signal. The first stacked transistor and the first current source transistor are connected in series and coupled to the first differential switch pair. The current compensation unit includes a second stacked transistor. The input terminal of the first amplifier is coupled to the source of the second stacked transistor, and the output terminal of the first amplifier is coupled to the gate of the second stacked transistor and the gate of the first stacked transistor. This increases the output impedance.

Description

Technical Field

[0001] This disclosure relates to a digital-to-analog converter, and more particularly to a digital-to-analog converter with a compensation current unit. Background Technology

[0002] A digital-to-analog converter (DAC) is a device that converts digital signals into analog signals so that the digital signals can be recognized by external devices. In this digital age, DACs are an indispensable component of various electronic devices. However, DACs are affected by the varying equivalent output impedance at their output terminals, which can lead to poor linearity. Summary of the Invention

[0003] This disclosed embodiment is a digital-to-analog converter (DTC). The DTC includes multiple current conversion units, a current compensation unit, a first amplifier circuit, and a current source circuit. Each current conversion unit includes a first differential switch pair, a first stacked transistor, and a first current source transistor. The first differential switch pair is controlled by a first control signal and a first inverting control signal. The first stacked transistor and the first current source transistor are connected in series and coupled to the first differential switch pair. The current compensation unit includes a second differential switch pair, a second stacked transistor, and a second current source transistor. The second differential switch pair is controlled by a second control signal. The second stacked transistor and the second current source transistor are connected in series and coupled to the second differential switch pair, wherein the gate of the second current source transistor is coupled to the gate of the first current source transistor. An input terminal of the first amplifier circuit is coupled to the source of the second stacked transistor, and an output terminal of the first amplifier circuit is coupled to each of the gates of the second stacked transistor and the gate of the first stacked transistor. The current source circuit is coupled to the second current source transistor to form a current mirror and is also coupled to the first current source transistor to form a current mirror.

[0004] In some embodiments, the first amplifier circuit includes: an operational amplifier, wherein an inverting input of the operational amplifier is coupled to the source of a second cascaded transistor, a non-inverting input of the operational amplifier is coupled to a bias signal, and an output of the operational amplifier is coupled to the gate of the second cascaded transistor and the gate of the first cascaded transistor.

[0005] In some embodiments, the first amplifier circuit includes: a first transistor, the drain of which is coupled to each of the gate of a second cascaded transistor and the gate of the first cascaded transistor, and the gate of the first transistor is coupled to the source of the second cascaded transistor; and a first current source coupled to the drain of the first transistor.

[0006] In some embodiments, the first differential switch pair includes: a first switch, a first end of which is coupled to a first output terminal and a second end of which is coupled to a first stacked transistor at a first node; and a second switch, a first end of which is coupled to a second output terminal and a second end of which is coupled to the first node.

[0007] In some embodiments, the second differential switch pair includes: a third switch controlled by a second control signal, a first terminal of the third switch coupled to a first output terminal, and a second terminal of the third switch coupled to a second stacked transistor at a second node; and a fourth switch controlled by a second reverse control signal and coupled to the second node, wherein the second control signal and the second reverse control signal remain unchanged.

[0008] In some embodiments, the digital-to-analog converter further includes an operational amplifier and an output resistor. An inverting input of the operational amplifier is coupled to a first output, a non-inverting input of the operational amplifier is coupled to a ground terminal, and the output resistor is coupled between the first output and an output of the operational amplifier.

[0009] In some embodiments, the digital-to-analog converter further includes a load resistor, which includes a first resistor coupled to a first output terminal.

[0010] In some embodiments, the load resistor further includes a second resistor coupled to the second output terminal.

[0011] In some embodiments, the first current source transistor is coupled to a ground terminal.

[0012] In some embodiments, the first current source transistor is used to receive a power supply voltage. Attached Figure Description

[0013] A fuller understanding of this disclosure can be obtained by referring to the following detailed description of the embodiments in conjunction with the accompanying drawings:

[0014] Figure 1A This is a circuit diagram of a digital-to-analog converter according to some embodiments of the present disclosure;

[0015] Figure 1B This is a circuit diagram of a digital-to-analog converter according to some embodiments of the present disclosure;

[0016] Figure 1C This is a circuit diagram of a portion of a digital-to-analog converter in a single-sided output architecture according to some embodiments of the present disclosure;

[0017] Figure 2A A circuit diagram of a digital-to-analog converter according to some embodiments of this disclosure; and

[0018] Figure 2B This is a circuit diagram of a digital-to-analog converter according to some embodiments of the present disclosure.

[0019] [Symbol Explanation]

[0020] 100A~100B: Digital-to-Analog Converter

[0021] 110: Current Conversion Unit

[0022] 111, 121: Differential switch pair

[0023] 120: Compensation Current Unit

[0024] 130: Pre-processing unit

[0025] 140: Current source circuit

[0026] 150: Digital Controller

[0027] Qj, B: Control signals

[0028] Reverse control signal

[0029] M3, M7: Stacked transistors

[0030] M4, M8: Current source transistors

[0031] M1, M2, M5, M6: Switches

[0032] M13: Transistor

[0033] Vb: Bias signal

[0034] 131: Amplifier Circuit

[0035] 131C: Operational Amplifier

[0036] Vsh: Voltage signal

[0037] DS: Digital signal

[0038] 141. IS: Current Source

[0039] 142: Gate bias circuit

[0040] 200A~200B: Digital-to-Analog Converter

[0041] n1, n2: Output terminals

[0042] n3~n6: Nodes

[0043] L1: Adjustment loop

[0044] VDD: Power supply voltage

[0045] RF: Output resistance Detailed Implementation

[0046] The following is a detailed description of the embodiments in conjunction with the accompanying drawings. However, the specific embodiments described are only for explaining this case and are not intended to limit this case. The description of the structural operations is not intended to limit the order of their execution. Any structure that is recombined with elements and produces a device with equivalent function is within the scope of this disclosure.

[0047] Unless otherwise specified, the terms used throughout the specification and claims generally have their ordinary meaning in the context of the art, the content disclosed herein, and the specific content.

[0048] The terms "coupled" or "connected" as used in this article can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or to two or more components operating or moving together.

[0049] Please refer to Figure 1A , Figure 1A This is a circuit diagram of a digital-to-analog converter 100A according to some embodiments of the present disclosure. Figure 1A As shown, the digital-to-analog converter 100A includes multiple current conversion units 110, current compensation units 120, amplifier circuits 131, preprocessing devices 130, digital controllers 150, and current source circuits 140.

[0050] In some embodiments, the digital controller 150 is used to generate a digital signal DS. The preprocessing unit 130 is used to convert the digital signal DS into a plurality of control signals Qj and a plurality of inverse control signals. In some embodiments, the control signal Qj and the reverse control signal This is referred to as a differential signal pair. Multiple current conversion units 110 and compensation current units 120 are coupled to each other at the output terminal n1, wherein the multiple current conversion units 110 are configured according to the control signal Qj and the inverted control signal... The corresponding analog signal is generated. The compensation current unit 120 is used to further compensate and adjust the analog signals output by the multiple conversion current units 110. The amplifier circuit 131, coupled to the multiple conversion current units 110 and the compensation current unit 120, provides gain boosting to increase the output impedance of the multiple conversion current units 110. The current source circuit 140, coupled to the multiple conversion current units 110 and the compensation current unit 120, provides the current required for the operation of the multiple conversion current units 110 and the compensation current unit 120.

[0051] refer to Figure 1AEach of the multiple current conversion units 110 includes a differential switch pair 111, a stacked transistor M3, and a current source transistor M4. For simplicity, Figure 1A Only a detailed configuration of a single current conversion unit 110 is shown. It should be understood that, unless otherwise specified, the configuration of the single current conversion unit 110 described below is applicable to each of a plurality of current conversion units 110. The differential switch pair 111 includes switches M1 and M2, which are controlled by a control signal Qj and a reverse control signal, respectively. In detail, switch M1 is controlled by control signal Qj and reverse control signal. One of them, switch M2 is controlled by control signal Qj and reverse control signal. The other one.

[0052] In addition, the control signal Qj and the reverse control signal This is related to the digital signal DS. In other words, the digital signal DS is converted into a control signal Qj and an inverse control signal by the pre-processing device 130. The digital-to-analog converter 100A then uses the control signal Qj and the inverted control signal... To generate analog signals. Due to the control signal Qj and the inverse control signal They are opposite to each other; when one of switches M1 and M2 is turned on, the other of switches M1 and M2 is turned off.

[0053] In some embodiments, the control signal Qj and the reverse control signal In this context, j can represent multiple positive integers, and the multiple current conversion units 110 respectively receive the corresponding control signal Qj and the reverse control signal. For example, switches M1 and M2 in the first current conversion unit 110 are controlled by control signal Q1 and reverse control signal. The switches M1 and M2 in the second current conversion unit 110 are controlled by the control signal Q2 and the reverse control signal. And so on. Switches M1 and M2 in the j-th current conversion unit 110 are controlled by the control signal Qj and the reverse control signal.

[0054] like Figure 1AAs shown, in the current conversion unit 110, switch M1 is coupled between output terminal n1 and node n3, and switch M2 is coupled between output terminal n2 and node n3. A stacked transistor M3 and a current source transistor M4 are connected in series between nodes n3 and n4. Switches M1, M2, M3, and M4 are illustrated using NMOS transistors as an example. Specifically, the sources of switches M1 and M2 are coupled at node n3, the drain of switch M1 is coupled to output terminal n1, and the drain of switch M2 is coupled to output terminal n2. The source of the stacked transistor M3 is coupled to the drain of the current source transistor M4. The drain of the stacked transistor M3 is coupled to node n3, and the source of the current source transistor M4 is coupled to node n4. In some embodiments, node n4 is a ground terminal.

[0055] Reference Figure 1A Similar to the current conversion unit 110, the current compensation unit 120 includes a differential switch pair 121, a stacked transistor M7, and a current source transistor M8. The differential switch pair 121 is controlled by a control signal B.

[0056] Specifically, the differential switch pair 121 includes switches M5 and M6. Switch M5 is controlled by control signal B. In some embodiments, switch M6 may be controlled by a reverse control signal. Inverted control signal It is the opposite of control signal B.

[0057] In some embodiments, control signal B and reverse control signal It is a fixed differential signal pair. Compared to the control signal Qj and reverse control signal received by the current conversion unit 110. Control signal B and reverse control signal It remains unchanged, and the control signal Qj and the reverse control signal It changes accordingly based on the digital signal DS.

[0058] In other words, in some embodiments, switch M5 remains on while switch M6 remains off. In some variations, switch M5 is controlled by a control signal. Switch M6 is controlled by control signal B. In other words, switch M5 remains off while switch M6 remains on.

[0059] like Figure 1AIn the current compensation unit 120, switch M5 is coupled between output terminal n1 and node n5, and switch M6 is coupled between output terminal n2 and node n5. Stacked transistor M7 and current source transistor M8 are connected in series between node n5 and node n4. Switches M5, M6, stacked transistor M7, and current source transistor M8 are illustrated using NMOS transistors as an example. Specifically, the sources of switch M5 and M6 are coupled at node n5, the drain of switch M5 is coupled to output terminal n1, and the drain of switch M6 is coupled to output terminal n2. The source of stacked transistor M7 is coupled to the drain of current source transistor M8. The drain of stacked transistor M7 is coupled to node n5, and the source of current source transistor M8 is coupled to node n4.

[0060] Reference Figure 1A Amplifier circuit 131 is coupled between the gate and source of the stacked transistor M7. Specifically, amplifier circuit 131 may include an operational amplifier OPA, wherein the inverting input of operational amplifier OPA is coupled to the source of the stacked transistor M7, the non-inverting input of operational amplifier OPA is coupled to a bias signal Vb, and the output of operational amplifier OPA is coupled to the gate of the stacked transistor M7. Figure 1A In this configuration, the inverting input is represented by the symbol -, and the non-inverting input is represented by the symbol +. Under this configuration, a regulated loop L1 is formed between the gate and source of the stacked transistor M7.

[0061] Furthermore, the gate of the stacked transistor M7 is further coupled to the gate of the stacked transistor M3 in each of the plurality of current conversion units 110. Correspondingly, the amplifier circuit 131 can provide a voltage signal Vsh to the gates of the stacked transistor M3 and the stacked transistor M7. Here, for the sake of simplicity, Figure 1A Only the connection between the stacked transistor M7 and a single current conversion unit 110 is shown; however, it should be understood that the other current conversion units 110 are also coupled to the stacked transistor M7 in the same way. In this configuration, the output of the amplifier circuit 131 is coupled to the gate of the stacked transistor M7, and then coupled via the gate of the stacked transistor M7 to the gate of the stacked transistor M3 of each of the plurality of current conversion units 110. Thus, the amplifier circuit 131 can increase the total impedance of the stacked transistor M3 and the current source transistor M4, and the total impedance of the stacked transistor M7 and the current source transistor M8, respectively, by providing gain, thereby correspondingly increasing the output impedance of the current conversion unit 110 and the compensation current unit 120.

[0062] Reference Figure 1AIn some embodiments, the gate of the current source transistor M8 is further coupled to the gate of the current source transistor M4 of each of the plurality of current conversion units 110. For the sake of brevity, Figure 1A Only the connection between the current source transistor M8 and the single current conversion unit 110 is shown, but it should be understood that other current conversion units 110 are also coupled to the current source transistor M8 in the same way.

[0063] like Figure 1A As shown, the current source circuit 140 is coupled to the current source transistor M8 to form a current mirror. Thus, the current source transistor M8 can be turned on according to the current source circuit 140 to generate a mirror current. Simultaneously, the current source circuit 140 is also coupled to each of the current source transistors M4 in the plurality of current conversion units 110 to form a current mirror. Thus, each current source transistor M4 is turned on according to the current source circuit 140 to generate a mirror current.

[0064] In some embodiments, the current source circuit 140 may include a current source 141 and a gate bias circuit 142. One end of the current source 141 is used to receive the power supply voltage VDD, and the other end of the current source 141 is coupled to the gate bias circuit 142. The gate bias circuit 142 is coupled to ground and is used to provide a gate bias to the gates of the current source transistors M4 and M8.

[0065] In some embodiments, the gate bias circuit 142 can be implemented using a transistor (not shown). The gate of this transistor is coupled to the gates of current source transistors M4 and M8. The drain of this transistor is coupled to its gate and the current source 141. The source of this transistor is coupled to ground.

[0066] In various embodiments, the digital-to-analog converter 100A can output analog signals from output terminals n1 and n2 in various ways. For example, the digital-to-analog converter 100A can be implemented using a single-sided output architecture. Figure 1C This is a circuit diagram of a portion of a digital-to-analog converter in a single-sided output architecture according to some embodiments of this disclosure. Figure 1C As shown, in the single-sided output architecture, the digital-to-analog converter 100A also includes an operational amplifier 131C and an output resistor RF. The inverting input of the operational amplifier 131C is coupled to the output terminal n1. The non-inverting input of the operational amplifier 131C is coupled to ground. The output resistor RF is coupled between the output terminal n1 and the output terminal of the operational amplifier 131C.

[0067] In the above example, multiple current conversion units 110 are used to generate multiple output currents I1 flowing through switch M1 and multiple currents I2 flowing through switch M2. The sum of the output currents I1 is determined by the number of switches M1 that are turned on and the number of switches M5 that remain on. The sum of the currents I2 is determined by the number of switches M2 that are turned on and the number of switches M6 that remain on. In this way, the digital-to-analog converter 100A can generate an output voltage, wherein the output voltage is equal to the sum of the output currents I1 multiplied by the output resistance RF.

[0068] As another example, the digital-to-analog converter 100A can be implemented using a dual-output architecture. In this architecture, the digital-to-analog converter 100A may also include a load resistor (not shown). The load resistor may include resistors R1 and R2 (not shown). Specifically, resistor R1 is coupled to a plurality of current conversion units 110 at output terminal n1, while resistor R2 is coupled to a plurality of current conversion units 110 at output terminal n2. In some embodiments, resistors R1 and R2 have the same resistance value. Furthermore, in another embodiment, the load resistor may consist only of resistor R1, in which case resistor R1 is coupled to output terminal n1, while output terminal n2 is grounded.

[0069] In the above example, multiple current conversion units 110 are used to generate multiple output currents I1 flowing through switch M1 and multiple output currents I2 flowing through switch M2. The sum of the output currents I1 is determined by the number of switches M1 that are turned on and the number of switches M5 that are kept on. The sum of the output currents I2 is determined by the number of switches M2 that are turned on and the number of switches M6 that are turned on. The sum of the output currents I1 and I2 flows through resistors R1 and R2 respectively to generate an output voltage difference at output terminals n1 and n2.

[0070] Please refer to Figure 1B . Figure 1B This is a circuit diagram of a digital-to-analog converter 100B according to some embodiments of the present disclosure. Compared to Figure 1A The main difference between the digital-to-analog converter 100A and the digital-to-analog converter 100B is that the amplifier circuit 131 includes a transistor M13 and a current source IS. The transistor M13, switches M1-M2, switches M5-M6, stacked transistors M3 and M7, current source transistors M4 and M8 are illustrated using NMOS transistors as an example. Specifically, the drain of transistor M13 is coupled to the current source IS and the gate of the stacked transistor M7. The gate of transistor M13 is coupled to the source of the stacked transistor M7. Thus, the amplifier circuit 131 can increase the total impedance of the stacked transistor M3 and the current source transistor M4, and the total impedance of the stacked transistor M7 and the current source transistor M8, respectively, by providing gain, thereby correspondingly increasing the output impedance of the conversion current unit 110 and the compensation current unit 120.

[0071] Please refer to Figure 2A . Figure 2A This is a circuit diagram of a digital-to-analog converter 200A according to some embodiments of this disclosure. Please refer to... Figure 1A and Figure 2A The digital-to-analog converter 200A is a variation of the digital-to-analog converter 100A. The components of the digital-to-analog converter 200A use the same numbering system as the digital-to-analog converter 100A. For the sake of brevity, the discussion will focus on the parts of the digital-to-analog converter 200A that differ from, rather than those that are the same as, the digital-to-analog converter 100A.

[0072] exist Figure 2A In the corresponding embodiment, the source of current source transistor M4 and the source of current source transistor M8 are coupled to the power supply voltage VDD at node n6. The drain of switch M2 and the drain of switch M6 are coupled to ground at the output terminal n2. Switches M1-M2, switches M5-M6, stacked transistors M3 and M7, current source transistors M4 and M8 are illustrated using PMOS transistors as an example.

[0073] Please refer to Figure 2B . Figure 2B This is a circuit diagram of a digital-to-analog converter 200B according to some embodiments of the present disclosure. Compared to Figure 2A The main difference between the digital-to-analog converter 200A and the digital-to-analog converter 200B is that the amplifier circuit 131 includes transistor M13 and current source IS. The transistors M13, switches M1-M2, switches M5-M6, stacked transistors M3 and M7, current source transistors M4 and M8 are illustrated using PMOS transistors as an example. Specifically, the drain of transistor M13 is coupled to the current source IS and the gate of stacked transistor M7. The gate of transistor M13 is coupled to the source of stacked transistor M7. Thus, the amplifier circuit 131 can increase the total impedance of stacked transistor M3 and current source transistor M4, and the total impedance of stacked transistor M7 and current source transistor M8, respectively, by providing gain, thereby correspondingly increasing the output impedance of the conversion current unit 110 and the compensation current unit 120.

[0074] exist Figure 2B In the illustrated embodiment, one end of the current source 141 is coupled to the ground terminal, and the other end of the current source 141 is coupled to the gate bias circuit 142. The gate bias circuit 142 is used to receive the power supply voltage VDD and provide gate bias to the gates of the current source transistors M4 and M8.

[0075] In summary, the technical means disclosed herein can improve the output impedance of a digital-to-analog converter at a lower cost and may also help improve the linearity of the digital-to-analog converter.

[0076] Although this disclosure has been presented above with reference to embodiments, it is not intended to limit this disclosure. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. A digital-to-analog converter, characterized by, Comprising: a plurality of conversion current cells, each of the plurality of conversion current cells comprising: a first differential pair of switches controlled by a first control signal and a first inverse control signal; and a first cascode transistor and a first current source transistor coupled in series with each other and with the first differential pair of switches; a compensation current cell comprising: a second differential pair of switches controlled by a second control signal; and a second cascode transistor and a second current source transistor coupled in series with each other and with the second differential pair of switches, wherein a gate of the second current source transistor is coupled to a gate of the first current source transistor; a first amplifier circuit, an input of the first amplifier circuit coupled to a source of the second cascode transistor, an output of the first amplifier circuit coupled to each of a gate of the second cascode transistor and a gate of the first cascode transistor; and a current source circuit coupled to the second current source transistor to form a current mirror and coupled to the first current source transistor to form a current mirror. wherein the first amplifier circuit comprises:

2. The digital analog converter of claim 1, wherein, an operational amplifier, wherein an inverting input of the operational amplifier is coupled to the source of the second cascode transistor, a non-inverting input of the operational amplifier is coupled to a bias signal, and an output of the operational amplifier is coupled to each of the gate of the second cascode transistor and the gate of the first cascode transistor. wherein the first amplifier circuit comprises:

3. The digital-to-analog converter of claim 1, wherein, a first transistor, a drain of the first transistor coupled to each of the gate of the second cascode transistor and the gate of the first cascode transistor, and a gate of the first transistor coupled to the source of the second cascode transistor; and a first current source coupled to the drain of the first transistor. wherein the first differential pair of switches comprises:

4. The digital-to-analog converter of claim 1, wherein, a first switch, a first terminal of the first switch coupled to a first output, and a second terminal of the first switch coupled to the first cascode transistor at a first node; and a second switch, a first terminal of the second switch coupled to a second output, and a second terminal of the second switch coupled to the first node. wherein the second differential pair of switches comprises: a third switch controlled by the second control signal, a first terminal of the third switch coupled to the first output, and a second terminal of the third switch coupled to the second cascode transistor at a second node; and 5. The digital-to-analog converter of claim 4, wherein, a fourth switch controlled by a second inverse control signal and coupled to the second node, wherein the second control signal and the second inverse control signal are held constant. further comprising: an operational amplifier; and an output resistor; 6. The digital-to-analog converter of claim 4, wherein, wherein an inverting input of the operational amplifier is coupled to the first output, a non-inverting input of the operational amplifier is coupled to a ground, and the output resistor is coupled between the first output and an output of the operational amplifier. further comprising a load resistor, the load resistor comprising: a first resistor coupled to the first output. wherein the load resistor further comprises:

7. The digital-to-analog converter of claim 4, wherein, a second resistor coupled to the second output. wherein the first current source transistor is coupled to a ground.

8. The digital-to-analog converter of claim 7, wherein, wherein the first current source transistor is configured to receive a supply voltage. ​ 9. The digital-to-analog converter of claim 1, wherein, ​ 10. The digital-to-analog converter of claim 1, wherein, ​

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