Tunneling oxide passivated contact structure and its preparation method, solar cells

Abstract

This application relates to a tunneling oxide passivation contact structure and its fabrication method, as well as a solar cell. The tunneling oxide passivation contact structure includes a first tunneling oxide passivation contact structure and at least one second tunneling oxide passivation contact structure stacked on the surface of the first tunneling oxide passivation contact structure. The first tunneling oxide passivation contact structure includes a first tunneling oxide layer and a first doped polycrystalline silicon layer stacked together. The second tunneling oxide passivation contact structure includes a second tunneling oxide layer and a second doped polycrystalline silicon layer stacked together. The second tunneling oxide layer includes doped polycrystalline silicon particles, and doped atoms are enriched in the doped polycrystalline silicon particles. The tunneling oxide passivation contact structure described in this application can promote carrier collection and reduce the carrier transport resistance in the tunneling layer, thereby significantly increasing the current.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a tunneling oxide passivated contact structure, its preparation method, and a solar cell. Background Technology

[0002] Photovoltaic technology is a technology that directly converts solar energy into electrical energy using solar cells. The core component of photovoltaics is the solar cell, among which the TBC (Tunnel Oxide Passivated Back Contact) cell is an important type, combining the designs of TOPCon (Tunnel Oxide Passivated Back Contact) and IBC (Interdigitated Back Contact) solar cells. The main characteristics of TBC cells are their highly efficient tunneling passivation structure and the absence of grid lines on the front side, which improves passivation performance while also enhancing light absorption, thus comprehensively improving cell performance.

[0003] Traditional polysilicon-passivated TBC cells form an isolation between the doped polysilicon and the silicon substrate through a tunneling layer, resulting in a passivation contact structure of doped polysilicon-tunneling layer-silicon substrate stack, which reduces carrier transport efficiency to some extent. Summary of the Invention

[0004] Therefore, it is necessary to provide a tunneling oxide passivated contact structure and its preparation method, as well as a solar cell, to address the above problems. The tunneling oxide passivated contact structure described in this application can promote carrier collection and reduce the carrier transmission resistance in the tunneling layer, thereby significantly increasing current.

[0005] The first aspect of this application provides a tunneling oxide passivation contact structure, including a first tunneling oxide passivation contact structure and at least one second tunneling oxide passivation contact structure stacked on the surface of the first tunneling oxide passivation contact structure.

[0006] The first tunneling oxide passivation contact structure includes a first tunneling oxide layer and a first doped polysilicon layer stacked together;

[0007] The second tunneling oxide passivation contact structure includes a second tunneling oxide layer and a second doped polysilicon layer stacked together. The second tunneling oxide layer includes doped polysilicon particles, and doped atoms are enriched in the doped polysilicon particles.

[0008] This application designs a multi-layer second tunneling oxide passivation contact structure based on the traditional tunneling oxide passivation contact structure. At the same time, doped polycrystalline silicon particles enriched with doped atoms are set in the second tunneling oxide layer of the second tunneling oxide passivation contact structure. This not only helps to enhance the interface barrier of the first doped polycrystalline silicon layer in the first tunneling oxide passivation contact structure and promote carrier collection, but also reduces the carrier transport resistance in the tunneling layer, which is conducive to the formation of efficient tunneling channels, thereby significantly improving the current.

[0009] In one embodiment, the particle size of the doped polycrystalline silicon particles is less than 10 nm.

[0010] By controlling the size of doped polycrystalline silicon particles, it is beneficial to optimize the enrichment effect of doped atoms, enhance the selective collection of charge carriers, and reduce recombination.

[0011] In one embodiment, the second tunneling oxide passivation contact structure consists of 1 to 3 layers.

[0012] By setting the number of multiple layers of the second tunneling oxide passivation contact structure, it is beneficial to further increase the doping concentration of the doped polycrystalline silicon layer close to the silicon substrate, thereby increasing the potential barrier and promoting carrier collection.

[0013] In one embodiment, the thickness of the first tunneling oxide layer is less than the thickness of the second tunneling oxide layer.

[0014] In one embodiment, the thickness of the first tunneling oxide layer is 1 nm to 3 nm;

[0015] And / or, the thickness of the second tunneling oxide layer is 5nm~10nm.

[0016] By adjusting the thickness relationship between the first tunneling oxide layer and the second tunneling oxide layer, and further optimizing the specific thickness range of the first tunneling oxide layer and the second tunneling oxide layer, the first tunneling oxide layer and the second tunneling oxide layer can be used as doping barrier layers, which helps to avoid excessive internal doping concentration and thus optimize the passivation effect.

[0017] In one embodiment, the thickness of the first doped polysilicon layer is less than the thickness of the second doped polysilicon layer.

[0018] In one embodiment, the thickness of the first doped polysilicon layer is less than or equal to 40 nm;

[0019] And / or, the thickness of the second doped polycrystalline silicon layer is 50nm~100nm.

[0020] By adjusting the thickness relationship between the first doped polysilicon layer and the second doped polysilicon layer, and further optimizing the specific thickness range of the first doped polysilicon layer and the second doped polysilicon layer, the first doped polysilicon layer and the second doped polysilicon layer can be used as doping barrier layers, which helps to avoid excessive internal doping concentration and thus optimize the passivation effect.

[0021] In one embodiment, in the tunneling oxide passivated contact structure, the doping concentration decreases from the second doped polysilicon layer to the first tunneling oxide layer, wherein the doping concentration of the second doped polysilicon layer is 4 × 10⁻⁶. 19 cm -3 ~8×10 19 cm -3 The doping concentration of the first tunneling oxide layer is 1×10⁻⁶. 19 cm -3 ~4×10 19 cm -3 .

[0022] By controlling the degree of doping concentration variation in the tunnel oxide passivation contact structure, the short-circuit current density can be significantly improved, and the open-circuit voltage and fill factor can be optimized, thereby achieving a comprehensive improvement in conversion efficiency.

[0023] A second aspect of this application provides a method for preparing the tunneling oxide layer passivated contact structure as described above, comprising the following steps:

[0024] A first tunneling oxide layer and a first amorphous silicon layer are sequentially deposited on the surface of a silicon substrate;

[0025] The surface of the first amorphous silicon layer is oxidized to transform the amorphous silicon on the surface into an amorphous silicon oxide layer, and a second amorphous silicon layer is deposited on the surface of the amorphous silicon oxide layer. By sequentially cyclically oxidizing and depositing the second amorphous silicon layer, multiple amorphous silicon oxide layers and multiple second amorphous silicon layers are formed.

[0026] Annealing process is used to crystallize and transform the first amorphous silicon layer, the amorphous silicon oxide layer, and the second amorphous silicon layer to form the first polycrystalline silicon layer, the pre-set second tunneling oxide layer, and the second polycrystalline silicon layer.

[0027] The tunneling oxide passivation contact structure is obtained by forming a first tunneling oxide layer, a first doped polysilicon layer, multiple layers of second tunneling oxide layer and multiple layers of second doped polysilicon layer through doping diffusion transformation.

[0028] The preparation method described in this application involves directly oxidizing and annealing an amorphous silicon thin film, resulting in phase separation at the interface between the oxygen-rich and silicon-rich regions, leading to the crystallization of a silicon oxide layer (SiO2). x=0.64~1.35The material contains nanocrystalline silicon (nc-Si) particles. During the doping and diffusion process, dopant atoms can replace silicon atoms in the lattice of the nanocrystalline silicon particles, creating ordered vacancies and diffusion channels in the crystal structure. This promotes carrier collection, reduces the carrier transport resistance in the tunneling layer, and increases current. Furthermore, this fabrication method is an optimization and improvement upon traditional solar cell fabrication, and is simple and easy to operate.

[0029] A third aspect of this application also provides a solar cell including the tunneling oxide passivated contact structure described above.

[0030] Compared with traditional solar cells, the solar cells described in this application have higher current and significant technical advantages in terms of conversion efficiency and output power. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the tunneling oxide layer passivation contact structure in one embodiment of this application;

[0033] Figure 2 This is a schematic diagram of the structure of a solar cell in one embodiment of this application;

[0034] Figure 3 This is a schematic diagram of the structure of a solar cell in another embodiment of this application.

[0035] Among them, 10 is a tunneling oxide passivation contact structure; 101 is a first tunneling oxide passivation contact structure; 1011 is a first tunneling oxide layer; 1012 is a first doped polysilicon layer; 102 is a second tunneling oxide passivation contact structure; 1021 is a second tunneling oxide layer; 1022 is a second doped polysilicon layer; and 30 is an AlO₂O₃ layer. x Passivation layer; 40, SiO x N y Passivation layer; 50, emitter. Detailed Implementation

[0036] To facilitate understanding of this application, it will be described in more detail below. However, it should be understood that this application can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments or examples only and is not intended to be limiting of this application.

[0038] Through long-term research and experimentation, the applicant discovered that in multilayer tunneling oxide passivation contact structures, the tunneling oxide layer away from the silicon substrate can significantly increase the doping concentration of the doped polycrystalline silicon layer close to the silicon substrate, forming a high barrier and thus promoting carrier collection. However, on this basis, it is also necessary to ensure that the multilayer tunneling oxide layer has good carrier transport properties.

[0039] Based on this, this application provides a tunnel oxide layer passivation contact structure, combined with Figure 1 As shown, the tunneling oxide passivation contact structure 10 includes a first tunneling oxide passivation contact structure 101 and at least one second tunneling oxide passivation contact structure 102 stacked on the surface of the first tunneling oxide passivation contact structure 101.

[0040] The first tunneling oxide passivation contact structure 101 includes a first tunneling oxide layer 1011 and a first doped polysilicon layer 1012 stacked together.

[0041] The second tunneling oxide passivation contact structure 102 includes a second tunneling oxide layer 1021 and a second doped polysilicon layer 1022 stacked together. The second tunneling oxide layer 1021 includes doped polysilicon particles, and doped atoms are enriched in the doped polysilicon particles.

[0042] Conventional tunneling oxide layers have weak absorption and retention capabilities for dopants. When dopants reach the interface between the tunneling oxide layer and silicon particles, they can replace silicon atoms in the silicon lattice, forming stable substitutional doping. At this point, the crystal structure provides ordered vacancies and diffusion channels, allowing dopants to efficiently enter and remain at lattice positions, thus achieving high solid solubility and electrical activation rate. Doping concentrations can reach 10-1. 19 atoms / cm 3 ~10 21 atoms / cm 3 This allows for the use of silicon particles enriched with doped atoms to promote carrier collection and reduce the transport resistance of carriers in the tunneling layer, thereby significantly increasing the current, while almost without losing the passivation effect of the tunneling oxide layer.

[0043] This application designs a multilayer second tunneling oxide passivation contact structure 102 based on the traditional tunneling oxide passivation contact structure. At the same time, doped polycrystalline silicon particles enriched with doped atoms are set in the second tunneling oxide layer 1021 of the second tunneling oxide passivation contact structure 102. This not only helps to improve the interface barrier of the first doped polycrystalline silicon layer 1012 in the first tunneling oxide passivation contact structure 101 and promotes carrier collection, but also the doped polycrystalline silicon particles can reduce the carrier transport resistance in the tunneling layer, which is conducive to the formation of efficient tunneling channels, thereby significantly improving the current.

[0044] In one embodiment of this application, the particle size of the doped polycrystalline silicon particles is less than 10 nm. By controlling the size of the doped polycrystalline silicon particles, it is beneficial to increase the specific surface area of ​​the particles and optimize the enrichment effect of doped atoms therein, thereby forming an efficient and low-resistance three-dimensional tunneling network in the oxide layer, enhancing the selective collection of charge carriers and reducing recombination.

[0045] It is understood that the particle size of the doped polycrystalline silicon particles needs to be smaller than the thickness of the second tunneling oxide layer; the particle size of the doped polycrystalline silicon particles includes, but is not limited to, any value of 1nm, 3nm, 5nm, 7nm, 9nm or any range between two; this application does not limit the shape of the doped polycrystalline silicon particles, including but not limited to spherical particles.

[0046] In one embodiment of this application, the second tunneling oxide passivation contact structure 102 has 1 to 3 layers, such as 1, 2 or 3 layers. By setting the number of multiple layers of the second tunneling oxide passivation contact structure 102, it is beneficial to further increase the doping concentration of the doped polycrystalline silicon layer close to the silicon substrate, thereby increasing the potential barrier and promoting carrier collection.

[0047] In one embodiment of this application, the thickness of the first tunneling oxide layer 1011 is less than the thickness of the second tunneling oxide layer 1021. Preferably, the thickness of the first tunneling oxide layer 1011 is 1nm to 3nm, including but not limited to any one of 1nm, 1.5nm, 2nm, 2.5nm, and 3nm or any range between two of them; the thickness of the second tunneling oxide layer 1021 is 5nm to 10nm, including but not limited to any one of 5nm, 6nm, 7nm, 8nm, 9nm, and 10nm or any range between two of them.

[0048] By adjusting the thickness relationship between the first tunneling oxide layer 1011 and the second tunneling oxide layer 1021, and further optimizing the specific thickness range of the first tunneling oxide layer 1011 and the second tunneling oxide layer 1021, the first tunneling oxide layer 1011 and the second tunneling oxide layer 1021 can be used as doping barrier layers, which helps to avoid excessive internal doping concentration and thus optimize the passivation effect.

[0049] In one embodiment of this application, the thickness of the first doped polysilicon layer 1012 is less than the thickness of the second doped polysilicon layer 1022. Preferably, the thickness of the first doped polysilicon layer 1012 is less than or equal to 40 nm, including but not limited to any value of 5 nm, 10 nm, 20 nm, 30 nm, or 40 nm, or a range between any two; the thickness of the second doped polysilicon layer 1022 is 50 nm to 100 nm, including but not limited to any value of 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm, or a range between any two.

[0050] By adjusting the thickness relationship between the first doped polysilicon layer 1012 and the second doped polysilicon layer 1022, and further optimizing the specific thickness range of the first doped polysilicon layer 1012 and the second doped polysilicon layer 1022, the first doped polysilicon layer 1012 and the second doped polysilicon layer 1022 can be used as doping barrier layers, which helps to avoid excessive internal doping concentration and thus optimize the passivation effect.

[0051] In one embodiment of this application, in the tunnel oxide passivation contact structure 10, the doping concentration decreases from the second doped polysilicon layer 1022 to the first tunnel oxide layer 1011, and more preferably decreases sequentially, wherein the doping concentration of the second doped polysilicon layer 1022 is 4 × 10⁻⁶. 19 cm -3 ~8×10 19 cm -3 , including but not limited to 4×10 19 cm -3 5×10 19 cm -3 6×10 19 cm -3 7×10 19 cm -3 8×10 19 cm -3 The value at any point in the range or any range between the two is preferably 6×10. 19 cm -3 ~7×10 19 cm -3 The doping concentration of the first tunneling oxide layer 1011 is 1×10⁻⁶. 19 cm -3 ~4×10 19 cm -3 , including but not limited to 1×10 19 cm -3 2×10 19 cm -3 3×1019 cm -3 4×10 19 cm -3 The value at any point in the range or between any two is preferably 2×10. 19 cm -3 ~3×10 19 cm -3 .

[0052] By controlling the degree of doping concentration variation in the tunnel oxide passivation contact structure 10, a specific potential gradient can be formed. This not only reduces the residence time of charge carriers in the composite interface region between the tunnel oxide layer and the doped polysilicon layer, promoting carrier tunneling and rapid collection, but also suppresses carrier recombination at the interface, thereby significantly improving the short-circuit current density, as well as simultaneously optimizing the open-circuit voltage and fill factor, achieving a comprehensive improvement in conversion efficiency.

[0053] This application provides a method for preparing the tunneling oxide passivated contact structure 10 as described above, comprising the following steps:

[0054] A first tunneling oxide layer and a first amorphous silicon layer are sequentially deposited on the surface of a silicon substrate;

[0055] The surface of the first amorphous silicon layer is oxidized to transform the amorphous silicon on the surface into an amorphous silicon oxide layer, and a second amorphous silicon layer is deposited on the surface of the amorphous silicon oxide layer. By sequentially cyclically oxidizing and depositing the second amorphous silicon layer, multiple amorphous silicon oxide layers and multiple second amorphous silicon layers are formed.

[0056] Annealing process is used to crystallize and transform the first amorphous silicon layer, the amorphous silicon oxide layer, and the second amorphous silicon layer to form the first polycrystalline silicon layer, the pre-set second tunneling oxide layer, and the second polycrystalline silicon layer.

[0057] The tunneling oxide passivated contact structure 10 is obtained by forming a first tunneling oxide layer 1011, a first doped polysilicon layer 1012, a multilayer second tunneling oxide layer 1021, and a multilayer second doped polysilicon layer 1022 through doping diffusion transformation.

[0058] The preparation method described in this application involves directly oxidizing and annealing an amorphous silicon thin film, resulting in phase separation at the interface between the oxygen-rich and silicon-rich regions, leading to the crystallization of a silicon oxide layer (SiO2). x=0.64~1.35 The material contains nanocrystalline silicon (nc-Si) particles. During the doping and diffusion process, dopant atoms can replace silicon atoms in the lattice of the nanocrystalline silicon particles, creating ordered vacancies and diffusion channels in the crystal structure. This promotes carrier collection, reduces the carrier transport resistance in the tunneling layer, and increases current. Furthermore, this fabrication method is an optimization and improvement upon traditional solar cell fabrication, and is simple and easy to operate.

[0059] It is understood that this application does not restrict the processes such as deposition, oxidation, annealing and diffusion doping, and existing conventional process conditions can be directly used for preparation. For example, deposition can be carried out using low-pressure chemical vapor deposition (LPCVD); oxidation can also be carried out using low-pressure chemical vapor deposition (LPCVD); doping includes boron doping, phosphorus doping and other doping methods.

[0060] It should be noted that for the fabrication of solar cells, after the tunnel oxide passivation contact structure is prepared through the above process, subsequent steps can be carried out according to conventional process steps. For example, AlO2 can be deposited on both sides of the cell using the ALD process. x A passivation layer is then deposited on both sides of the solar cell using a PECVD process to deposit SiO2. x N y The passivation layer is then processed, and finally, the back emitter of the solar cell is fabricated through processes such as screen printing, sintering, light injection, and laser-assisted sintering, thus completing the fabrication of the solar cell.

[0061] This application also provides a solar cell including the tunneling oxide passivated contact structure 10 as described above.

[0062] Compared with traditional solar cells, the solar cells described in this application have higher current and significant technical advantages in terms of conversion efficiency and output power.

[0063] It is understood that the tunneling oxide passivated contact structure 10 described in this application is applicable to various solar cells, including but not limited to TBC cells, TOPCon cells and IBC cells, and is particularly applicable to TBC cells.

[0064] In one embodiment of this application, as Figures 2-3 As shown, the back side of the solar cell mainly includes an N-region tunneling oxide passivation contact structure 10, a P-region tunneling oxide passivation contact structure 10, and AlO₂. x Passivation layer 30, SiO x N y The passivation layer 40 and the emitter 50, wherein at least one of the N-region and the P-region is a multi-layered tunneling oxide passivation contact structure 10, i.e.: Figure 2 As shown, region N can be a conventional single-layer tunneling oxide passivation contact structure, and region P can be a double-layer tunneling oxide passivation contact structure 10 in one embodiment of this application; or, region P can be a conventional single-layer tunneling oxide passivation contact structure, and region N can be a double-layer tunneling oxide passivation contact structure 10 in one embodiment of this application; Figure 3 As shown, both the N-region and the P-region are double-layered tunneling oxide passivation contact structures 10 in one embodiment of this application.

[0065] The following specific embodiments will further illustrate the tunneling oxide passivated contact structure, its preparation method, and the solar cell. However, those skilled in the art will understand that the following embodiments are for illustrative purposes only and should not be considered as limiting the scope of this application. Unless otherwise specified, specific conditions in the embodiments are performed under conventional conditions or conditions recommended by the manufacturer. Reagents or instruments used without specified manufacturers are all commercially available conventional products.

[0066] Example 1

[0067] The silicon wafer is polished on both sides using a tank-type alkaline polishing process to remove surface impurities and damaged layers.

[0068] Using LPCVD technology, a predetermined first tunneling oxide layer (SiO2) is fabricated on the back side of a silicon wafer. x The first amorphous silicon layer (i-Poly, 30nm) and the second amorphous silicon layer (i-Poly, 30nm) are deposited on the surface of the first amorphous silicon layer by LPCVD technology to form an amorphous silicon oxide layer (10nm), and a second amorphous silicon layer (85nm) is deposited on its surface.

[0069] The material is transferred to a boron diffusion apparatus, where high-temperature annealing crystallizes the first amorphous silicon layer, the second amorphous silicon layer, and the amorphous silicon oxide layer. At this point, the amorphous silicon oxide layer contains nanocrystalline silicon particles (nc-Si). Boron trichloride (BCl3) and oxygen are then introduced to complete boron diffusion, thus completing the preparation of the tunneling oxide passivation contact structure.

[0070] Laser-assisted photolithography (LAP) is used to remove some surface-bound silicon gas slag (BSG) in the passivated contact structure through the tunnel oxide layer. Then, a wet-tank process is employed to remove the BSG in the laser-treated area and a small amount of silicon substrate etched using a strongly alkaline solution and additives.

[0071] An N-type monolayer phosphorus-doped polycrystalline silicon layer and a tunnel oxide layer structure were prepared in the grooved area on the back of the battery using conventional LPCVD and phosphorus diffusion methods. A portion of the PSG was removed using laser film-opening technology.

[0072] Through a wet chain process, using additives and strong acid / base reagents, B / PSG and excess doped polysilicon are removed from the front and sides of the solar cell. Furthermore, a wet tank process creates a textured surface on the front of the cell, and all BSG and PSG in the P-Gap-N region on the back are also removed.

[0073] Following the standard TBC battery manufacturing process, AlO2 was subsequently deposited on both sides of the cell using the ALD process. x Passivation layer, SiO2 deposited on both sides of the solar cell using PECVD process. x N y The passivation layer, and the back emitter of the battery cell are fabricated through processes such as screen printing, sintering, light injection, and laser-assisted sintering to complete the preparation of TBC batteries.

[0074] Example 2

[0075] The difference between Example 2 and Example 1 is that LPCVD technology is used to fabricate a pre-defined first tunneling oxide layer (SiO2) on the back side of the silicon wafer. x The process involves depositing a first amorphous silicon layer (i-Poly, 20nm) and a second amorphous silicon layer (i-Poly, 20nm). The surface of the first amorphous silicon layer is oxidized using LPCVD technology to form an amorphous silicon oxide layer (8nm), and a second amorphous silicon layer (60nm) is deposited on its surface. The surface of the second amorphous silicon layer is then oxidized again using LPCVD technology to form an amorphous silicon oxide layer (8nm), and a third amorphous silicon layer (60nm) is deposited on its surface.

[0076] Example 3

[0077] The difference between Example 3 and Example 1 is that LPCVD technology is used to fabricate a pre-defined first tunneling oxide layer (SiO2) on the back side of the silicon wafer. x The process involves depositing a first amorphous silicon layer (i-Poly, 10nm) and a second amorphous silicon layer (i-Poly, 10nm). The surface of the first amorphous silicon layer is oxidized using LPCVD to form an amorphous silicon oxide layer (5nm), and a second amorphous silicon layer (50nm) is deposited on its surface. The surface of the second amorphous silicon layer is then oxidized again using LPCVD to form an amorphous silicon oxide layer (5nm), and a third amorphous silicon layer (50nm) is deposited on its surface. Finally, the surface of the third amorphous silicon layer is oxidized again using LPCVD to form an amorphous silicon oxide layer (5nm), and a fourth amorphous silicon layer (50nm) is deposited on its surface.

[0078] Example 4

[0079] The difference between Example 4 and Example 1 is that after high-temperature annealing to complete crystallization, phosphorus oxychloride (POCl3) and nitrogen are introduced to complete phosphorus diffusion and complete the preparation of the tunnel oxide passivation contact structure. Subsequently, a P-type monolayer phosphorus-doped polycrystalline silicon layer and a tunnel oxide structure are prepared in the grooved area on the back of the battery.

[0080] Example 5

[0081] The difference between Example 5 and Example 1 is that the same process is used to fabricate the N-type double-layer phosphorus-doped polycrystalline silicon layer and tunneling oxide layer structure in the grooved area on the back of the cell. The resulting solar cell structure can be referenced. Figure 3 The diagram shown is a structural schematic.

[0082] Comparative Example 1

[0083] The difference between Comparative Example 1 and Example 1 is that no second tunneling oxide layer and no second doped polysilicon layer were prepared.

[0084] Comparative Example 2

[0085] The difference between Comparative Example 2 and Example 1 is that silicon oxide is directly deposited on the surface of the first amorphous silicon layer as the second tunneling oxide layer using LPCVD technology, and a second amorphous silicon layer is then deposited on its surface.

[0086] High-resolution TEM lattice analysis was performed on the tunneling oxide passivated contact structures prepared in Examples 1 to 5. Clear lattice fringes were observed in the second tunneling oxide layers of Examples 1 and 4-5, the two-layer second tunneling oxide layer of Example 2, and the three-layer second tunneling oxide layer of Example 3. By comparing the lattice fringes, it can be seen that they are crystalline silicon particles, that is, polycrystalline silicon particles exist in the second tunneling oxide layer. Furthermore, local bright spots can also be observed at the positions of the lattice fringes of the second tunneling oxide layer, which proves that doped atoms are enriched in the polycrystalline silicon particles.

[0087] ECV tests were performed on the tunneling oxide passivated contact structures prepared in Examples 1 to 3, and the results are shown in Table 1.

[0088] Table 1

[0089]

[0090] The performance of the solar cells prepared in all embodiments and comparative examples was tested (IV curves were obtained using a photoelectric testing machine), and the test results are summarized in Table 2.

[0091] Table 2

[0092]

[0093] As shown in Table 2, compared with the conventional solar cell structure provided in Comparative Example 1, the solar cells prepared in Examples 1 to 5 have the special tunneling oxide passivation contact structure described in this application, which can increase the short-circuit current to 13.81A~14.43A and the maximum operating current to 13.24A~13.83A, resulting in a significant improvement in conversion efficiency. While Comparative Example 2 has a multi-layer tunneling oxide passivation contact structure, the tunneling oxide layer on the original silicon substrate does not contain silicon particles, and there is no enrichment of doped atoms, resulting in the multi-layer tunneling oxide passivation contact structure not achieving good carrier collection and transport effects.

[0094] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A tunneling oxide passivation contact structure for solar cells, characterized in that, The tunneling oxide passivation contact structure includes a first tunneling oxide passivation contact structure and at least one second tunneling oxide passivation contact structure stacked on the surface of the first tunneling oxide passivation contact structure. The first tunneling oxide passivation contact structure includes a first tunneling oxide layer and a first doped polysilicon layer stacked together; The second tunneling oxide passivation contact structure includes a second tunneling oxide layer and a second doped polysilicon layer stacked together. The second tunneling oxide layer includes doped polysilicon particles, and doped atoms are enriched in the doped polysilicon particles.

2. The tunneling oxide passivation contact structure according to claim 1, characterized in that, The particle size of the doped polycrystalline silicon particles is less than 10 nm.

3. The tunneling oxide passivation contact structure according to claim 1, characterized in that, The second tunneling oxide passivation contact structure consists of 1 to 3 layers.

4. The tunneling oxide passivation contact structure according to claim 1, characterized in that, The thickness of the first tunneling oxide layer is less than the thickness of the second tunneling oxide layer.

5. The tunneling oxide passivation contact structure according to claim 4, characterized in that, The thickness of the first tunneling oxide layer is 1 nm to 3 nm; And / or, the thickness of the second tunneling oxide layer is 5nm~10nm.

6. The tunneling oxide passivation contact structure according to claim 1, characterized in that, The thickness of the first doped polysilicon layer is less than the thickness of the second doped polysilicon layer.

7. The tunneling oxide passivation contact structure according to claim 6, characterized in that, The thickness of the first doped polycrystalline silicon layer is less than or equal to 40 nm; And / or, the thickness of the second doped polycrystalline silicon layer is 50nm~100nm.

8. The tunneling oxide passivation contact structure according to claim 1, characterized in that, In the tunneling oxide passivated contact structure, the doping concentration decreases from the second doped polysilicon layer to the first tunneling oxide layer, wherein the doping concentration of the second doped polysilicon layer is 4 × 10⁻⁶. 19 cm -3 ~8×10 19 cm -3 The doping concentration of the first tunneling oxide layer is 1×10⁻⁶. 19 cm -3 ~4×10 19 cm -3 .

9. A method for preparing a tunneling oxide passivated contact structure as described in any one of claims 1 to 8, characterized in that, Includes the following steps: A first tunneling oxide layer and a first amorphous silicon layer are sequentially deposited on the surface of a silicon substrate; The surface of the first amorphous silicon layer is oxidized to transform the amorphous silicon on the surface into an amorphous silicon oxide layer, and a second amorphous silicon layer is deposited on the surface of the amorphous silicon oxide layer. By sequentially cyclically oxidizing and depositing the second amorphous silicon layer, multiple amorphous silicon oxide layers and multiple second amorphous silicon layers are formed. Annealing process is used to crystallize and transform the first amorphous silicon layer, the amorphous silicon oxide layer, and the second amorphous silicon layer to form the first polycrystalline silicon layer, the pre-set second tunneling oxide layer, and the second polycrystalline silicon layer. The tunneling oxide passivation contact structure is obtained by forming a first tunneling oxide layer, a first doped polysilicon layer, multiple layers of second tunneling oxide layer and multiple layers of second doped polysilicon layer through doping diffusion transformation.

10. A solar cell, characterized in that, Includes the tunneling oxide passivation contact structure as described in any one of claims 1 to 8.

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