Light Emitting Diode Chips and Their Fabrication Methods

Abstract

This disclosure discloses a light-emitting diode (LED) chip and its fabrication method, belonging to the field of semiconductor technology. The LED chip includes: an epitaxial layer, a first electrode, a second electrode, a first passivation layer, a second passivation layer, a first pad, and a second pad. The first passivation layer has first electrode holes and second electrode holes; the second passivation layer has first pad holes and second pad holes. The vertical projection of the first pad holes on the epitaxial layer does not coincide with the vertical projections of all the first electrode holes on the epitaxial layer; the vertical projection of the first pad holes on the epitaxial layer does not coincide with the vertical projections of all the second electrode holes on the epitaxial layer; the vertical projection of the second pad holes on the epitaxial layer does not coincide with the vertical projections of all the first electrode holes on the epitaxial layer; the vertical projection of the second pad holes on the epitaxial layer does not coincide with the vertical projections of all the second electrode holes on the epitaxial layer. The embodiments of this disclosure enable the LED chip to be used in outdoor environments.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a light-emitting diode chip and its fabrication method. Background Technology

[0002] A light-emitting diode (LED) chip is a semiconductor device that can convert electrical energy into light energy.

[0003] In related technologies, LED chips are classified into two categories based on their application environment: outdoor and indoor. For outdoor applications, upright LED chips are widely used due to their superior corrosion resistance. However, the packaging process for upright LED chips requires wire bonding with gold wire, resulting in higher costs. In contrast, flip-chip LED chips only require die bonding with solder paste, eliminating the need for wire bonding and thus reducing costs.

[0004] However, the electrodes of flip-chip LEDs typically contain aluminum. Aluminum is a reactive metal that reacts with water in outdoor environments, especially in high-temperature and high-humidity environments, where it is prone to corrosion. This can lead to increased voltage in the LED chip and even cause the LED to fail. Summary of the Invention

[0005] This disclosure provides a light-emitting diode (LED) chip and its fabrication method, enabling the LED chip to be used in outdoor environments. The technical solution is as follows: On one hand, this disclosure provides a light-emitting diode chip, including: an epitaxial layer, a first electrode, a second electrode, a first passivation layer, a second passivation layer, a first pad, and a second pad; The first passivation layer is located on one side of the epitaxial layer, and the first passivation layer has a first electrode hole and a second electrode hole; The first electrode is located on the side of the first passivation layer opposite to the epitaxial layer, and the first electrode passes through the first electrode hole and is connected to the epitaxial layer; The second electrode is located on the side of the first passivation layer opposite to the epitaxial layer, and the second electrode passes through the second electrode hole and is connected to the epitaxial layer; The second passivation layer is located on the side of the first passivation layer opposite to the epitaxial layer, and the second passivation layer has a first pad hole and a second pad hole; The first pad penetrates through the first pad hole and contacts the first electrode, and the second pad penetrates through the second pad hole and contacts the second electrode; The vertical projection of the first pad hole on the epitaxial layer does not coincide with the vertical projection of all the first electrode holes on the epitaxial layer, and the vertical projection of the first pad hole on the epitaxial layer does not coincide with the vertical projection of all the second electrode holes on the epitaxial layer. The vertical projection of the second pad hole on the epitaxial layer does not coincide with the vertical projection of all the first electrode holes on the epitaxial layer.

[0006] In one implementation of this disclosure, neither the first pad nor the second pad is made of aluminum or silver, and both the first electrode and the second electrode are made of aluminum or silver.

[0007] In one implementation of this disclosure, the first pad and the second pad are composed of an adhesion layer, a fusion layer and a bonding layer stacked sequentially.

[0008] In one implementation of this disclosure, the thickness of the fusion layer is 8-12 times the thickness of the adhesion layer.

[0009] In one implementation of this disclosure, the thickness of the fusion layer is 2-4 times the thickness of the bonding layer.

[0010] In one implementation of this disclosure, the fusion layer material is nickel, and the bonding layer material is gold.

[0011] In one implementation of this disclosure, the light-emitting diode chip further includes a third passivation layer; The third passivation layer is located on the side of the second passivation layer opposite to the first passivation layer. The third passivation layer has a third electrode hole and a fourth electrode hole. The third electrode hole exposes at least a portion of the first pad, and the fourth electrode hole exposes at least a portion of the second pad.

[0012] In one implementation of this disclosure, the light-emitting diode chip further includes a third electrode and a fourth electrode; The first electrode is connected to the epitaxial layer via the third electrode; The second electrode is connected to the epitaxial layer via the fourth electrode.

[0013] In one implementation of this disclosure, the inner walls of the first electrode hole and the second electrode hole are inclined surfaces, and the opening size of the first electrode hole and the second electrode hole facing away from the epitaxial layer is larger than the opening size facing the epitaxial layer.

[0014] On the other hand, embodiments of this disclosure provide a method for fabricating a light-emitting diode chip, comprising: Preparation of epitaxial layer; A third electrode and a fourth electrode are fabricated on one side of the epitaxial layer; A first passivation layer is formed on one side of the epitaxial layer. The first passivation layer has a first electrode hole and a second electrode hole. The first electrode hole is opposite to the third electrode, and the second electrode hole is opposite to the fourth electrode. A first electrode and a second electrode are fabricated on the side of the first passivation layer opposite to the epitaxial layer. The first electrode is connected to the corresponding third electrode through the first electrode hole, and the second electrode is connected to the corresponding fourth electrode through the second electrode hole. A second passivation layer is formed on the side of the first passivation layer opposite to the epitaxial layer. The second passivation layer has a first pad hole and a second pad hole. The vertical projection of the first pad hole on the epitaxial layer does not coincide with the vertical projection of all the first electrode holes on the epitaxial layer. The vertical projection of the first pad hole on the epitaxial layer does not coincide with the vertical projection of all the second electrode holes on the epitaxial layer. The vertical projection of the second pad hole on the epitaxial layer does not coincide with the vertical projection of all the first electrode holes on the epitaxial layer. A first pad and a second pad are prepared on the side of the second passivation layer opposite to the first passivation layer, such that the first pad penetrates the first pad hole and contacts the first electrode, and the second pad penetrates the second pad hole and contacts the second electrode.

[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The LED chip provided in this disclosure introduces a second passivation layer between the first passivation layer and the pads, and designs the positional relationships between the first pad holes and the first electrode holes and the second electrode holes on the second passivation layer, as well as the positional relationships between the second pad holes and the first electrode holes and the second electrode holes on the second passivation layer. This ensures that the second passivation layer precisely covers any gaps and weak points that may exist between the first electrode, the second electrode, and the first passivation layer, thereby blocking the path of developer and external moisture penetration and corrosion of the electrodes. In this way, the problem of easy corrosion of the electrodes in flip-chip LEDs is effectively solved, enhancing the LED chip's moisture resistance and overall sealing performance, allowing it to meet high-temperature and high-humidity outdoor usage conditions while retaining its low-cost advantage.

[0016] In other words, the light-emitting diode chip provided in this embodiment of the present disclosure, through reasonable design of the positions of the first pad hole and the second pad hole of the second passivation layer, enables the second passivation layer to effectively seal any gaps that may exist between the first electrode, the second electrode and the first passivation layer, thereby fundamentally preventing the infiltration of external moisture and enabling the light-emitting diode chip to be suitable for outdoor high temperature and high humidity environments. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of the light-emitting diode chip provided in the embodiments of this disclosure; Figure 2 This is provided by the embodiments of this disclosure. Figure 1 A magnified view of part A; Figure 3 This is a flowchart illustrating a method for fabricating a light-emitting diode chip according to an embodiment of this disclosure; Figure 4 This is a flowchart of another method for fabricating a light-emitting diode chip provided in this disclosure embodiment; Figure 5 This is a schematic diagram of the fabrication process of the light-emitting diode chip provided in the embodiments of this disclosure; Figure 6 This is a schematic diagram of the fabrication process of the light-emitting diode chip provided in the embodiments of this disclosure; Figure 7 This is a schematic diagram of the fabrication process of the light-emitting diode chip provided in the embodiments of this disclosure; Figure 8 This is a schematic diagram of the fabrication process of the light-emitting diode chip provided in the embodiments of this disclosure; Figure 9 This is a schematic diagram of the fabrication process of the light-emitting diode chip provided in the embodiments of this disclosure; Figure 10 This is a schematic diagram of the fabrication process of the light-emitting diode chip provided in the embodiments of this disclosure; Figure 11 This is a schematic diagram of the fabrication process of the light-emitting diode chip provided in the embodiments of this disclosure; Figure 12 This is a schematic diagram of the fabrication process of the light-emitting diode chip provided in the embodiments of this disclosure; Figure 13 This is a schematic diagram of the fabrication process of the light-emitting diode chip provided in the embodiments of this disclosure.

[0019] Icon labels: 10. Epitaxial layer; 110. Isolation trench; 210, First electrode; 220, Second electrode; 230, Third electrode; 240, Fourth electrode; 241. First connecting part; 242. Second connecting part; 310. First passivation layer; 320. Second passivation layer; 330. Third passivation layer; 311, First electrode hole; 312, Second electrode hole; 321, First pad hole; 322, Second pad hole; 331, Third electrode hole; 332, Fourth electrode hole; 410, First pad; 420, Second pad; 50. Current blocking layer; 60. Transparent conductive layer; 70. Substrate. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0021] This disclosure provides a light-emitting diode (LED) chip, which is a flip-chip LED chip. Figure 1 See the schematic diagram of the structure of this light-emitting diode chip. Figure 1 In this embodiment, the light-emitting diode chip includes an epitaxial layer 10, a first electrode 210, a second electrode 220, a first passivation layer 310, a second passivation layer 320, a first pad 410, and a second pad 420.

[0022] A first passivation layer 310 is located on one side of the epitaxial layer 10, and has a first electrode hole 311 and a second electrode hole 312. A first electrode 210 is located on the side of the first passivation layer 310 facing away from the epitaxial layer 10, and the first electrode 210 passes through the first electrode hole 311 and is connected to the epitaxial layer 10. A second electrode 220 is located on the side of the first passivation layer 310 facing away from the epitaxial layer 10, and the second electrode 220 passes through the second electrode hole 312 and is connected to the epitaxial layer 10. A second passivation layer 320 is located on the side of the first passivation layer 310 facing away from the epitaxial layer 10, and has a first pad hole 321 and a second pad hole 322. A first pad 410 passes through the first pad hole 321 and contacts the first electrode 210, and a second pad 420 passes through the second pad hole 322 and contacts the second electrode 220. The vertical projection of the first pad hole 321 on the epitaxial layer 10 does not coincide with the vertical projection of all the first electrode holes 311 on the epitaxial layer 10. Similarly, the vertical projection of the second pad hole 322 on the epitaxial layer 10 does not coincide with the vertical projection of all the second electrode holes 312 on the epitaxial layer 10.

[0023] The LED chip provided in this embodiment introduces a second passivation layer 320 between the first passivation layer 310 and the pads. The design of the positional relationship between the first pad hole 321 and the first electrode hole 311 and the second electrode hole 312 on the second passivation layer 320, as well as the positional relationship between the second pad hole 322 and the first electrode hole 311 and the second electrode hole 312 on the second passivation layer 320, ensures that the second passivation layer 320 precisely covers any gaps and weak points that may exist between the first electrode 210, the second electrode 220, and the first passivation layer 310. This effectively blocks the path of developer and external moisture penetration and corrosion of the electrodes. In this way, the problem of easy corrosion of the electrodes in flip-chip LEDs is effectively solved, enhancing the LED chip's moisture resistance and overall sealing performance. This allows it to meet high-temperature and high-humidity outdoor usage conditions while retaining its low-cost advantage.

[0024] In other words, the light-emitting diode chip provided in this embodiment of the present disclosure, through reasonable design of the positions of the first pad hole 321 and the second pad hole 322 of the second passivation layer 320, enables the second passivation layer 320 to effectively seal any gaps that may exist between the first electrode 210, the second electrode 220 and the first passivation layer 310, thereby fundamentally preventing the infiltration of external moisture and enabling the light-emitting diode chip to be suitable for outdoor high temperature and high humidity environments.

[0025] In this embodiment, the first passivation layer 310 is a distributed Bragg reflector (DBR), and the second passivation layer 320 is a silicon dioxide layer.

[0026] In the above implementation, the second passivation layer 320 forms a robust anti-permeation barrier due to the excellent density and insulation of silicon dioxide, enabling the light-emitting diode chip to have good water-blocking and moisture-proof performance even in high temperature and high humidity environments.

[0027] In this embodiment, the epitaxial layer 10 includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially.

[0028] The first semiconductor layer is an N-type semiconductor layer, the active layer is a quantum well layer, and the second semiconductor layer is a P-type semiconductor layer.

[0029] The first electrode 210 and the first pad 410 correspond to the first semiconductor layer, and the second electrode 220 and the second pad 420 correspond to the second semiconductor layer. The first pad 410 achieves ohmic contact with the first semiconductor layer through the first electrode 210, and the second pad 420 achieves ohmic contact with the second semiconductor layer through the second electrode 220.

[0030] See also Figure 1 In this embodiment, the light-emitting diode chip further includes a third electrode 230 and a fourth electrode 240. The first electrode 210 is connected to the epitaxial layer 10 through the third electrode 230, and the second electrode 220 is connected to the epitaxial layer 10 through the fourth electrode 240.

[0031] In the above implementation, reliable electrical connectivity between the inside of the LED chip and the external package is ensured through the step-by-step transmission between the first electrode 210 and the third electrode 230, and the step-by-step transmission between the second electrode 220 and the fourth electrode 240.

[0032] In this embodiment, the first electrode 210 and the second electrode 220 include an aluminum metal layer.

[0033] In the above implementation, on the one hand, the excellent reflective properties of the aluminum metal layer can effectively reflect light, thereby improving the brightness of the light-emitting diode chip. On the other hand, since the metal of the first pad 410 and the second pad 420 has large internal stress, the relatively soft aluminum metal layer can effectively buffer and release the stress brought by the first pad 410 and the second pad 420, avoiding the cracking of the bottom first passivation layer 310 due to excessive stress, thus eliminating the risk of physical structural failure of the light-emitting diode chip.

[0034] Figure 2 for Figure 1 A magnified view of part A, combined with Figure 2In this embodiment, the first electrode 210 and the second electrode 220 include a first connecting portion 241 and a second connecting portion 242. The inner contour of the first connecting portion 241 matches the inner contour of the first electrode hole 311 or the second electrode hole 312, and the first connecting portion 241 covers the inner sidewall of the first electrode hole 311 or the second electrode hole 312. The second connecting portion 242 is located on the side of the first passivation layer 310 facing away from the epitaxial layer 10.

[0035] In the above implementation, by extending the first connecting part 241 into the inner wall of the first electrode hole 311 or the second electrode hole 312, and by extending the second connecting part 242 laterally on the surface of the first passivation layer 310, it is ensured that the first electrode 210 and the second electrode 220 have a sufficiently large attachment contact area and conductive cross section, which greatly reduces the contact resistance of the first electrode 210 and the second electrode 220.

[0036] For example, the inner sidewalls of the first electrode hole 311 and the second electrode hole 312 are inclined surfaces, and the opening size of the first electrode hole 311 and the second electrode hole 312 facing away from the epitaxial layer 10 is larger than the opening size facing the epitaxial layer 10.

[0037] In the above implementation, the inner contours of the first electrode hole 311 and the second electrode hole 312 are inverted trapezoidal, which can improve the step coverage of the metal material in the hole and facilitate the continuous and uniform deposition and ramping of the electrode in the hole.

[0038] Because the inner walls of the first electrode hole 311 and the second electrode hole 312 are sloped, micro-cracks are prone to appear at the corners of the first connecting part 241 inside the hole and at the connection between the first connecting part 241 and the second connecting part 242 due to the characteristics of the electrode evaporation process. This allows alkaline developer to easily penetrate. However, the protection provided by the second passivation layer 320 effectively prevents the penetration of developer, thus avoiding aluminum layer corrosion and aluminum voids.

[0039] In this embodiment, the orthographic projections of the first pad hole 321 and the second pad hole 322 in the epitaxial growth direction are both located on the second connecting portion 242.

[0040] The design of the positions of the first pad hole 321 and the second pad hole 322 allows the first pad 410 and the second pad 420 to easily make ohmic contact with the second connection part 242, thereby making the geometric layout of the conductive channels inside the light-emitting diode chip more reasonable.

[0041] For example, the second connection portion 242 is a platform structure with a flat surface, such that the connection between the first pad 410 and the first electrode 210, and the connection between the second pad 420 and the second electrode 220 are both disposed on the flat platform (first passivation layer 310).

[0042] In this way, the slopes and corners that are prone to cracking are avoided, and the critical electrical connections are transferred to a flat platform that is relatively well covered and free of defects.

[0043] For example, the area of ​​the first pad 410 is larger than the area of ​​the first electrode 210 on the side of the first passivation layer 310 facing away from the epitaxial layer 10, and the area of ​​the second pad 420 is larger than the area of ​​the second electrode 220 on the side of the first passivation layer 310 facing away from the epitaxial layer 10.

[0044] By utilizing the first pad 410 and the second pad 420, which have larger areas, and in conjunction with the second passivation layer 320 below, the internal first electrode 210 and the second electrode 220 are completely enclosed, which helps to isolate moisture.

[0045] In this embodiment, neither the first pad 410 nor the second pad 420 is made of aluminum or silver, and both the first electrode 210 and the second electrode 220 are made of aluminum or silver.

[0046] In the aforementioned implementations, aluminum and silver possess excellent electrical conductivity and extremely high light reflectivity in the visible light band. Using them as electrode materials not only reduces ohmic contact resistance but also reflects light incident on the bottom of the chip, significantly improving the light extraction efficiency of the LED chip. However, for the pads, silver is prone to electromigration leading to short circuits, while aluminum readily oxidizes in air, forming a dense insulating alumina layer, making soldering difficult. Therefore, avoiding these two materials on the pad surface can effectively prevent pad oxidation, avoid the leakage and short circuit risks caused by silver ion migration, and significantly improve the reliability and yield of subsequent packaging wire bonding or soldering.

[0047] In this embodiment, the first pad 410 and the second pad 420 are composed of an adhesion layer, a fusion layer and a bonding layer stacked sequentially.

[0048] In the above implementation, the adhesion layer forms a strong bond with the first electrode 210 and the second electrode 220, preventing the solder pads from detaching under heat or stress. The fusion layer prevents the diffusion of metal atoms between the upper and lower layers at high temperatures, for example, preventing metal from the bottom layer's first electrode 210 and second electrode 220 from diffusing to the surface and affecting the soldering. In addition, the fusion layer can support the adhesion layer and the bonding layer, and provide mechanical support. The bonding layer is used for direct contact with external gold wires or solder, exhibiting good oxidation resistance and solder affinity.

[0049] For example, the adhesion layer material is titanium, the fusion layer material is nickel, and the bonding layer material is gold.

[0050] In the above implementation, nickel's hardness allows it to withstand the mechanical pressure during wire bonding and forms an extremely dense barrier, effectively preventing the diffusion of the underlying metal to the surface. Gold's chemical stability, when applied to the nickel surface, prevents nickel from oxidizing in air. Furthermore, gold possesses good ductility and electrical conductivity.

[0051] For example, the thickness of the fusion layer is 8-12 times the thickness of the adhesion layer, and the thickness of the fusion layer is 2-4 times the thickness of the bonding layer.

[0052] In the above implementation method, while ensuring that the pads have sufficient mechanical strength and excellent soldering performance, the amount of expensive surface metal used is minimized, thereby effectively reducing the manufacturing cost of the chip.

[0053] See you again Figure 1 In this embodiment, the light-emitting diode chip further includes a current blocking layer 50, which is located between the second electrode 220 and the second semiconductor layer.

[0054] In the above implementation, the current blocking layer 50 can effectively block the direct downward vertical conduction of current, forcing the current to change its path and spread in all directions, thereby making the current distribution in the epitaxial layer 10 more uniform.

[0055] In this embodiment, the light-emitting diode chip further includes a transparent conductive layer 60, which is located on the side of the second semiconductor layer opposite to the active layer, and the transparent conductive layer 60 is at least partially located between the current blocking layer 50 and the second electrode 220.

[0056] In the above implementation, the transparent conductive layer 60 has high light transmittance and high conductivity, which enables it to rapidly and uniformly expand the current in the wide planar area it covers, thus optimizing the lateral diffusion of the current.

[0057] For example, the transparent conductive layer 60 is an ITO (indium tin oxide) layer, and the transparent conductive layer 60 covers the upper surface of the second semiconductor layer and the upper surface of the current blocking layer 50.

[0058] In this embodiment, the light-emitting diode chip further includes a third passivation layer 330, which is located on the side of the second passivation layer 320 that faces away from the first passivation layer 310. The third passivation layer 330 has a third electrode hole 331 and a fourth electrode hole 332. The third electrode hole 331 exposes at least a portion of the first pad 410, and the fourth electrode hole 332 exposes at least a portion of the second pad 420.

[0059] In the above implementation, the third passivation layer 330 serves as the outermost insulating barrier of the LED chip, providing a sealed enclosure and mechanical protection for the internal structure of the LED chip.

[0060] For example, the third passivation layer 330 is a silicon dioxide layer.

[0061] This disclosure provides a method for fabricating a light-emitting diode chip. Figure 3 For a flowchart of the preparation method, see [link to flowchart]. Figure 3 The preparation method includes: Step 301: Prepare epitaxial layer 10.

[0062] Step 302: Prepare a third electrode 230 and a fourth electrode 240 on one side of the epitaxial layer 10.

[0063] Step 303: Prepare a first passivation layer 310 on one side of the epitaxial layer 10.

[0064] The first passivation layer 310 has a first electrode hole 311 and a second electrode hole 312. The first electrode hole 311 is opposite to the third electrode 230, and the second electrode hole 312 is opposite to the fourth electrode 240.

[0065] Step 304: Prepare a first electrode 210 and a second electrode 220 on the side of the first passivation layer 310 facing away from the epitaxial layer 10.

[0066] The first electrode 210 is connected to the corresponding third electrode 230 through the first electrode hole 311, and the second electrode 220 is connected to the corresponding fourth electrode 240 through the second electrode hole 312.

[0067] Step 305: Prepare a second passivation layer 320 on the side of the first passivation layer 310 that faces away from the epitaxial layer 10.

[0068] The second passivation layer 320 has a first pad hole 321 and a second pad hole 322. The vertical projection of the first pad hole 321 on the epitaxial layer 10 does not coincide with the vertical projection of all the first electrode holes 311 on the epitaxial layer 10. The vertical projection of the first pad hole 321 on the epitaxial layer 10 does not coincide with the vertical projection of all the second electrode holes 312 on the epitaxial layer 10. The vertical projection of the second pad hole 322 on the epitaxial layer 10 does not coincide with the vertical projection of all the first electrode holes 311 on the epitaxial layer 10. The vertical projection of the second pad hole 322 on the epitaxial layer 10 does not coincide with the vertical projection of all the second electrode holes 312 on the epitaxial layer 10.

[0069] Step 306: Prepare the first pad 410 and the second pad 420 on the side of the second passivation layer 320 opposite to the first passivation layer 310.

[0070] This allows the first pad 410 to penetrate the first pad hole 321 and contact the first electrode 210, and the second pad 420 to penetrate the second pad hole 322 and contact the second electrode 220.

[0071] The preparation method provided in this disclosure can prepare... Figures 1-2 The LED chip shown has therefore the following characteristics: Figures 1-2 The full range of beneficial effects of the LED chip shown will not be elaborated upon here.

[0072] This disclosure provides another method for fabricating a light-emitting diode chip. Figure 4 For a flowchart of the preparation method, see [link to flowchart]. Figure 4 The preparation method includes: Step 401: Provide a substrate 70.

[0073] For example, the substrate 70 is a sapphire substrate, a silicon substrate, or other light-emitting diode chip substrate material.

[0074] Step 402: Prepare epitaxial layer 10.

[0075] For example, metal-organic chemical vapor deposition (MOCVD) is used to grow a first semiconductor layer, an active layer, and a second semiconductor layer sequentially.

[0076] For example, the first semiconductor layer is an N-type GaN layer, the active layer is a quantum well layer, and the second semiconductor layer is a P-type GaN layer.

[0077] Step 403: Etch to obtain the mesa (MESA) trench (see...) Figure 5 ).

[0078] In this embodiment, the mesa trench extends from the second semiconductor layer, the active layer, the first semiconductor layer, to the substrate 70.

[0079] In step 403, mesa trenches are etched using photolithography and inductively coupled plasma (ICP) etching.

[0080] Step 404: Etching to obtain isolation trench 110 (see...) Figure 6 ).

[0081] Step 405: Fabrication of current blocking layer 50 (see...) Figure 7 ).

[0082] The current blocking layer 50 can effectively block the direct downward vertical conduction of current, forcing the current to change its path and diffuse in all directions, thereby making the current distribution in the epitaxial layer 10 more uniform.

[0083] Step 406: Prepare transparent conductive layer 60 (see...) Figure 8 ).

[0084] The transparent conductive layer 60 has high light transmittance and high conductivity, enabling it to rapidly and uniformly spread current over a wide planar area it covers, thus optimizing the lateral diffusion of current.

[0085] Step 407: Fabricate the third electrode 230 and the fourth electrode 240 on one side of the epitaxial layer 10 (see...) Figure 9 ).

[0086] In the above implementation, the third electrode 230 is in ohmic contact with the first semiconductor layer, and the fourth electrode 240 is in ohmic contact with the second semiconductor layer.

[0087] Step 408: Prepare a first passivation layer 310 on one side of the epitaxial layer 10 (see...) Figure 10 ).

[0088] The first passivation layer 310 has a first electrode hole 311 and a second electrode hole 312. The first electrode hole 311 is opposite to the third electrode 230, and the second electrode hole 312 is opposite to the fourth electrode 240.

[0089] Step 409: Fabricate the first electrode 210 and the second electrode 220 on the side of the first passivation layer 310 facing away from the epitaxial layer 10 (see...). Figure 11 ).

[0090] The first electrode 210 is connected to the corresponding third electrode 230 through the first electrode hole 311, and the second electrode 220 is connected to the corresponding fourth electrode 240 through the second electrode hole 312.

[0091] Step 4010: Prepare a second passivation layer 320 on the side of the first passivation layer 310 facing away from the epitaxial layer 10 (see...). Figure 12 ).

[0092] The second passivation layer 320 has a first pad hole 321 and a second pad hole 322. The vertical projection of the first pad hole 321 on the epitaxial layer 10 does not coincide with the vertical projection of all the first electrode holes 311 on the epitaxial layer 10. The vertical projection of the first pad hole 321 on the epitaxial layer 10 does not coincide with the vertical projection of all the second electrode holes 312 on the epitaxial layer 10. The vertical projection of the second pad hole 322 on the epitaxial layer 10 does not coincide with the vertical projection of all the first electrode holes 311 on the epitaxial layer 10. The vertical projection of the second pad hole 322 on the epitaxial layer 10 does not coincide with the vertical projection of all the second electrode holes 312 on the epitaxial layer 10.

[0093] Step 4011: Prepare the first pad 410 and the second pad 420 on the side of the second passivation layer 320 opposite to the first passivation layer 310 (see...). Figure 13 ).

[0094] The first pad 410 passes through the first pad hole 321 and contacts the first electrode 210, and the second pad 420 passes through the second pad hole 322 and contacts the second electrode 220.

[0095] Step 4012: Prepare the third passivation layer 330 (see...) Figure 1 ).

[0096] The third passivation layer 330 is located on the side of the second passivation layer 320 that faces away from the first passivation layer 310. The third passivation layer 330 covers the gap between the first pad 410 and the second passivation layer 320, as well as the gap between the second pad 420 and the second passivation layer 320.

[0097] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0098] The above is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above through embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.

Claims

1. A light-emitting diode chip, characterized in that, include: Epitaxial layer (10), first electrode (210), second electrode (220), first passivation layer (310), second passivation layer (320), first pad (410) and second pad (420); The first passivation layer (310) is located on one side of the epitaxial layer (10), and the first passivation layer (310) has a first electrode hole (311) and a second electrode hole (312). The first electrode (210) is located on the side of the first passivation layer (310) facing away from the epitaxial layer (10), and the first electrode (210) is connected to the epitaxial layer (10) through the first electrode hole (311); The second electrode (220) is located on the side of the first passivation layer (310) facing away from the epitaxial layer (10), and the second electrode (220) is connected to the epitaxial layer (10) through the second electrode hole (312); The second passivation layer (320) is located on the side of the first passivation layer (310) facing away from the epitaxial layer (10), and the second passivation layer (320) has a first pad hole (321) and a second pad hole (322). The first pad (410) penetrates the first pad hole (321) and contacts the first electrode (210), and the second pad (420) penetrates the second pad hole (322) and contacts the second electrode (220); The vertical projection of the first pad hole (321) on the epitaxial layer (10) does not coincide with the vertical projection of all the first electrode holes (311) on the epitaxial layer (10), and the vertical projection of the first pad hole (321) on the epitaxial layer (10) does not coincide with the vertical projection of all the second electrode holes (312) on the epitaxial layer (10). The vertical projection of the second pad hole (322) on the epitaxial layer (10) does not coincide with the vertical projection of all the first electrode holes (311) on the epitaxial layer (10).

2. The light-emitting diode chip according to claim 1, characterized in that, The materials of the first pad (410) and the second pad (420) do not include aluminum or silver, and the materials of the first electrode (210) and the second electrode (220) respectively include aluminum or silver.

3. The light-emitting diode chip according to claim 1, characterized in that, The first pad (410) and the second pad (420) are composed of an adhesion layer, a fusion layer and a bonding layer stacked in sequence.

4. The light-emitting diode chip according to claim 3, characterized in that, The thickness of the fusion layer is 8-12 times the thickness of the adhesion layer.

5. The light-emitting diode chip according to claim 3, characterized in that, The thickness of the fusion layer is 2-4 times the thickness of the bonding layer.

6. The light-emitting diode chip according to claim 3, characterized in that, The fusion layer material is nickel, and the bonding layer material is gold.

7. The light-emitting diode chip according to any one of claims 1 to 6, characterized in that, The light-emitting diode chip also includes a third passivation layer (330). The third passivation layer (330) is located on the side of the second passivation layer (320) facing away from the first passivation layer (310). The third passivation layer (330) has a third electrode hole (331) and a fourth electrode hole (332). The third electrode hole (331) exposes at least a portion of the first pad (410), and the fourth electrode hole (332) exposes at least a portion of the second pad (420).

8. The light-emitting diode chip according to any one of claims 1 to 6, characterized in that, The light-emitting diode chip also includes a third electrode (230) and a fourth electrode (240). The first electrode (210) is connected to the epitaxial layer (10) through the third electrode (230); The second electrode (220) is connected to the fourth electrode (240) and the epitaxial layer (10).

9. The light-emitting diode chip according to any one of claims 1 to 6, characterized in that, The inner walls of the first electrode hole (311) and the second electrode hole (312) are inclined surfaces, and the opening size of the first electrode hole (311) and the second electrode hole (312) facing away from the epitaxial layer (10) is larger than the opening size facing the epitaxial layer (10).

10. A method for fabricating a light-emitting diode chip, characterized in that, include: Prepare an epitaxial layer (10); A third electrode (230) and a fourth electrode (240) are fabricated on one side of the epitaxial layer (10). A first passivation layer (310) is prepared on one side of the epitaxial layer (10). The first passivation layer (310) has a first electrode hole (311) and a second electrode hole (312). The first electrode hole (311) is opposite to the third electrode (230), and the second electrode hole (312) is opposite to the fourth electrode (240). A first electrode (210) and a second electrode (220) are prepared on the side of the first passivation layer (310) opposite to the epitaxial layer (10). The first electrode (210) is connected to the corresponding third electrode (230) through the first electrode hole (311), and the second electrode (220) is connected to the corresponding fourth electrode (240) through the second electrode hole (312). A second passivation layer (320) is prepared on the side of the first passivation layer (310) opposite to the epitaxial layer (10). The second passivation layer (320) has a first pad hole (321) and a second pad hole (322). The vertical projection of the first pad hole (321) on the epitaxial layer (10) does not coincide with the vertical projection of all the first electrode holes (311) on the epitaxial layer (10). The vertical projection of the first pad hole (321) on the epitaxial layer (10) does not coincide with the vertical projection of all the second electrode holes (312) on the epitaxial layer (10). The vertical projection of the second pad hole (322) on the epitaxial layer (10) does not coincide with the vertical projection of all the first electrode holes (311) on the epitaxial layer (10). The vertical projection of the second pad hole (322) on the epitaxial layer (10) does not coincide with the vertical projection of all the second electrode holes (312) on the epitaxial layer (10). A first pad (410) and a second pad (420) are prepared on the side of the second passivation layer (320) opposite to the first passivation layer (310), such that the first pad (410) contacts the first electrode (210) through the first pad hole (321), and the second pad (420) contacts the second electrode (220) through the second pad hole (322).

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