Memory cell structure using a back-side metal cross-coupling structure

Abstract

In one aspect, a semiconductor memory cell includes a first inverter and a second inverter. The first inverter includes a top field effect transistor (FET) and a bottom FET in a first complementary field effect transistor (CFET) structure. The first complementary FET (CFET) structure has a first common gate that serves as an input node of the first inverter. The second inverter includes a top FET and a bottom FET in a second complementary CFET structure. The second complementary CFET structure has a second common gate that serves as an input node of the second inverter. The first inverter and the second inverter are cross-coupled to each other using a backside metal (BM) structure. The top FET and the bottom FET can be N-type and P-type respectively, or vice versa. The memory cell can include a transmission gate using the top FETs of two additional CFET structures, where the bottom FETs are disabled, or vice versa. The disabled FETs can be disabled during the wafer process by suppressing the growth of the source / drain epitaxial regions and / or by removing the channel via etching and dielectric filling.

Description

Background Technology

[0001] 1. Technical Field

[0002] This disclosure relates generally to semiconductor wafer processes, and more specifically to compact memory cells using a back-side metal cross-coupling structure and methods for manufacturing the same.

[0003] 2. Related technical descriptions

[0004] Integrated circuit (IC) technology has made significant strides in improving computing power through the miniaturization of electronic components. IC devices can be implemented as IC chips, which have a collection of circuits integrated on them. These IC devices include multiple active and passive components (e.g., transistors, diodes, capacitors, inductors, and / or resistors) and contact and interconnect layers above the active and passive components. In some aspects, the contacts and interconnects of the IC device are formed on the active and passive components on the front side of the IC device. As the size of the IC device and the components formed thereon become smaller, the available area for forming the contacts and interconnects also becomes smaller. Therefore, the wiring complexity and / or parasitic resistance and capacitance of the contacts and interconnects may increase, and thus the manufacturing cost or performance of the IC device may be negatively affected. Summary of the Invention

[0005] The following is a simplified summary of the invention relating to one or more aspects disclosed herein. Therefore, this summary should not be considered an exhaustive overview relating to all conceived aspects, nor should it be considered to identify key or decisive elements relating to all conceived aspects or to depict the scope associated with any particular aspect. Thus, the sole purpose of this summary is to present, in a simplified form, certain concepts relating to one or more aspects involving the mechanisms disclosed herein, prior to the detailed description presented below.

[0006] In one aspect, a semiconductor device includes: a memory cell comprising: a first inverter including a first top field-effect transistor (FET) and a first bottom FET in a first complementary field-effect transistor (CFET) structure having a first common gate as an input node of the first inverter; and a second inverter including a second top FET and a second bottom FET in a second complementary CFET structure having a second common gate as an input node of the second inverter, wherein the output node of the first inverter is coupled to the input node of the second inverter using a first back metal (BM) structure, and the output node of the second inverter is coupled to the input node of the first inverter using a second BM structure.

[0007] In one aspect, a method for providing a semiconductor device including a memory cell includes: providing a first inverter including a first top FET and a first bottom FET in a first CFET structure having a first common gate as an input node of the first inverter; providing a second inverter including a second top FET and a second bottom FET in a second complementary CFET structure having a second common gate as an input node of the second inverter; providing a first BM structure coupling an output node of the first inverter to the input node of the second inverter; and providing a second BM structure coupling an output node of the second inverter to the input node of the first inverter.

[0008] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0009] A more complete understanding of the various aspects of this disclosure and its many accompanying advantages will be readily available when considered in conjunction with the following detailed description taken in conjunction with the accompanying drawings, wherein similar reference numerals denote similar parts, and the drawings are given for illustrative purposes only and do not constitute any limitation on this disclosure.

[0010] Figure 1 An example of a nanosheet field-effect transistor (FET) is shown.

[0011] Figure 2 It is a cross-sectional view of a semiconductor structure including a substrate according to various aspects of this disclosure, on which a pair of gate structures have been fabricated.

[0012] Figures 3A to 3D The image shows a cross-section of a semiconductor structure according to various aspects of this disclosure, illustrating structures produced by various techniques of disabling CFET stacking for a single FET.

[0013] Figure 4A and Figure 4B This is a simplified top view of a semiconductor structure of a compact memory cell using a back-side metal cross-coupling structure according to various aspects of this disclosure.

[0014] Figures 4C to 4F This is a cross-sectional view of a semiconductor structure of a compact memory cell using a back-side metal cross-coupling structure according to various aspects of this disclosure.

[0015] Figure 5A and Figure 5B This is a simplified top view of a semiconductor structure of a compact memory cell using a back-side metal cross-coupling structure according to various aspects of this disclosure.

[0016] Figures 5C to 5F This is a cross-sectional view of a semiconductor structure of a compact memory cell using a back-side metal cross-coupling structure according to various aspects of this disclosure.

[0017] Figure 6 This is a flowchart illustrating a portion of a simplified wafer process for manufacturing a compact memory cell using a back-side metal cross-coupling structure, according to various aspects of this disclosure.

[0018] Figure 7 This is a flowchart illustrating a method for manufacturing a semiconductor device including a memory cell according to various aspects of this disclosure.

[0019] Figure 8 Mobile devices according to some examples of this disclosure are illustrated.

[0020] Figure 9 Various electronic devices that can be integrated with any of the aforementioned integrated devices or semiconductor devices are illustrated according to various examples of this disclosure.

[0021] By convention, the features depicted in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. Furthermore, similar reference numerals are used throughout the specification and drawings to represent similar features. Detailed Implementation

[0022] In one aspect, a semiconductor memory cell includes a first inverter and a second inverter. The first inverter includes a top field-effect transistor (FET) and a bottom FET in a first complementary field-effect transistor (CFET) structure having a first common gate as the input node of the first inverter. The second inverter includes a top FET and a bottom FET in a second complementary CFET structure having a second common gate as the input node of the second inverter. The first and second inverters are cross-coupled to each other using a back metal (BM) structure. The top FET and the bottom FET can be N-type and P-type, respectively, or vice versa. The memory cell may include a transmission gate using a top FET with two additional CFET structures, wherein the bottom FET is disabled, or vice versa. The disabled FET can be disabled during wafer fabrication by suppressing the growth of the source / drain epitaxial regions and / or by removing the channel via etching and dielectric filling.

[0023] Various aspects of this disclosure are provided in the following description and accompanying drawings of various examples provided for illustrative purposes. Alternative aspects may be devised without departing from the scope of this disclosure. Additionally, well-known elements of this disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of this disclosure.

[0024] The various aspects as a whole relate to semiconductor structural devices and methods for manufacturing semiconductor structural devices. Some aspects more specifically relate to compact memory cells that utilize full back-side connectivity to reduce cell area, reduce bit line resistance, reduce bit line capacitance, or combinations thereof.

[0025] Specific aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. Using back metal to cross-connect a pair of CFET inverters enables a very compact memory cell layout. Furthermore, by disabling unused top or bottom FETs of the CFET pair used for transmission gates, for example, by preventing the growth of epitaxial source / drain regions on either side of the channel of the unused FETs, the memory cell layout can be made even more compact.

[0026] The terms “exemplary” and / or “example” are used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” and / or “example” is not necessarily to be construed as superior to or better than other aspects. Similarly, the term “aspects of this disclosure” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed.

[0027] Those skilled in the art will understand that any of a variety of different techniques and methods can be used to represent the information and signals described below. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the following description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof, depending in part on the specific application, in part on the desired design, in part on the corresponding technology, and so on.

[0028] Furthermore, many aspects are described according to a sequence of actions to be performed by elements of, for example, a computing device. It will be appreciated that the various actions described herein can be performed by specific circuitry (e.g., an application-specific integrated circuit (ASIC)), by program instructions executed by one or more processors, or by a combination of both. Additionally, the sequence of actions described herein can be considered to be entirely embodied in any form of non-transitory computer-readable storage medium storing a corresponding set of computer instructions that, when executed, will cause or command the associated processor of the device to perform the functionality described herein. Therefore, various aspects of this disclosure can be embodied in a variety of different forms, all of which are contemplated within the scope of the claimed subject matter. Furthermore, for each aspect described herein, any corresponding form of any such aspect may be described herein as, for example, "logic configured to perform the described actions."

[0029] Figure 1 A nanosheet field-effect transistor (FET) 100 is illustrated. Figure 1 The illustrated nanosheet FET 100 is constructed on a substrate 102 (e.g., silicon) and comprises an assembly of three nanosheets 104 extending through a gate-all-around (GAA) structure 106. One end of each of the three nanosheets 104 is electrically connected together in a first heavily doped epitaxial (EPI) structure (not shown) to form a first source / drain (S / D) region 108, and the other ends of each nanosheet 104 are electrically connected together in a second heavily doped EPI structure (also not shown) to form a second S / D region 110. The gate structure is isolated from the substrate 102 by an oxide isolation region 112. The nanosheets 104 are channels through which charge carriers travel through the GAA structure 106 from the first S / D region 108 to the second S / D region 110, and are therefore referred to herein as “nanosheet channels”. The nanosheets 104 are electrically insulated from the GAA structure 106 by a dielectric layer 114 surrounding the portions of the nanosheets 104 extending through the GAA structure 106.

[0030] For each pair of S / D regions on either side of the gate, one S / D region can operate as a source and the other as a drain, or vice versa. Generally, the term "source" is used to refer to the S / D region connected to the source of charge carriers (i.e., for a PFET, the S / D region is connected to VDD; for an NFET, the S / D region is connected to VSS), and therefore whether the first S / D region 108 is the source or the second S / D region 110 is the source depends on their specific electrical connections.

[0031] exist Figure 1In the orientation shown, the bottom and top surfaces of substrate 102 are generally referred to as the “back side” and “front side” of the substrate. Therefore, generally speaking, the process of creating structures (e.g., GAA structures, channels, and S / D regions) on the front side of substrate 102 is called a “front side” process, and the process of creating structures on the back side of substrate 102 (or, if substrate 102 has been removed, creating structures below the front side structure) is called a “back side” process. Similarly, connections made during the front side process are called front side connections, and connections made during the back side process are called back side connections. Figure 1 The structure shown can be adapted to allow complete removal of substrate 102 to facilitate back-side connectivity.

[0032] Figure 2 This is a cross-sectional view of a semiconductor structure 200 including a substrate 202 according to various aspects of the present disclosure, on which a pair of gate structures have been fabricated. The gate structures, designated 204a and 204b, may be collectively referred to as gate structure 204 or individually as gate structure 204a and gate structure 204b. The gate structures 204 extend in the Y direction and are spaced apart from each other in the X direction. Gate structure 204a includes a metal gate structure 206a having spacers 208a on each side along the X direction, and a plurality of channels extending through the metal gate structure 206a and the spacers 208a. Figure 2 In the example shown, the top channel 210a is part of a top FET (TFET), the middle channel 212a is part of a middle dielectric isolation (MDI) structure, and the bottom channel 214a is part of a bottom FET (BFET). Similarly, the gate structure 204b includes a metal gate structure 206b having spacers 208b on each side along the X direction, and a plurality of channels extending through the metal gate structure 206b and the spacers 208b, wherein the top channel 210b is part of the top FET, the middle channel 212b is part of the middle dielectric isolation (MDI) structure, and the bottom channel 214b is part of the bottom FET.

[0033] exist Figure 2In the example shown, semiconductor structure 200 includes multiple S / D EPI regions, including top S / D EPI regions labeled 216a to 216c and bottom S / D EPI regions labeled 218a to 218c. A top channel 210a provides a channel between S / D EPI regions 216a and 216b, and a top channel 210b provides a channel between S / D EPI regions 216b and 216c. A bottom channel 214a provides a channel between S / D EPI regions 218a and 218b, and a bottom channel 214b provides a channel between S / D EPI regions 218b and 218c. Channels (i.e., channels 212a and 212b) that are part of the MDI structure are not connected to any S / D EPI region. Figure 2 In the example shown, the gate structure 204 is surrounded by an electrically insulating interlayer dielectric (ILD) 220.

[0034] It will be understood that the terms TFET and BFET refer to the top and bottom FETs of a CFET pair, and phrases such as "TFET-type" mean "FET of the same type as TFET," regardless of the type (e.g., N-type or P-type). It will also be understood that semiconductor structure 200 may use a P-type FET (PFET) as the top FET and an N-type FET (NFET) as the bottom FET, or vice versa, depending on the details of the wafer process. It will also be understood that although... Figure 2 The diagram shows top FET, bottom FET, and MDI structures with only one channel; however, in other embodiments, each of these structures may have more than one channel that is vertically stacked (i.e., in the Z direction) and separated from each other by gate and internal spacer structures. Using semiconductor structure 200 as an example, each gate structure 204 contains vertically stacked pairs of PFETs and NFETs that constitute a complementary FET (CFET) structure.

[0035] Since each gate structure 204 has a PFET / NFET pair, each gate structure 204 can implement inverter logic. For example, assuming the top FET is a PFET and the bottom FET is an NFET, gate structure 204a can be implemented as an inverter by connecting S / D EPI region 216a to VDD, S / D EPI region 218a to VSS, and S / D EPI region 216b to S / D EPI region 218b as the output of an inverter, wherein the input of the inverter is connected to metal gate structure 206a.

[0036] A static random access memory (SRAM) cell includes a pair of cross-coupled inverters, where the output of one inverter is connected to the bit line (BL) via a transmission gate (PG) controlled by the word line (WL). Therefore, a basic SRAM cell contains six transistors: a first PFET / NFET pair for one inverter, a second PFET / NFET pair for the other inverter, and a PFET / PFET pair or NFET / NFET pair for the transmission gate. It can be used... Figure 2 The CFET structure shown is used to construct a simple SRAM cell, but since the FETs are PFET / NFET pairs, this means there will be four NFETs and four PFETs (two for each gate structure 204), and either two NFETs or two PFETs will not be used, depending on whether the transmission gate is P-type or N-type. Therefore, Figure 2 The circuit shown can be adapted to provide one half of an inverter and a transmission gate, i.e., by disabling the unused PFET or NFET used for the gate structure 204 of the transmission gate structure. One way to disable the top or bottom FET is to omit the S / D EPI region from either side of the channel to be disabled. The resulting structure will vary depending on whether the top FET is an NFET or a PFET and whether the transmission gate is N-type or P-type, as... Figures 3A to 3D exemplified.

[0037] Figure 3A The resulting structure is shown when the top FET is an NFET, the bottom FET is a PFET, and the transmission gate is N-type. In this example, the bottom FET of the transmission gate has been disabled by preventing the growth of the S / D EPI region around the bottom channel.

[0038] Figure 3B The resulting structure is shown when the top FET is an NFET, the bottom FET is a PFET, and the transmission gate is P-type. In this example, the top FET of the transmission gate has been disabled by preventing the growth of the S / D EPI region around the top channel and by etching away the channel and filling it with dielectric material to create a top dielectric isolation (TDI) structure. However, in other specific implementations, either preventing S / D EPI growth or creating the TDI separately can be performed.

[0039] Figure 3C The resulting structure is shown when the top FET is a PFET, the bottom FET is an NFET, and the transmission gate is N-type. In this example, the top FET of the transmission gate has been disabled by preventing the growth of the S / D EPI region around the top channel and by etching away the channel and filling it with dielectric material to create a TDI structure.

[0040] Figure 3DThe resulting structure is shown when the top FET is a PFET, the bottom FET is an NFET, and the transmission gate is P-type. In this example, the bottom FET of the transmission gate has been disabled by preventing the growth of the S / D EPI region around the bottom channel.

[0041] Figure 4A and Figure 4B This is a simplified top view of a semiconductor structure 400 of a compact CFET memory cell using a back-side metal cross-coupled structure according to various aspects of this disclosure. Figure 4A The front connection is shown, and Figure 4B The rear connection is shown. Specifically, Figure 4A The components shown can be located in the vertical direction (e.g., the Z direction corresponding to the direction away from the drawing plane). Figure 4B Above the element shown. In some respects, Figure 4A and Figure 4B Some components of the semiconductor structure 400 are shown for illustrative purposes only, and may be configured... Figures 4A to 4B Other elements above and / or below the element shown, but... Figures 4A to 4B Not shown in the image.

[0042] exist Figures 4A to 4B In the example shown, semiconductor structure 400 includes four gate structures, labeled G1, G2, G3, and G4, each gate structure including a CFET pair with a top FET (TFET) and a bottom FET (BFET). The TFETs of G1 and G2 have channels connecting different regions of the first EPI layer EL1, the TFETs of G3 and G4 have channels connecting different regions of the second EPI layer EL2, the BFETs of G1 and G2 have channels connecting different regions of the third EPI layer EL3, and the BFET of G3 has a channel connecting different regions of the fourth EPI layer EL4. Figures 4A to 4B In the example shown, semiconductor structure 400 includes six front-side S / D contacts, labeled FC1, FC2, FC3, FC4, FC5, and FC6. Figures 4A to 4B In the example shown, the semiconductor structure 400 includes four back-side S / D contacts, labeled BC1, BC2, BC3, and BC4. Figures 4A to 4B In the example shown, semiconductor structure 400 includes two cross-connected structures, labeled CC1 and CC2. G2 and G3 are cross-coupled inverters. Figures 4A to 4B In the example shown, semiconductor structure 400 includes two vertical connectors (VCs), labeled VC1 and VC2. Each VC extends in the Z direction and, for example, connects the S / D region of the TFET to the S / D region of the BFET in the CFET pair by electrically connecting the FC to the BC below it.

[0043] The TFET of G2 is connected to the front power supply (FSP) via FC3, and the BFET of G2 is connected to the back power supply (BSP) via BC2. In some implementations, the TFET is an NFET, the BFET is a PFET, the FSP is VSS, and the BSP is VDD. In other implementations, the TFET is a PFET, the BFET is an NFET, the FSP is VDD, and the BSP is VSS. Figures 4A to 4B In the example shown, the transmission gate is made up of a TFET, and the BFET is disabled.

[0044] The outputs of the TFET and BFET of G2 are connected together via FC2, VC1, and BC1, and this output is connected to the gate of G3 via CC1. The TFET of G3 is connected to the FSP via FC4, and the BFET of G3 is connected to the BSP via BC3. The outputs of the TFET and BFET of G3 are connected together via FC5, VC2, and BC4, and this output is connected to the gate of G2 via CC2. The upper half of G1 is a transmission gate controlled by word line WL to connect the output of the inverter formed by G2 to the first bit line BL, and the lower half of G1 is disabled. The upper half of G4 is a transmission gate controlled by WL to connect the output of the inverter formed by G3 to the second bit line BL', and the lower half of G4 is disabled. Figures 4C to 4F The text shows more details about having Figures 4A to 4B Cross section AA at the indicated position BB CC and DD .

[0045] Figure 4C The semiconductor structure 400 according to various aspects of this disclosure passes through cross section AA A sectional view. For example... Figure 4C As shown, the top EPI layer EL1 exists on either side of the TFET of G1, which operates as a TFET-type transmission gate, and therefore in Figure 4C The middle is marked "PG", but the bottom EPI layer EL3 is not present around the BFET of G1, which disables the BFET of G1, therefore in Figure 4C The middle is marked "off". The outputs of the TFET and BFET transistors of G2 are through FC2, VC1 (which is in cross-section AA) (Outside the plane, and therefore shown in dashed outline) and BC1 are connected together. The output of the first inverter formed by the TFET and BFET of G2 is wired to the gate of the second inverter via BC1 and CC1.

[0046] Figure 4D The semiconductor structure 400 according to various aspects of this disclosure passes through a cross-section BB A sectional view. For example... Figure 4D As shown, the top EPI layer EL2 exists on either side of the TFET of G4, which operates as an N-type transmission gate, and therefore in Figure 4D The middle is marked "PG", but the bottom EPI layer EL4 is not present around the BFET of G4, which disables the BFET of G4, therefore in Figure 4D The middle is marked "off". The outputs of the TFET and BFET transistors of G3 are through FC5, VC2 (which is in cross-section BB). (Outside the plane, and therefore shown in dashed outline) and BC4 are connected together. The output of the second inverter, formed by the TFET and BFET of G3, is wired to the gate of the first inverter via BC4 and CC2.

[0047] Figure 4E The semiconductor structure 400 according to various aspects of this disclosure passes through a cross-section CC A sectional view. Figure 4E Cross-sections of G1 and G3 are shown, and it is also shown how the back connector CC1 is connected to the back of G3.

[0048] Figure 4F The semiconductor structure 400 according to various aspects of this disclosure passes through a cross-section DD A sectional view. Figure 4F Cross-sections of G2 and G4 are shown, and it is also shown how the back connector CC2 is attached to the back of G2.

[0049] Figure 5A and Figure 5B This is a simplified top view of a semiconductor structure 500 of a compact CFET memory cell using a back-side metal cross-coupled structure according to various aspects of this disclosure. Figure 5A The front connection is shown, and Figure 5B The rear connection is shown. Specifically, Figure 5A The components shown can be located in the vertical direction (e.g., the Z direction corresponding to the direction away from the drawing plane). Figure 5B Above the element shown. In some respects, Figure 5A and Figure 5B Some components of the semiconductor structure 500 are shown for illustrative purposes only, and may be configured... Figures 5A to 5B Other elements above and / or below the element shown, but... Figures 5A to 5B Not shown in the image.

[0050] exist Figures 5A to 5BIn the example shown, semiconductor structure 500 has a similar topology to semiconductor structure 400, and therefore the descriptions of structures with the same names G1 to G4, FC1 to FC6, BC1 to BC4, CC1 to CC2, VC1 to VC2, FSP, and BSP will not be repeated here. However, semiconductor structure 500 differs from semiconductor structure 400 in that, in semiconductor structure 500, the transmission gates are composed of BFETs, and TFETs are disabled. Therefore, the dimensions and locations of the EPI layers EL1 to EL4 in semiconductor structure 500 differ from those of the similarly named EPI layers EL1 to EL4 in semiconductor structure 400, and there are two TDI regions, namely TDI1 within G1 and TDI2 within G4. These differences are further explained in... Figures 5C to 5F The cross sections EE shown respectively FF GG and HH It's easier to see in the middle.

[0051] Figure 5C The semiconductor structure 500 according to various aspects of this disclosure passes through a cross-section EE A sectional view. For example... Figure 5C As shown, the bottom EPI layer EL3 exists on either side of the BFET of G1, which operates as a BFET-type transmission gate, and therefore in Figure 5C The middle is marked "PG", but the top EPI layer EL1 is not present around the TFET of G1, which is in Figure 5C The TDI1 has been replaced in G2. The outputs of the TFET and BFET transistors in G2 are connected through FC2 and VC1 (which has a cross-sectional area EE). (Outside the plane, and therefore shown in dashed outline) and BC1 are connected together. The output of the first inverter formed by the TFET and BFET of G2 is wired to the gate of the second inverter via BC1 and CC1.

[0052] Figure 5D The semiconductor structure 500 according to various aspects of this disclosure passes through a cross section FF A sectional view. For example... Figure 5D As shown, the bottom EPI layer EL4 exists on either side of the BFET of G4, operating as a BFET-type transmission gate, and therefore in Figure 5D The middle is marked "PG", but the top EPI layer EL4 is not present around the TFET of G4, which is in Figure 5D The TDI2 has been replaced in G3. The outputs of the TFET and BFET transistors in G3 are connected through FC5 and VC2 (which has a cross-sectional area of ​​FF). (Outside the plane, and therefore shown in dashed outline) and BC4 are connected together. The output of the second inverter, formed by the TFET and BFET of G3, is wired to the gate of the first inverter via BC4 and CC2.

[0053] Figure 5E The semiconductor structure 500 according to various aspects of this disclosure is permeated through a cross-section GG A sectional view. Figure 5E Cross-sections of G1 (showing TDI1) and G3 are shown, and how the back connector CC1 is connected to the back of G3 is shown.

[0054] Figure 5F The semiconductor structure 500 according to various aspects of this disclosure is permeated through a cross-section HH A sectional view. Figure 5F Cross-sections of G2 and G4 (TDI2 is shown) are illustrated, and how the back connector CC2 is attached to the back of G2 is shown.

[0055] Figure 6 This illustrates the methods for manufacturing according to various aspects of this disclosure. Figures 4A to 4F and Figures 5A to 5F A flowchart illustrating a simplified portion of the wafer fabrication process for the structure shown. (See attached diagram.) Figure 6 As shown, process 600 may include forming a substrate EPI at block 602, for example... Figure 2 The substrate 202 is shown. Process 600 may include forming an active region at block 604.

[0056] Process 600 may optionally include a TDI process at block 606. In some aspects, forming the TDI includes, for example, removing the top FET channel by an etching step, backfilling the resulting cavity with a dielectric, and optional planarization steps, such as chemical / mechanical polishing (CMP). In some aspects, this optional step, such as..., is performed when the memory cell topology uses a BFET-type transmission gate and therefore the TFET is disabled or removed from the gate forming the transmission gate. Figures 5A to 5F As shown.

[0057] Process 600 may include forming a gate structure at block 608, for example Figures 4A to 5F G1 to G4 in the diagram. Process 600 may include forming an MDI at block 610, for example... Figures 4A to 5F The MDI area in the middle. Process 600 may include forming an S / D groove at frame 612, for example, in Figures 4A to 5F The left and right sides of the gate structures G1 to G4 in the middle form volumes. Process 600 may include forming internal spacers at block 614, for example... Figure 2 Spacers 208a and 208b in the middle.

[0058] Process 600 may optionally include a BFET disable process at block 616. In some aspects, disabling the BFET includes using a dummy SD mask to prevent the formation of the bottom EPI structure, thereby depositing dielectric material up to MDI, and forming a cover spacer. In some aspects, this optional step, such as..., is performed when the memory cell topology uses a TFET-type transmission gate and therefore the BFET is disabled or removed from the gate forming the transmission gate. Figures 4A to 4F As shown.

[0059] Process 600 may include forming a bottom S / D EPI structure at block 618, for example, Figures 4A to 5F The bottom EPI layers EL3 and EL4 are located in the middle. Process 600 may include forming a top S / D EPI structure at block 620, for example, Figures 4A to 5F The top EPI layers EL1 and EL2 are in the middle. Process 600 may include depositing a zero-layer ILD (ILD0) at box 622, for example, Figure 2 ILD220 in the middle. Process 600 may include forming a replacement metal gate (RMG) structure at block 624. Process 600 may include patterning and etching at block 626 to form a vertical connector (VC) (e.g., Figures 4A to 5F The process 600 may include metallizing the VCs and front contacts at frame 628. Process 600 may include forming front vias (FSVs) at frame 630, which may be S / D vias (Vd) and / or gate vias (Vg). Process 600 may include forming a front metal (FM) structure at frame 632 and performing the remaining front process steps. In some aspects, the FM structure may include a front metal zero (FM0) structure, but other metal levels may be used additionally or alternatively.

[0060] Process 600 may include bonding the wafer to a carrier at block 634. Process 600 may include flipping the wafer and removing the substrate via a CMP process at block 636. Process 600 may include silicon removal and backside ILD filling processes at block 638. Process 600 may include forming a direct backside contact (BSC) at block 640, for example... Figures 4A to 5F BC1 to BC4 in the diagram. Process 600 may include forming a bidirectional cross connector at frame 642 using back metal (BM), for example, Figures 4A to 5F CC1 and CC2 in the diagram. In some aspects, CC1 and CC2 may include a back metal zero (BM0) structure, but other metal layers may be used additionally or alternatively. The remaining process steps are then performed, as shown in box 644.

[0061] Figure 7This is a flowchart of an example process 700 associated with a memory cell structure using a back-side metal cross-coupling structure, according to various aspects of this disclosure. Figure 7 As shown, process 700 may include providing a first inverter at block 710, the first inverter including a first top FET and a first bottom FET in a first CFET structure, the first CFET structure having a first common gate as the input node of the first inverter, for example including... Figure 4A The inverters of the top and bottom FETs in G2.

[0062] like Figure 7 Further shown, process 700 may include providing a second inverter at block 720, the second inverter including a second top FET and a second bottom FET in a second complementary CFET structure, the second complementary CFET structure having a second common gate as the input node of the second inverter, for example including... Figure 4A The inverters of the top and bottom FETs in G3.

[0063] like Figure 7 As further shown, process 700 may include providing a first back metal (BM) structure at block 730, which couples the output node of the first inverter to the input node of the second inverter, for example, Figure 4B CC1 in the middle.

[0064] like Figure 7 As further shown, process 700 may include providing a second BM structure at block 740, which couples the output node of the second inverter to the input node of the first inverter, for example... Figure 4B CC2 in the middle.

[0065] In some aspects, the output node of the first inverter includes a first vertical connector that electrically couples the source / drain (S / D) region of the first top FET to the S / D region of the first bottom FET (e.g., Figure 4A (VC1 in the second inverter), and the output node of the second inverter includes a second vertical connector (e.g., VC1 in the second inverter) that electrically couples the S / D region of the second top FET to the S / D region of the second bottom FET. Figure 4A (VC2 in the middle).

[0066] In some aspects, process 700 includes providing a transmission gate, which includes a third top FET in a third CFET structure (e.g., Figure 4A In G1) and the fourth top FET in the fourth CFET structure (e.g., Figure 4A (G4 in the middle).

[0067] In some respects, process 700 includes removing each of the third bottom FET in the third CFET structure and the fourth bottom FET in the fourth CFET structure.

[0068] In some respects, each of the third bottom FET in the third CFET structure and the fourth bottom FET in the fourth CFET structure is incomplete and nonfunctional (e.g., by preventing EL3 from being in Figure 4B Growth on either side of G1 in the middle, and prevent EL4 from growing in Figure 4B Growth on either side of G3 in the middle.

[0069] In some aspects, process 700 includes providing a transmission gate, which includes a third bottom FET in a third CFET structure (e.g., Figure 5A In G1) and the fourth bottom FET in the fourth CFET structure (e.g., Figure 5A (G4 in the middle).

[0070] In some aspects, process 700 includes removing each of the third top FET in the third CFET structure and the fourth top FET in the fourth CFET structure, for example, thereby producing Figure 5A TDI1 and TDI2 in the middle.

[0071] In some respects, each of the third top FET in the third CFET structure and the fourth top FET in the fourth CFET structure is incomplete and nonfunctional (e.g., by preventing EL1 from being in Figure 5A Growth on either side of G1 in the middle, and prevention of EL2 in Figure 5A Growth on either side of G4 in the middle.

[0072] In some respects, the top FET includes an N-type FET, and the bottom FET includes a P-type FET. In these respects, the FSP can be a VSS, and the BSP can be a VDD.

[0073] In some respects, the top FET includes a P-type FET, and the bottom FET includes an N-type FET. In these respects, the FSP can be VDD, and the BSP can be VSS.

[0074] Process 700 may include additional embodiments, such as those described below and / or any single embodiment or any combination of embodiments described in conjunction with one or more other processes described elsewhere herein. Although Figure 7 An example block for process 700 is shown, but in some specific implementations, it differs from... Figure 7Compared to the boxes depicted, process 700 may include additional boxes, fewer boxes, different boxes, or boxes arranged in a different manner. Additionally or alternatively, two or more boxes in process 700 may be executed in parallel.

[0075] Figure 8 A mobile device 800 according to various aspects of this disclosure is illustrated. In some aspects, the mobile device 800 may be implemented by including one or more IC devices manufactured based on the examples described in this disclosure.

[0076] In some aspects, the mobile device 800 can be configured as a wireless communication device. As shown, the mobile device 800 includes a processor 802. The processor 802 is communicatively coupled to a memory 804 via a link, which can be a die-to-die or chip-to-chip link. The mobile device 800 also includes a display 806 and a display controller 808, wherein the display controller 808 is coupled to the processor 802 and the display 806. The mobile device 800 may include an input device 810 (e.g., a physical or virtual keyboard), a power supply 812 (e.g., a battery), a speaker 814, a microphone 816, and a wireless antenna 818. In some aspects, the power supply 812 may directly or indirectly provide the power supply voltage for operating some or all of the components of the mobile device 800.

[0077] In some respects, Figure 8 It may include a decoder / decoder (CODEC) 820 (e.g., an audio and / or voice CODEC) coupled to processor 802; a speaker 814 and a microphone 816 coupled to CODEC 820; and a wireless circuit 822 (which may include a modem, RF circuitry, filters, etc.) coupled to wireless antenna 818 and to processor 802.

[0078] In some aspects, one or more of the processor 802, display controller 808, memory 804, CODEC 820, and wireless circuit 822 may include one or more IC devices, the one or more IC devices including semiconductor structures manufactured according to the examples described in this disclosure.

[0079] It should be noted that, although Figure 8 Mobile device 800 is described, but similar architectures can be used to implement devices including set-top boxes, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), fixed location data units, computers, laptops, tablets, communication devices, mobile phones, or other similar devices.

[0080] Figure 9Examples of various electronic devices that may integrate any of the following: the aforementioned devices, semiconductor devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, interposer packages, stacked package (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 902, laptop computer device 904, fixed-location terminal device 906, wearable device 908, or motor vehicle 910 may include semiconductor device 900 as described herein (which may include semiconductor structures 400 and 500). Figure 9 The illustrated devices 902, 904, 906, and 908, as well as vehicle 910, are merely exemplary. Other devices or apparatuses may also feature semiconductor device 900, including but not limited to a group of devices comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0081] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to have more features than those explicitly mentioned in each clause. Rather, the various aspects of this disclosure may include fewer features than those in the individual example clauses disclosed. Therefore, the following clauses should be regarded accordingly as incorporated into the description, where each clause may serve as a separate example. Although each dependent clause may refer in the clause to a specific combination with one of the other clauses, the aspect of that dependent clause is not limited to that specific combination. It should be understood that other example clauses may also include combinations of aspects of a dependent clause with the subject matter of any other dependent or independent clause, or combinations of any feature with other dependent and independent clauses. The various aspects disclosed herein explicitly include these combinations unless explicitly stated or readily inferred that a particular combination is not intended for use (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is contemplated that aspects of a clause may be included in any other independent clause, even if that clause does not directly depend on the independent clause.

[0082] Specific implementation examples are described in the following numbered clauses: Clause 1. A semiconductor device comprising: a memory cell including: a first inverter including a first top field-effect transistor (FET) and a first bottom FET in a first complementary field-effect transistor (CFET) structure, the first complementary FET (CFET) structure having a first common gate as an input node of the first inverter; and a second inverter including a second top FET and a second bottom FET in a second complementary CFET structure, the second complementary CFET structure having a second common gate as an input node of the second inverter, wherein the output node of the first inverter is coupled to the input node of the second inverter using a first back metal (BM) structure, and the output node of the second inverter is coupled to the input node of the first inverter using a second BM structure.

[0083] Clause 2. The semiconductor device according to Clause 1, wherein the output node of the first inverter includes a first vertical connector electrically coupling the source / drain (S / D) region of the first top FET to the S / D region of the first bottom FET, and the output node of the second inverter includes a second vertical connector electrically coupling the S / D region of the second top FET to the S / D region of the second bottom FET.

[0084] Clause 3. The semiconductor device according to any one of Clauses 1 to 2, wherein the memory cell further comprises a transmission gate, the transmission gate comprising a third top FET in a third CFET structure and a fourth top FET in a fourth CFET structure.

[0085] Clause 4. The semiconductor device according to Clause 3, wherein each of the third bottom FET in the third CFET structure and the fourth bottom FET in the fourth CFET structure is removed.

[0086] Clause 5. The semiconductor device according to any one of Clauses 3 to 4, wherein each of the third bottom FET in the third CFET structure and the fourth bottom FET in the fourth CFET structure is incomplete and / or nonfunctional.

[0087] Clause 6. The semiconductor device according to any one of Clauses 1 to 5, wherein the memory cell further comprises a transmission gate, the transmission gate comprising a third bottom FET in a third CFET structure and a fourth bottom FET in a fourth CFET structure.

[0088] Clause 7. The semiconductor device according to Clause 6, wherein each of the third top FET in the third CFET structure and the fourth top FET in the fourth CFET structure is removed.

[0089] Clause 8. The semiconductor device according to any one of Clauses 6 to 7, wherein each of the third top FET in the third CFET structure and the fourth top FET in the fourth CFET structure is incomplete and / or nonfunctional.

[0090] Clause 9. The semiconductor device according to any one of Clauses 1 to 8, wherein each of the first top FET and the second top FET comprises an N-type FET, and wherein each of the first bottom FET and the second bottom FET comprises a P-type FET.

[0091] Clause 10. The semiconductor device according to any one of Clauses 1 to 9, wherein each of the first top FET and the second top FET comprises a P-type FET, and wherein each of the first bottom FET and the second bottom FET comprises an N-type FET.

[0092] Clause 11. A semiconductor device according to any one of Clauses 1 to 10, wherein at least one of the first BM structure and the second BM structure includes a back metal layer zero (BM0).

[0093] Clause 12. A semiconductor device according to any one of Clauses 1 to 11, wherein the semiconductor device is included in a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, and devices in motor vehicles.

[0094] Clause 13. A method for manufacturing a semiconductor device including a memory cell, the method comprising: providing a first inverter, the first inverter including a first top field-effect transistor (FET) and a first bottom FET in a first complementary field-effect transistor (CFET) structure, the first complementary FET (CFET) structure having a first common gate as an input node of the first inverter; providing a second inverter, the second inverter including a second top FET and a second bottom FET in a second complementary CFET structure, the second complementary CFET structure having a second common gate as an input node of the second inverter; providing a first back metal (BM) structure, the first back metal (BM) structure coupling an output node of the first inverter to the input node of the second inverter; and providing a second BM structure, the second BM structure coupling an output node of the second inverter to the input node of the first inverter.

[0095] Clause 14. The method according to Clause 13, wherein the output node of the first inverter includes a first vertical connector electrically coupling the source / drain (S / D) region of the first top FET to the S / D region of the first bottom FET, and the output node of the second inverter includes a second vertical connector electrically coupling the S / D region of the second top FET to the S / D region of the second bottom FET.

[0096] Clause 15. The method according to any one of Clauses 13 to 14, the method further comprising providing a transmission gate, the transmission gate comprising a third top FET in a third CFET structure and a fourth top FET in a fourth CFET structure.

[0097] Clause 16. The method according to Clause 15, the method further comprising removing each of the third bottom FET in the third CFET structure and the fourth bottom FET in the fourth CFET structure.

[0098] Clause 17. The method according to any one of Clauses 15 to 16, wherein each of the third bottom FET in the third CFET structure and the fourth bottom FET in the fourth CFET structure is incomplete and / or nonfunctional.

[0099] Clause 18. The method according to any one of Clauses 13 to 17, the method further comprising providing a transmission gate, the transmission gate comprising a third bottom FET in a third CFET structure and a fourth bottom FET in a fourth CFET structure.

[0100] Clause 19. The method according to Clause 18, the method further comprising removing each of the third top FET in the third CFET structure and the fourth top FET in the fourth CFET structure.

[0101] Clause 20. The method according to any one of Clauses 18 to 19, wherein each of the third top FET in the third CFET structure and the fourth top FET in the fourth CFET structure is incomplete and / or nonfunctional.

[0102] Clause 21. The method according to any one of Clauses 13 to 20, wherein each of the first top FET and the second top FET comprises an N-type FET, and wherein each of the first bottom FET and the second bottom FET comprises a P-type FET.

[0103] Clause 22. The method according to any one of Clauses 13 to 21, wherein each of the first top FET and the second top FET comprises a P-type FET, and wherein each of the first bottom FET and the second bottom FET comprises an N-type FET.

[0104] Clause 23. The method according to any one of Clauses 13 to 22, wherein at least one of the first BM structure and the second BM structure includes a back metal layer zero (BM0).

[0105] Clause 24. The method according to any one of Clauses 13 to 23, further comprising incorporating the semiconductor device into an apparatus selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, and devices in motor vehicles.

[0106] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0107] Furthermore, those skilled in the art will understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0108] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0109] The methods, sequences, and / or algorithms described in conjunction with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or a combination of both. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. Example storage media are coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal (e.g., a UE). Alternatively, the processor and storage medium may reside as discrete components in the user terminal.

[0110] In one or more examples, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, which includes any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and is accessible to a computer. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of a medium. As used herein, disks and optical discs include: compact optical discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0111] While the foregoing disclosure illustrates exemplary aspects of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. The functions, steps, and / or actions of the method claims according to the aspects of this disclosure described herein need not be performed in any particular order. Furthermore, although elements of this disclosure may be described or claimed in the singular, the plural form may also be considered unless explicitly stated as limited to the singular.

Claims

1. A semiconductor device, the semiconductor device comprising: Memory unit, the memory unit comprising: A first inverter, comprising a first top field-effect transistor (FET) and a first bottom FET in a first complementary field-effect transistor (CFET) structure, the first complementary FET (CFET) structure having a first common gate serving as the input node of the first inverter; and The second inverter includes a second top FET and a second bottom FET in a second complementary CFET structure, the second complementary CFET structure having a second common gate as the input node of the second inverter. The output node of the first inverter is coupled to the input node of the second inverter using a first back metal (BM) structure, and the output node of the second inverter is coupled to the input node of the first inverter using a second BM structure.

2. The semiconductor device of claim 1, wherein the output node of the first inverter includes a first vertical connector electrically coupling the source / drain (S / D) region of the first top FET to the S / D region of the first bottom FET, and the output node of the second inverter includes a second vertical connector electrically coupling the S / D region of the second top FET to the S / D region of the second bottom FET.

3. The semiconductor device of claim 1, wherein the memory cell further comprises a transmission gate, the transmission gate comprising a third top FET in a third CFET structure and a fourth top FET in a fourth CFET structure.

4. The semiconductor device of claim 3, wherein each of the third bottom FET in the third CFET structure and the fourth bottom FET in the fourth CFET structure is removed.

5. The semiconductor device of claim 3, wherein each of the third bottom FET in the third CFET structure and the fourth bottom FET in the fourth CFET structure is incomplete and / or nonfunctional.

6. The semiconductor device of claim 1, wherein the memory cell further comprises a transmission gate, the transmission gate comprising a third bottom FET in a third CFET structure and a fourth bottom FET in a fourth CFET structure.

7. The semiconductor device of claim 6, wherein each of the third top FET in the third CFET structure and the fourth top FET in the fourth CFET structure is removed.

8. The semiconductor device of claim 6, wherein each of the third top FET in the third CFET structure and the fourth top FET in the fourth CFET structure is incomplete and / or nonfunctional.

9. The semiconductor device of claim 1, wherein each of the first top FET and the second top FET comprises an N-type FET, and wherein each of the first bottom FET and the second bottom FET comprises a P-type FET.

10. The semiconductor device of claim 1, wherein each of the first top FET and the second top FET comprises a P-type FET, and wherein each of the first bottom FET and the second bottom FET comprises an N-type FET.

11. The semiconductor device of claim 1, wherein at least one of the first BM structure and the second BM structure includes a back metal layer zero (BM0).

12. The semiconductor device of claim 1, wherein the semiconductor device is included in a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, and devices in motor vehicles.

13. A method for manufacturing a semiconductor device including memory cells, the method comprising: A first inverter is provided, the first inverter including a first top field-effect transistor (FET) and a first bottom FET in a first complementary field-effect transistor (CFET) structure, the first complementary FET (CFET) structure having a first common gate as the input node of the first inverter; A second inverter is provided, the second inverter including a second top FET and a second bottom FET in a second complementary CFET structure, the second complementary CFET structure having a second common gate as the input node of the second inverter; A first back metal (BM) structure is provided, which couples the output node of the first inverter to the input node of the second inverter; as well as A second BM structure is provided, which couples the output node of the second inverter to the input node of the first inverter.

14. The method of claim 13, wherein the output node of the first inverter includes a first vertical connector electrically coupling the source / drain (S / D) region of the first top FET to the S / D region of the first bottom FET, and the output node of the second inverter includes a second vertical connector electrically coupling the S / D region of the second top FET to the S / D region of the second bottom FET.

15. The method of claim 13, further comprising providing a transmission gate, the transmission gate comprising a third top FET in a third CFET structure and a fourth top FET in a fourth CFET structure.

16. The method of claim 15, further comprising removing each of the third bottom FET in the third CFET structure and the fourth bottom FET in the fourth CFET structure.

17. The method of claim 15, wherein each of the third bottom FET in the third CFET structure and the fourth bottom FET in the fourth CFET structure is incomplete and / or nonfunctional.

18. The method of claim 13, further comprising providing a transmission gate, the transmission gate comprising a third bottom FET in a third CFET structure and a fourth bottom FET in a fourth CFET structure.

19. The method of claim 18, further comprising removing each of the third top FET in the third CFET structure and the fourth top FET in the fourth CFET structure.

20. The method of claim 18, wherein each of the third top FET in the third CFET structure and the fourth top FET in the fourth CFET structure is incomplete and / or nonfunctional.

21. The method of claim 13, wherein each of the first top FET and the second top FET comprises an N-type FET, and wherein each of the first bottom FET and the second bottom FET comprises a P-type FET.

22. The method of claim 13, wherein each of the first top FET and the second top FET comprises a P-type FET, and wherein each of the first bottom FET and the second bottom FET comprises an N-type FET.

23. The method of claim 13, wherein at least one of the first BM structure and the second BM structure comprises a back metal layer zero (BM0).

24. The method of claim 13, further comprising incorporating the semiconductor device into a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, and devices in motor vehicles.

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