FPGA prototype energy efficiency verification and iteration method for power patrol

Abstract

The present application relates to the technical field of hardware verification, and discloses an FPGA prototype energy efficiency verification and iteration method for power patrol, which comprises the following cyclic execution: image data of a scene subsequence is input to an FPGA prototype verification board for target detection, and board-level power consumption data is obtained at the same time; based on the target detection result and the board-level power consumption data, a current efficiency index of the scene subsequence to be verified is calculated; the current efficiency index is evaluated: if the current efficiency index is not up to standard, the current bottleneck type is determined according to the size relationship between the current efficiency index and a current efficiency target value, and the hardware configuration scheme is updated according to the current bottleneck type. The method of the present application divides an image sequence into multiple groups of scene subsequences with different feature complexities, and each group of scene subsequences enters an independent cyclic verification, so that the final hardware configuration scheme can cope with diversity and complexity; through the cyclic verification process, the verification efficiency is improved, and the verification period is shortened.

Description

Technical Field

[0001] This invention relates to the technical field of hardware verification, and in particular to an energy efficiency verification and iterative method for FPGA prototypes for power line inspection. Background Technology

[0002] When applying neural network models to edge computing scenarios such as power transmission line inspection, FPGA-based prototyping is a crucial step in evaluating their actual performance and energy efficiency. The goal of the verification is to confirm whether the model can meet the detection accuracy requirements while achieving strict real-time performance and power consumption constraints on the verification system.

[0003] Current verification methods heavily rely on human experience. Inspectors first implement the selected model using an FPGA (including parallelism, frequency, quantization, etc.), then deploy and test it. By observing the output results, frame rate, and power meter readings, they manually determine whether the requirements are met. If not, they must guess the bottleneck based on their experience (whether it's a model detection accuracy issue, insufficient computing resources, or poor power configuration), manually adjust the design parameters, and re-synthesize, place and route, and test. This process often requires multiple iterations, is inefficient, leads to aimless optimization, and lacks consistency.

[0004] Furthermore, traditional verification methods based on hardware configuration schemes obtained from power inspection videos are prone to significant performance degradation in practical applications. Summary of the Invention

[0005] Therefore, the purpose of this invention is to overcome the problem that hardware configuration schemes obtained through verification in the prior art are prone to significant performance degradation in practical applications. This invention provides an FPGA prototype energy efficiency verification and iteration method for power inspection. By dividing the image sequence into multiple scene subsequences with different feature complexities, and putting each scene subsequence into an independent loop for verification, the current bottleneck type is determined based on the relationship between the current performance index and the current performance target value. The hardware configuration scheme is then updated based on the current bottleneck type. Through iteration of scene subsequences with different feature complexities, a hardware configuration scheme that can solve challenges in various scenarios is obtained. Thus, the final hardware configuration scheme can cope with diverse and complex scenarios in practical applications and has robustness.

[0006] To address the aforementioned technical problems, this invention provides an FPGA prototype energy efficiency verification and iterative method for power line inspection, applied to a verification system including an FPGA prototype verification board. The method takes the target detection model and its hardware configuration scheme to be verified as the object, and is based on one or more scene subsequences in an image sequence representing the target power line inspection scene. The method includes a first stage, which comprises: cyclically executing the following steps until all scene subsequences are marked as verified:

[0007] The image data of the current scene subsequence to be verified is input into the FPGA prototype verification board for target detection, and the board-level power consumption data is obtained at the same time.

[0008] Based on the target detection results and board-level power consumption data, calculate the current performance index of the current scene subsequence to be verified;

[0009] Assess current performance metrics: If current performance metrics are not met, determine the current bottleneck type based on the relationship between the current performance metrics and the current performance target value, and update the hardware configuration scheme according to the current bottleneck type; If current performance metrics are met, mark the current scenario subsequence to be verified as verified, and use the remaining scenario subsequences to be verified as the current scenario subsequences to be verified.

[0010] Compared with the prior art, the above-described technical solution of the present invention has the following advantages:

[0011] The FPGA prototype energy efficiency verification and iteration method for power inspection described in this invention divides the image sequence into multiple scene subsequences with different feature complexities, and puts each scene subsequence into an independent loop for verification. The current bottleneck type is determined based on the relationship between the current efficiency index and the current efficiency target value, and the hardware configuration scheme is updated according to the current bottleneck type. By iterating through scene subsequences with different feature complexities, a hardware configuration scheme that can solve the challenges in various scenarios is obtained. Thus, the final hardware configuration scheme can cope with diverse and complex scenarios in practical applications and has robustness.

[0012] Furthermore, the FPGA prototype energy efficiency verification and iteration method for power inspection described in this invention improves verification efficiency and shortens the verification cycle by verifying each set of scenario subsequences one by one, and each set of scenario subsequences enters an independent cyclic verification process (detection, calculation of indicators, evaluation and judgment and updating of hardware configuration). Attached Figure Description

[0013] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings, wherein:

[0014] Figure 1 This is a schematic block diagram of a verification system in an embodiment of the present invention.

[0015] Figure 2 This is a flowchart illustrating the FPGA prototype energy efficiency verification and iteration method in an embodiment of the present invention.

[0016] Figure 3 This is a table showing the qualitative impact of a single strategy on performance indicators and volatility characteristics in embodiments of the present invention.

[0017] Figure 4 This is a schematic diagram of the strategy library structure in an embodiment of the present invention.

[0018] Figure 5 This is a schematic diagram of the lookup table structure in an embodiment of the present invention. Detailed Implementation

[0019] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0020] Image sequences in power line inspection scenarios (such as transmission line inspection) are decomposed from transmission line inspection videos (1080p, 30fps) into continuous image frames. Power line inspection videos include power equipment under different angles and lighting conditions, with the equipment's status including normal operation and defects. Further, for example, transmission line inspection videos include transmission lines under different angles and lighting conditions, where the transmission lines' status includes normal operation and defects. A defective transmission line could be one with broken strands.

[0021] Therefore, in power transmission line inspections, the actual input image sequences naturally exhibit unevenness in content. Specifically: Image sequences may alternate between simple and complex frames. For example, an image sequence might contain a large number of simple frames (e.g., a frame with a simple blue sky background, easy to process), followed by sudden transitions to complex frames (frames with complex backgrounds and densely packed targets, requiring complex processing). Image sequences may also exhibit uneven target frequency. For instance, an image sequence might have dozens of consecutive frames without defective targets, followed by several consecutive frames with multiple tiny defective targets requiring precise identification. Finally, image sequences may experience abrupt changes in lighting conditions. For example, an image sequence might suddenly switch from a brightly lit scene to a backlit or shadowed scene.

[0022] Since performance metrics are all average values, if the host computer calculates performance metrics based on the entire image sequence, the performance metrics will fail to reflect the real situation, making the verification results unusable in practice. Specifically, frame throughput may meet the standard, but severe instantaneous stuttering (i.e., a sharp drop in processing speed when encountering complex frames) will cause the system to be unstable in actual applications. Board-level power may meet the standard, but peak power consumption exceeds hardware safety or heat dissipation limits (e.g., low power consumption for simple frames, such as 3W; high power consumption for complex frames, such as 6W), which will cause the system to malfunction in actual applications. Detection accuracy may meet the standard, but insufficient reliability of critical tasks (e.g., high accuracy on simple frames, but low accuracy on a few critical complex frames) will prevent the system from obtaining accurate results in actual applications. Furthermore, since performance metrics are all average values, it may lead to the erroneous judgment that instantaneous performance fluctuations caused by uneven content distribution are inherent hardware configuration problems, thus leading to incorrect optimization directions.

[0023] To ensure that the performance of hardware configurations that meet all performance indicators will not deteriorate significantly when deployed in actual inspections, this application introduces an FPGA prototype energy efficiency verification and iterative method for power inspection.

[0024] Example 1: This example discloses an FPGA prototype energy efficiency verification and iteration method for power inspection.

[0025] The FPGA prototype energy efficiency verification and iterative method of this embodiment is applied to a verification system including an FPGA prototype verification board, a host computer, and a power monitoring unit. (Refer to...) Figure 1 .

[0026] In application, the power monitoring unit includes a power monitoring chip integrated on the verification board that can read data via an I2C interface.

[0027] The FPGA prototype energy efficiency verification and iteration method in this embodiment takes the target detection model to be verified and its initial hardware configuration scheme as the object, and is based on one or more scene subsequences in the image sequence of the target power inspection scenario (e.g., transmission line inspection).

[0028] In application, the target detection model to be validated is a neural network detection model for power equipment defect detection. Specifically, the target detection model has been trained using a large number of power equipment and defect images. Further, the target detection model is a neural network detection model used to locate and determine whether power equipment has defects in images, such as determining whether a transmission line has broken strands. Even further, the neural network detection model can be a YOLO series model, preferably YOLOv5. The neural network detection model includes a backbone network for feature extraction, a neck network for localization and feature fusion, and a head network for classification. The backbone network includes multiple convolutional layers, primarily using 3×3 convolutional kernels.

[0029] In practical applications, the initial hardware configuration is deployed on the FPGA prototype verification board as the current hardware configuration. Specifically, the host computer software reads the network structure description file of the target detection model and matches the corresponding initial hardware configuration from a pre-set configuration scheme library based on the network structure description file (e.g., computational graph features mainly composed of 3x3 convolutions). The host computer downloads the FPGA configuration file (bitstream) generated based on the initial hardware configuration scheme and the model weight data in INT8 format to the FPGA prototype verification board via an Ethernet interface. Furthermore, the initial hardware configuration scheme includes at least computational parallelism, operating frequency, quantization parameters, and power consumption constraints.

[0030] In practice, the image sequence includes one or more scene subsequences. Furthermore, each scene subsequence has different feature complexity, and each scene subsequence includes one or more image frames.

[0031] The FPGA prototype energy efficiency verification and iteration method in this embodiment includes a first stage, which is used to verify each set of scene subsequences in the image sequence.

[0032] The first stage of this embodiment includes: cyclically executing steps SS1 to SS3, as referenced. Figure 2 This continues until all scene subsequences are marked as verified.

[0033] Step SS1: Input the image data of the current scene subsequence to be verified into the FPGA prototype verification board for target detection, and at the same time obtain the board-level power consumption data.

[0034] When applied, the image data of the current scene subsequence to be verified is input into the FPGA prototype verification board with the current hardware configuration to perform target detection, and the board-level power consumption data is obtained at the same time.

[0035] In practical applications, the image data of the current scene subsequence to be verified is streamed to the FPGA prototype verification board via Ethernet. The FPGA prototype verification board receives the image stream, performs image preprocessing (e.g., scaling, color space conversion), then performs convolution calculations (e.g., INT8 precision convolution calculations), and finally outputs the target detection results for each frame. Furthermore, the target detection results may include: the presence of target power equipment, the bounding box coordinates of the target power equipment, and / or a confidence score indicating the presence of defects; these can be obtained using existing technologies, which will not be elaborated here. Even further, the target detection results may include: the presence of transmission equipment, the bounding box coordinates of the transmission equipment, and / or a confidence score indicating whether a line break has occurred.

[0036] In practical implementation, board-level power consumption data can include the current and voltage of the FPGA power rails. Specifically, a power monitoring unit measures the current and voltage of the FPGA power rails in real time at a frequency of 1000 times per second, and calculates the instantaneous power based on the current and voltage of the FPGA power rails. Furthermore, the board-level power consumption data can include instantaneous power with timestamps.

[0037] Step SS2: Based on the target detection results and board-level power consumption data, calculate the current performance index of the current scene subsequence to be verified.

[0038] In application, the host computer synchronously receives two data streams via a gigabit Ethernet interface. One stream is the target detection result for each frame sent back by the FPGA prototype verification board; the other stream is the instantaneous power data stream with timestamps sent back by the power monitoring chip. Based on the target detection results, image processing time (which can be determined based on the timestamps), and board-level power consumption data, the host computer calculates the current performance index of the scene subsequence to be verified.

[0039] In practical applications, performance metrics should include at least: detection accuracy, frame throughput, and board-level power. Specifically:

[0040] The detection accuracy value is calculated by comparing the target detection result with the actual annotation information (i.e., the actual annotation information of the video frame). Furthermore, based on the detection status of defective and normal power transmission equipment in all test frames, the precision rate is calculated, and the detection accuracy value is determined based on the precision rate. Even further, the power transmission equipment can be a power transmission line, and the detection accuracy value is the average detection accuracy value.

[0041] Frame throughput is calculated based on image processing time and the total number of image frames. Furthermore, the average processing speed is calculated based on the time difference between sending the first frame of the scene subsequence and receiving the last frame of the scene subsequence, as well as the total number of image frames, to obtain the frame throughput.

[0042] The board-level power is calculated based on the board-level power consumption data. Further, the board-level power can be the average board-level power, and the host computer calculates the average value of all the instantaneous powers received to obtain the average board-level power.

[0043] It can be seen that in the actual implementation process, the performance indicators are all average values.

[0044] Step SS3: Evaluate the current performance indicator: If the current performance indicator does not meet the standard, determine the current bottleneck type according to the magnitude relationship between the current performance indicator and the current performance target value, and update the hardware configuration plan according to the current bottleneck type; if the current performance indicator meets the standard, mark the current scene subsequence to be verified as verified, and use the remaining scene subsequences to be verified as the current scene subsequence to be verified.

[0045] During application, when all three performance indicators reach the passing threshold, it is qualified; otherwise, it is unqualified. Specifically: If the detection accuracy value does not reach the detection accuracy target value, the performance indicator does not meet the standard, and it is determined that there is an accuracy bottleneck; if the detection accuracy value reaches the detection accuracy target value, but the frame throughput rate does not reach the throughput rate target value, the performance indicator does not meet the standard, and it is determined that there is a throughput bottleneck; if the detection accuracy value reaches the detection accuracy target value, the frame throughput rate reaches the throughput rate target value, but the board-level power does not reach the board-level target value, the performance indicator does not meet the standard, and it is determined that there is a power consumption bottleneck.

[0046] During actual application, the detection accuracy target value, the throughput rate target value, and the board-level target value can be determined through statistical analysis of historical data. For example: The detection accuracy target value is 0.85, that is, on the test image, the comprehensive detection accuracy of the target detection model for defective transmission lines and normal transmission lines needs to reach more than 85%. The throughput rate target value is 30fps, that is, it is required that the system processes continuously input images with a resolution of 1920x1080 (1080p) at a speed not lower than 30 frames per second. The board-level target value is 5W, that is, it is required that the average power consumption of the entire FPGA prototype verification board in the working state is lower than 5W.

[0047] In some embodiments, when it is determined to be an accuracy bottleneck, based on the analysis results of the detection error samples in the current round, adjust the fixed-point quantization bit width of the model or perform fixed-point number accuracy remapping on specific network layers, and use it to update the hardware configuration plan. When it is determined to be a throughput bottleneck, under the constraint of FPGA resources, increase the parallel channels of the computing engine or optimize the stage division of the computing pipeline, and use it to update the hardware configuration plan. When it is determined to be a power consumption bottleneck, on the premise that the frame throughput rate does not fall below its threshold, stepwise lower the working voltage and frequency configuration of the relevant computing modules inside the FPGA, and use it to update the hardware configuration plan.

[0048] In one specific embodiment, the image sequence comprises a set of scene subsequences. The target detection accuracy is 0.85, the target throughput is 30fps, and the target board level is 5W. In the initial hardware configuration, the computational parallelism is configured with the convolutional computation unit set to 16-channel parallel processing mode, the operating frequency is configured with the clock frequency of the computation logic at 200MHz, the quantization parameters are configured with the fixed-point quantization scheme for model weights and activation values ​​as 8-bit integers (i.e., INT8), and the power consumption constraint parameter is configured with a voltage of 0.85V.

[0049] During the first loop, the average detection accuracy was 0.78, the frame throughput was 28fps, and the average board power consumption was 5.8W. Therefore, this was identified as an accuracy bottleneck. Specifically, the weights and computational accuracy of the last three classification layers, the most sensitive layers in the model, were increased from INT8 to INT12 (to improve classification accuracy), and the hardware configuration was updated. The updated hardware configuration modifies the computational units to support INT12 accuracy, while other configurations (e.g., 16-channel parallel processing mode, 200MHz clock frequency, 0.85V voltage) remain unchanged for now.

[0050] During the second loop, the average detection accuracy was 0.88, the frame throughput was 27fps, and the average board power consumption was 5.9W. Therefore, this was identified as a throughput bottleneck, and the parallelism was increased from 16-channel to 24-channel, along with an updated hardware configuration. It's worth noting that the pipeline can be fine-tuned in practical applications.

[0051] After multiple cycles, the voltage was reduced to 0.82V. In the final cycle, the average detection accuracy was 0.86, the frame throughput was 31fps, and the average board power was 4.9W, indicating that the three performance indicators met the standards. At this point, after the first phase of verification, for image sequences, the target detection model on the FPGA prototype verification board simultaneously met the following three performance indicators: 24-channel parallel processing mode, 175MHz clock frequency, INT12 quantization scheme, and 0.82V voltage.

[0052] Example 2: Based on Example 1, this example details the energy efficiency verification and iterative method for FPGA prototypes for power line inspection.

[0053] In application, the FPGA prototype energy efficiency verification and iteration method for power inspection in this embodiment includes a step of dividing multiple scene subsequences and a first-stage step.

[0054] The method for dividing multiple scene subsequences in this embodiment includes step SS01.

[0055] Step SS01: Based on the background texture complexity and target density value of the image sequence, a clustering algorithm is used to cluster and group the image sequence, grouping consecutive or adjacent frames with similar features into the same group to obtain multiple scene subsequences.

[0056] In application, the background texture complexity of an image sequence can be calculated using existing techniques. For example, by statistically analyzing the distribution of the image grayscale gradient magnitudes and calculating the information entropy of the grayscale gradients, the background texture complexity can be quantified using information entropy. Higher information entropy indicates a more dispersed distribution of the image grayscale gradients and thus greater background texture complexity; lower information entropy indicates less background texture complexity. Further details are omitted here.

[0057] The target density value of an image sequence can be determined based on the proportion of the foreground region area to the total image area. For example, the target density value can be determined by performing color-based foreground segmentation on each frame of the image sequence and calculating the proportion of the foreground region area to the total image area. This will not be elaborated further here.

[0058] In practical applications, clustering algorithms (such as K-means) are used to group the frame features (background texture complexity, target density value) of image sequences.

[0059] The multiple scene subsequences include at least one of the following: low background low target group scene subsequence, high background high target group scene subsequence, high background low target group scene subsequence, and low background high target group scene subsequence.

[0060] In practical implementation, a low-background, low-target-group scene subsequence is a frame sequence with a simple background texture and a small number of targets, such as 1 to 3 power transmission lines against a solid color background. A high-background, high-target-group scene subsequence is a frame sequence with a complex background texture and a large number of targets, such as a dense area of ​​multiple power transmission lines against a complex background. In some embodiments, a complex background refers to a background that includes at least one of the following: clouds, tree branches, or other electrical equipment such as utility poles.

[0061] The first stage of this embodiment includes: repeatedly executing steps SS1 to SS3 until all scene subsequences are marked as verified.

[0062] Step SS1: Input the image data of the current scene subsequence to be verified into the FPGA prototype verification board with the current hardware configuration scheme for target detection, and at the same time obtain the board-level power consumption data.

[0063] During application, scene subsequences are input in ascending order of feature complexity. For example, first verify the low-background, low-target scene subsequence, then the high-background, low-target scene subsequence, then the low-background, high-target scene subsequence, and finally the high-background, high-target scene subsequence. In actual grouped cyclic verification, each scene subsequence is verified independently, and the hardware configuration of the FPGA prototype verification board (e.g., clock frequency, computational parallelism) is fixed. However, when switching scene subsequences, the hardware operating state of the FPGA prototype verification board (e.g., on-chip cache state) may change due to the load of the previous scene subsequence, thus affecting the performance of verifying the current scene subsequence—this is known as inter-group interference.

[0064] For example, after verifying a high-background, high-target-group scene subsequence, the chip temperature rises. This may cause the chip temperature to not drop immediately when verifying a low-background, low-target-group scene subsequence, even though the load is reduced. Furthermore, the chip temperature may be too high, triggering frequency reduction and resulting in substandard performance.

[0065] For example, after validating a low-background, low-target-group scene subsequence, when continuing to validate high-background, high-target-group scene subsequences, high-background, low-target-group scene subsequences, or low-background, high-target-group scene subsequences, the FPGA prototype verification board needs to at least complete a power supply system switch. However, switching from a low-power operating state to a high-power state requires a transition period for the power supply to stably output the required large current. During this transition period, voltage undershoot may occur, leading to a decrease in detection accuracy, which may result in misjudgment as an accuracy bottleneck.

[0066] Furthermore, the lag in hardware status during inter-group switching is affected by various factors (such as ambient temperature, individual hardware differences, and historical operating status). This can lead to different results when the same hardware configuration is run for verification at different times due to different initial conditions of hardware status data, thus affecting the reliability of the verification.

[0067] To mitigate or even eliminate inter-group interference, step SS1 in this embodiment includes steps SS11 to SS13.

[0068] Step SS11: Continuously input images of the current scene subsequence to be verified, and obtain hardware status data in real time.

[0069] In application, step SS11 is the initial verification stage. Furthermore, the hardware status data includes at least chip temperature and voltage ripple data.

[0070] Step SS12: When the hardware status data is stable within the steady-state range of the scene subsequence, perform target detection on the current scene subsequence to be verified and obtain board-level power consumption data.

[0071] In application, step SS12 is the verification and detection phase. Further, when the hardware state data stabilizes within the steady-state range of the current subsequence to be verified, target detection is performed on the current subsequence to be verified, and board-level power consumption data is obtained.

[0072] In practical applications, the method for determining whether hardware status data is stable within the steady-state range of a scene subsequence includes step SS121.

[0073] Step SS121: During the continuous input of the current scene subsequence to be verified to the FPGA prototype verification board, hardware status data is collected at a fixed period (e.g., times / 100 milliseconds). When all chip temperatures fall within the temperature steady-state target range of the scene subsequence within M1 (e.g., 5) consecutive collection periods, and the voltage ripple data are all less than the maximum allowable ripple value of the scene subsequence, it is determined that the hardware status data is stable within the steady-state range of the scene subsequence.

[0074] When applying this technology, the method for determining the steady-state temperature target range is as follows: Within the operating temperature range specified in the power supply chip datasheet (e.g., -40℃ to 100℃), a narrow and stable operating temperature range is set as the steady-state temperature target range, taking into account long-term operational reliability, heat dissipation design capabilities, and ambient temperature conditions in practical applications. For example, in practical applications, to ensure long-term stable system operation, the steady-state temperature target range can be set to 50℃ to 60℃.

[0075] The method for determining the maximum permissible ripple value is as follows: Based on the steady-state ripple specification given in the power supply chip datasheet (e.g., not exceeding ±2%), and considering the acceptable voltage fluctuation range and noise margin requirements during the system's load transient response, the maximum permissible ripple value is determined. For example, for a voltage (e.g., 0.85V), based on the steady-state ripple requirement (±2%) in the power supply chip datasheet, and considering the system's transient response requirements during load switching, the maximum permissible ripple value is set to ±2% (corresponding to a ripple voltage not exceeding ±17mV).

[0076] Step SS13: After obtaining the target detection result, continuously input the image of the reference subsequence until the hardware state data stabilizes within the steady-state range of the reference subsequence.

[0077] In application, step SS13 is the verification and recovery phase. Furthermore, the baseline subsequence includes multiple frames of solid color images.

[0078] In practical applications, the method for determining whether hardware status data is stable within the steady-state range of the reference subsequence includes step SS131.

[0079] Step SS131: During the continuous input of the reference subsequence to the FPGA prototype verification board, hardware status data is collected at a fixed period (e.g., times / 100 milliseconds). When all chip temperatures fall within the reference temperature range calibrated by the system within M2 (e.g., 5) consecutive collection cycles, and the voltage ripple data are all less than the reference ripple threshold calibrated by the system, it is determined that the hardware status data is stable within the steady-state range of the reference subsequence.

[0080] In application, the reference temperature range and reference ripple threshold are steady-state reference ranges determined statistically after the system reaches thermal and electrical equilibrium during the system initialization phase by running a reference subsequence (such as a solid color image sequence) and monitoring hardware status data.

[0081] In practical applications, after system startup, 1000 frames of pure black images are continuously input (at which point the load is at its lowest), and the chip temperature and voltage ripple data are continuously monitored. After running for 5 minutes, the chip temperature stabilizes between 32℃ and 34℃, and the voltage ripple data fluctuates within ±0.5%. Therefore, the reference temperature range is set to 32℃ to 34℃, and the reference ripple threshold is set to ±0.5%.

[0082] Step SS2: Based on the target detection results and board-level power consumption data, calculate the current performance index of the current scene subsequence to be verified.

[0083] When applied, the image processing time of the current scene subsequence to be verified is determined based on the timestamp in the board-level power consumption data, which is the time difference between sending the first frame of the current scene subsequence to be verified and receiving the target detection result of the last frame of the current scene subsequence to be verified.

[0084] In practical applications, refer to Example 1: calculate the detection accuracy value by comparing the target detection result with the real annotation information; calculate the frame throughput rate by calculating the image processing time and the total number of image frames; and obtain the board-level power by calculating the average value of the board-level power consumption data.

[0085] Step SS3: Evaluate current performance metrics: If the current performance metrics do not meet the target, determine the current bottleneck type based on the relationship between the current performance metrics and the current performance target value, and update the hardware configuration scheme according to the current bottleneck type; If the current performance metrics meet the target, mark the current scenario subsequence to be verified as verified, and use the remaining scenario subsequences to be verified as the current scenario subsequences to be verified.

[0086] When applying the application, the current performance indicators are evaluated as follows: if the detection accuracy value does not reach the detection accuracy target value, the performance indicator is not up to standard, and it is determined that there is an accuracy bottleneck; if the detection accuracy value reaches the detection accuracy target value, but the frame throughput does not reach the throughput target value, the performance indicator is not up to standard, and it is determined that there is a throughput bottleneck; if the detection accuracy value reaches the detection accuracy target value and the frame throughput reaches the throughput target value, but the board-level power does not reach the board-level target value, the performance indicator is not up to standard, and it is determined that there is a power consumption bottleneck; otherwise, the performance indicator is up to standard.

[0087] In some embodiments, the detection accuracy target value is equal to the product of a first adjustment coefficient and a base accuracy target value. Further, the first adjustment coefficient > 1, and the first adjustment coefficient is positively correlated with the target density value of the scene subsequence. Even further, the first adjustment coefficient is an increasing function. In application, the base accuracy target value can be set according to task requirements, for example, 0.85.

[0088] In some embodiments, the throughput target value is equal to the product of the second adjustment coefficient and the base frame rate target value. Further, 0 < the second adjustment coefficient ≤ 1, and the second adjustment coefficient is negatively correlated with the background texture complexity of the scene subsequence. Even further, the second adjustment coefficient is a decreasing function. In application, the base frame rate target value can be set according to the video source frame rate, for example, 1080p@30fps.

[0089] In some embodiments, the board-level target value is equal to the product of a third adjustment factor and a base power consumption target value. Further, the third adjustment factor is greater than 1, and is positively correlated with the scene difficulty calculated based on the target density value of the scene subsequence and the background texture complexity. Even further, the third adjustment factor is an increasing function. In application, the base power consumption target value can be set according to the hardware's heat dissipation and power supply capabilities, for example, 5W.

[0090] In practical applications, the three performance metrics may have complex interrelationships. If the bottleneck type is determined solely based on whether the three performance metrics meet the standards, and the hardware configuration is updated accordingly, it may lead to the discovery of another bottleneck while addressing one, causing the optimization process to loop between multiple hardware configurations and making convergence difficult. For example, improving detection accuracy may simultaneously reduce frame throughput or increase power consumption; increasing frame throughput may affect power consumption and detection accuracy; reducing power consumption may affect frame throughput or detection accuracy. To reduce the number of loops, this embodiment sets up a multi-metric prediction and comprehensive evaluation mechanism (steps SS31 to SS36) when updating the hardware configuration.

[0091] Step SS31: Based on the hardware state data collected in the initial stage of the verification of the current scenario subsequence to be verified, calculate the fluctuation characteristic quantity reflecting the transient response of the hardware.

[0092] In application, fluctuation characteristics include the temperature rise slope and / or voltage downslope.

[0093] In practical applications, during the initial verification phase, the slope of the temperature change curve (i.e., the chip temperature change curve) for the first few sampling cycles is the temperature rise slope. At the moment of load switching, the drop in voltage waveform from its lowest point relative to the nominal voltage (i.e., the standard voltage value specified in the power chip datasheet, such as 0.85V) is the voltage undershoot.

[0094] Step SS32: Based on the comparison between the fluctuation characteristic quantity and the preset threshold, determine the interference risk level of the hardware to load changes under the current hardware configuration scheme.

[0095] In application, preset thresholds include a temperature slope threshold and a voltage undershoot threshold. Furthermore, these preset thresholds can be determined based on historical data statistical analysis. Specifically, the temperature slope threshold is less than or equal to 2℃ / second, and the voltage undershoot threshold is less than or equal to 5%.

[0096] In practical applications, interference risk levels include low risk and medium-high risk. Furthermore, when the volatility characteristic is less than a preset threshold, it is considered low risk; when the volatility characteristic is greater than or equal to the preset threshold, it is considered medium-high risk.

[0097] In actual implementation, when the temperature rise slope is less than the temperature slope threshold and the voltage downslope is less than the voltage downslope threshold, it is considered low risk; otherwise, it is considered medium to high risk.

[0098] Step SS33: Select candidate strategies from the strategy library based on the interference risk level and the current bottleneck type.

[0099] In application, the strategy library includes multiple strategies, each with pre-defined qualitative impacts on various performance indicators and volatility characteristics. Specifically, the qualitative impact refers to the trend of the effect on various performance indicators and volatility characteristics after the strategy is executed (e.g., increase, decrease, or remain essentially unchanged). For example: Reference Figure 3 The strategy to increase the number of parallel channels in convolutional computation units can have the following pre-defined qualitative impacts: frame throughput: significantly improved (++); detection accuracy: basically unchanged (→); board-level power consumption: basically unchanged (→); temperature rise slope: slightly increased (+); voltage downslope: basically unchanged (→). It's worth noting that in the qualitative impacts, ++ indicates a strong positive impact, + indicates a positive impact, → indicates no significant impact, and - indicates a negative impact. Furthermore, each strategy can also have a pre-defined empirical description of its impact level.

[0100] In practical applications, the policy library includes various types of policies. For details, please refer to... Figure 4The strategy library includes: detection accuracy optimization strategies, throughput optimization strategies, power consumption optimization strategies, and / or interference suppression strategies. Detection accuracy optimization strategies are used to increase the global quantization bit width of the model, increase the bit width of the classification layer at the end of the network, and / or adjust the dynamic range of activation values. Throughput optimization strategies are used to increase the number of parallel channels in convolutional computation units, increase the clock frequency, increase the upper limit of the clock frequency, and / or adjust the on-chip cache size. Power consumption optimization strategies are used to reduce voltage, reduce clock frequency, reduce switching activity, and / or skip the computation of zero weights. Interference suppression strategies are used to increase the upper limit of the voltage threshold, smooth the transition curve of voltage frequency with load changes, and / or reduce the clock frequency based on temperature.

[0101] In actual implementation, candidate strategies are selected from the strategy library based on the level of interference risk and the current bottleneck type.

[0102] Candidate strategies are selected based on the degree of matching between the qualitative impact of each strategy in the strategy library and the current bottleneck type and interference risk level. This specifically includes steps SS331 to SS332.

[0103] Step SS331: Determine the strategy type based on the bottleneck type. Specifically, if the bottleneck is accuracy, select a detection accuracy optimization strategy as a candidate strategy; if the bottleneck is throughput, select a throughput optimization strategy as a candidate strategy; if the bottleneck is power consumption, select a power consumption optimization strategy as a candidate strategy.

[0104] Step SS332: Determine whether to add an interference suppression strategy as a candidate strategy based on the interference risk level. Specifically, if the interference risk level is medium to high, then add an interference suppression strategy as a candidate strategy; if the interference risk level is medium, then do not add an interference suppression strategy as a candidate strategy.

[0105] Step SS34: For each candidate strategy, based on the qualitative impact, predict the predicted values ​​of various performance indicators and fluctuation characteristics after the candidate strategy is executed.

[0106] When applied, the predicted values ​​of various performance indicators and fluctuation characteristics are estimated by looking up tables based on the current hardware status data, load characteristics, and the qualitative impact of the selected strategy.

[0107] In practical applications, the predicted values ​​for various performance indicators include throughput, detection accuracy, and board-level predictions. Predicted values ​​for fluctuation characteristics include temperature rise slope and / or voltage undershoot amplitude. The load is the sum of computational tasks, data processing, and hardware resource usage triggered by image data input to the FPGA prototype verification board. Furthermore, load characteristics include at least background texture complexity, target density, convolution calculation intensity, and on-chip cache utilization. (Reference) Figure 5 The lookup table includes load characteristics, hardware configuration status, policy content, performance indicator predictions, fluctuation characteristic predictions, and / or qualitative impact labels.

[0108] In a specific embodiment, the current frame throughput is 25fps. A candidate strategy to increase the number of parallel channels in the convolutional computation unit is selected. The qualitative impact of this candidate strategy is a significant increase in frame throughput (++), a slight increase in the temperature rise slope (+), and other performance indicators and fluctuation characteristics remaining essentially unchanged (→). A lookup table based on historical experimental data shows that, under the current load, increasing the number of parallel channels from 16 to 24 can increase frame throughput by approximately 20% and increase the temperature rise slope by 10%. Therefore, the predicted throughput is 25fps × (1 + 20%) = 30fps, and the predicted temperature rise slope is 1.5℃ / sec × (1 + 10%) = 1.65℃ / sec. It is worth noting that, at this point, the predicted values ​​for other performance indicators and fluctuation characteristics are assumed to be the current values.

[0109] Step SS35: Calculate the comprehensive score based on the predicted values ​​of each performance indicator and fluctuation characteristic quantity, as well as the target values ​​of each performance indicator and fluctuation characteristic quantity.

[0110] When applying the application, the calculation of the comprehensive score includes steps SS351 to SS353.

[0111] Step SS351: Determine the key optimization indicators and coupled attention indicators based on the current bottleneck type.

[0112] When applying this technology, if the bottleneck type is accuracy bottleneck, the key optimization metric is the detection accuracy value, while frame throughput and board-level power are coupled metrics of concern; if the bottleneck type is throughput bottleneck, the key optimization metric is the frame throughput, while detection accuracy and board-level power are coupled metrics of concern; if the bottleneck type is power consumption bottleneck, the key optimization metric is board-level power, while detection accuracy and frame throughput are coupled metrics of concern.

[0113] Step SS352: Calculate the first score, second score, and third score based on the predicted values ​​of each performance indicator and fluctuation characteristic quantity and the target values ​​of each performance indicator and fluctuation characteristic quantity.

[0114] In application, the target values ​​for various performance indicators include target values ​​for detection accuracy, throughput, and board-level performance. Target values ​​for fluctuation characteristics include target values ​​for temperature rise rate and voltage undershoot amplitude. In some embodiments, the target value for temperature rise rate is 0 to 0.2°C / second, and the target value for voltage undershoot amplitude is 0 to 2%.

[0115] In practical applications, the first score includes the positive difference between the predicted value and the target value of the key optimization indicator. Specifically, when X≤0, the first score = 0; when X>0, the first score = X, where X is the ratio of the difference between the predicted value and the target value of the key optimization indicator to the target value of the key optimization indicator.

[0116] The second score includes the positive difference between the predicted values ​​of each coupled indicator of concern and their target values. Specifically, when Y≤0, the second score = 0; when Y>0, the second score = Y, where Y is the ratio of the sum of the differences between the predicted values ​​of each coupled indicator of concern and their target values ​​to the predicted values ​​of the coupled indicators of concern.

[0117] The third score includes the degree to which the predicted value of the fluctuation characteristic decreases relative to its current value. Specifically, the third score = Z, where Z is the ratio of the difference between the current value and the predicted value of the fluctuation characteristic to the current value of the fluctuation characteristic. In some specific embodiments, the third score = Z1 when Z1 is greater than or equal to Z2; and the third score = Z2 when Z1 is less than Z2; where Z1 is the ratio of the difference between the current value and the predicted value of the temperature rise slope to the current value of the temperature rise slope; and Z2 is the ratio of the difference between the current value and the predicted value of the voltage undershoot amplitude to the current value of the voltage undershoot amplitude. When only the temperature rise slope is considered for the fluctuation characteristic, Z = Z1; when only the voltage undershoot amplitude is considered for the fluctuation characteristic, Z = Z2; and when both the temperature rise slope and the voltage undershoot amplitude are considered for the fluctuation characteristic, Z = (Z1 + Z2) / 2.

[0118] Step SS353: Obtain the overall score by weighted summation of the first score, the second score, and the third score.

[0119] In application, in order to ensure that the current bottleneck is resolved first, while taking into account that other performance indicators do not deteriorate, and to appropriately consider system stability and avoid oscillations during the optimization process, the weight of the first score in this embodiment is greater than the weight of the second score, and the weight of the second score is greater than the weight of the third score.

[0120] In practical applications, the weights of the first score, the second score, and the third score are all greater than 0, and their sum equals 1.

[0121] Step SS36: Select the candidate strategy with the highest overall score as the update strategy, and update the hardware configuration scheme according to the update strategy.

[0122] When applying this strategy, if multiple candidate strategies have the same overall score and are all the highest, all of them will be used as the update strategy.

[0123] Example 3: This example introduces an FPGA prototype energy efficiency verification and iteration method for power inspection.

[0124] While scenario-based verification (i.e., verification of each scenario subsequence) ensures that the hardware configuration meets standards in each static, single scenario, the actual power inspection process is continuous and dynamic. Scenarios with different complexities and load characteristics alternate randomly and switch rapidly. This dynamic switching of scenarios places continuous transient stress on the FPGA prototype verification board. Specifically, when switching from one high-load scenario to another, the hardware status data of the FPGA prototype verification board may not be able to recover in time, leading to a decrease in the initial performance of subsequent scenarios. Furthermore, frequent load fluctuations may cause continuous voltage noise or temperature accumulation, potentially exposing stability issues or reliability risks that were not detected in static testing over long-term operation. Therefore, although the configuration of each scenario subsequence is independently optimized and meets standards, the overall performance, when combined into a complete workflow, may fail to meet global constraints due to the aforementioned dynamic effects.

[0125] To improve the robustness of the final determined hardware configuration scheme, based on Embodiment 1 or Embodiment 2, the FPGA prototype energy efficiency verification and iteration method for power inspection in this embodiment also includes a second stage.

[0126] When applying the application, the second phase steps are executed after the first phase steps are completed.

[0127] In practical applications, the second stage involves randomly mixing the images of each scene subsequence to generate a mixed sequence, and cyclically executing steps SS41 to SS43 until the performance indicators are met.

[0128] Step SS41: Input the mixed sequence image data into the FPGA prototype verification board for target detection, and at the same time obtain the board-level power consumption data.

[0129] In application, the mixed sequence of image data is input to an FPGA prototype verification board with the current hardware configuration for target detection, while board-level power consumption data is acquired.

[0130] In practical applications, the mixed sequence is regarded as a set of scene sub-sequences. The specific execution method of step SS41 can be referred to step SS1 of Embodiment 1 or Embodiment 2, which will not be repeated here.

[0131] Step SS42: Based on the target detection results and board-level power consumption data, calculate the performance index of the hybrid sequence.

[0132] When applying this method, the specific execution method of step SS42 can be referred to step SS2 of embodiment 1 or embodiment 2, and will not be repeated here.

[0133] Step SS43: Evaluate current performance metrics: If performance metrics are not met, determine the bottleneck type based on the relationship between the performance metrics and the performance target value, and update the hardware configuration scheme according to the bottleneck type.

[0134] When applying this method, the specific execution method of step SS43 can be referred to step SS3 of Example 1 or Example 2 to confirm that the model can meet the detection accuracy requirements while achieving frame throughput constraints (e.g., 1080p@30fps) and board-level power constraints (e.g., <5W) on the verification system. Further details are omitted here.

[0135] In practical applications, when the performance indicators in the second stage fail to meet the standards, the hardware configuration scheme will be updated based on the bottleneck type of the mixed sequence. Since the problem is exposed during dynamic scene switching, throughput optimization strategies and power consumption optimization strategies will be prioritized.

[0136] This embodiment simulates the harsh working conditions of disordered and abrupt load changes in real-world inspections by randomly mixing sub-sequence images from various scenarios to obtain a hybrid sequence. By verifying that the performance indicators of the hybrid sequence meet the standards, it ensures that the final hardware configuration scheme can maintain stable and reliable performance in complex dynamic environments during actual deployment, significantly enhancing the practicality and reliability of the project.

[0137] In summary, the FPGA prototype energy efficiency verification and iteration method for power inspection described in this invention divides the image sequence into multiple scene subsequences with different feature complexities and puts each scene subsequence into an independent loop verification. This ensures that the optimization process can solve the challenges under various scenarios, so that the final hardware configuration scheme has the ability to cope with diversity and complexity and has robustness.

[0138] Furthermore, the FPGA prototype energy efficiency verification and iteration method for power inspection described in this invention improves verification efficiency and shortens the verification cycle by verifying each set of scenario subsequences one by one, and each set of scenario subsequences enters an independent cyclic verification process (detection, calculation of indicators, evaluation and judgment and updating of hardware configuration).

[0139] Furthermore, the FPGA prototype energy efficiency verification and iterative method for power line inspection described in this invention uses a hybrid sequence to simulate the harsh working conditions of disordered and abrupt load changes in real-world inspections. By verifying the performance indicators of the hybrid sequence in the second stage, it is ensured that the final hardware configuration scheme can maintain stable and reliable performance in complex dynamic environments during actual deployment, significantly enhancing engineering practicality and reliability.

[0140] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for energy efficiency verification and iterative analysis of FPGA prototypes for power line inspection, characterized in that, An application to a verification system including an FPGA prototype verification board, this method takes the target detection model and its hardware configuration scheme to be verified as the object, and is based on one or more scene subsequences in an image sequence of a target power inspection scene. The method includes a first stage, which includes: cyclically executing the following steps until all scene subsequences are marked as verified: The image data of the current scene subsequence to be verified is input into the FPGA prototype verification board for target detection, and the board-level power consumption data is obtained at the same time. Based on the target detection results and board-level power consumption data, calculate the current performance index of the current scene subsequence to be verified; Assess current performance metrics: If current performance metrics are not met, determine the current bottleneck type based on the relationship between the current performance metrics and the current performance target value, and update the hardware configuration scheme according to the current bottleneck type; If current performance metrics are met, mark the current scenario subsequence to be verified as verified, and use the remaining scenario subsequences to be verified as the current scenario subsequences to be verified.

2. The FPGA prototype energy efficiency verification and iteration method for power line inspection according to claim 1, characterized in that, Methods for dividing multiple scene subsequences include: Based on the background texture complexity and target density value of the image sequence, a clustering algorithm is used to cluster and group the image sequence, grouping consecutive or adjacent frames with similar features into the same group to obtain multiple scene subsequences; among them, the multiple scene subsequences include at least one of the following: low background low target group scene subsequence, high background high target group scene subsequence, high background low target group scene subsequence, and low background high target group scene subsequence.

3. The FPGA prototype energy efficiency verification and iteration method for power line inspection according to claim 1, characterized in that, The step of inputting the image data of the current scene subsequence to be verified into the FPGA prototype verification board deployed with the current hardware configuration for target detection includes: The system continuously inputs images of the current scene subsequence to be verified and acquires hardware status data in real time. The hardware status data includes at least chip temperature and voltage ripple data. When the hardware status data stabilizes within the steady-state range of the scene subsequence, target detection is performed on the current scene subsequence to be verified, and board-level power consumption data is obtained. After obtaining the target detection result, the images of the reference subsequence are continuously input until the hardware state data stabilizes within the steady-state range of the reference subsequence; the reference subsequence includes multiple frames of solid color images.

4. The FPGA prototype energy efficiency verification and iteration method for power line inspection according to claim 3, characterized in that, The target detection results include: whether the target power equipment exists, the bounding box coordinates of the target power equipment, and the confidence score for whether there is a defect; The method for determining that the hardware status data is stable within the steady-state range of the scene subsequence includes: during the continuous input of the current scene subsequence to be verified to the FPGA prototype verification board, hardware status data is collected at fixed intervals. When all chip temperatures fall within the temperature steady-state target range of the scene subsequence within M1 consecutive collection cycles, and the voltage ripple data are all less than the maximum allowable ripple value of the scene subsequence, it is determined that the hardware status data is stable within the steady-state range of the scene subsequence. The method for determining whether the hardware status data is stable within the steady-state range of the reference subsequence includes: during the continuous input of the reference subsequence to the FPGA prototype verification board, hardware status data is collected at fixed intervals. When all chip temperatures fall within the reference temperature range calibrated by the system within M2 consecutive collection cycles, and the voltage ripple data are all less than the reference ripple threshold calibrated by the system, it is determined that the hardware status data is stable within the steady-state range of the reference subsequence; wherein, the reference temperature range and the reference ripple threshold are determined by measurement when the reference subsequence is run during system initialization.

5. The FPGA prototype energy efficiency verification and iteration method for power inspection according to claim 1, characterized in that, The performance indicators include at least: detection accuracy, frame throughput, and board-level power; wherein, the detection accuracy is calculated based on the comparison between the target detection result and the real annotation information; the frame throughput is calculated based on the image processing time and the total number of image frames; and the board-level power is calculated based on the board-level power consumption data. The current performance indicators for evaluation include: If the detection accuracy value does not reach the detection accuracy target value, the performance index is not up to standard, and it is determined that there is an accuracy bottleneck. If the detection accuracy reaches the target value, but the frame throughput does not reach the target value, the performance indicator is not up to standard, and it is determined that there is a throughput bottleneck. If the detection accuracy value reaches the detection accuracy target value and the frame throughput reaches the throughput target value, but the board-level power does not reach the board-level target value, then the performance indicators are not up to standard and it is determined that there is a power consumption bottleneck. Otherwise, the performance indicators will be met.

6. The FPGA prototype energy efficiency verification and iteration method for power line inspection according to claim 5, characterized in that, The target detection accuracy is equal to the product of the first adjustment coefficient and the base accuracy target value; wherein, the first adjustment coefficient is greater than 1, and the first adjustment coefficient is positively correlated with the target density value of the scene subsequence; The throughput target value is equal to the product of the second adjustment coefficient and the base frame rate target value; where 0 < second adjustment coefficient ≤ 1, and the second adjustment coefficient is negatively correlated with the background texture complexity of the scene subsequence; The board-level target value is equal to the product of the third adjustment coefficient and the basic power consumption target value; wherein, the third adjustment coefficient is greater than 1, and the third adjustment coefficient is positively correlated with the scene difficulty calculated based on the target density value of the scene subsequence and the background texture complexity.

7. The FPGA prototype energy efficiency verification and iteration method for power line inspection according to claim 3, characterized in that, The step of updating the hardware configuration scheme according to the current bottleneck type includes: Based on the hardware state data collected in the initial stage of the verification of the current scenario subsequence to be verified, fluctuation characteristics reflecting the transient response of the hardware are calculated; the fluctuation characteristics include the temperature rise slope and / or voltage downslope. By comparing the fluctuation characteristics with the preset threshold, the interference risk level of the hardware to load changes under the current hardware configuration scheme is determined. Based on the level of interference risk and the current bottleneck type, candidate strategies are selected from the strategy library; the strategy library includes multiple strategies, each of which has a pre-defined qualitative impact on various performance indicators and volatility characteristics. For each candidate strategy, based on the qualitative impact, predict the predicted values ​​of various performance indicators and fluctuation characteristics after the candidate strategy is executed; A comprehensive score is calculated based on the predicted values ​​of each performance indicator and fluctuation characteristic quantity, as well as the target values ​​of each performance indicator and fluctuation characteristic quantity. The candidate strategy with the highest overall score is selected as the update strategy, and the hardware configuration scheme is updated according to the update strategy.

8. The FPGA prototype energy efficiency verification and iteration method for power inspection according to claim 7, characterized in that, The comprehensive score calculation includes: Based on the current bottleneck type, determine the key optimization metrics and coupled metrics of concern: When the bottleneck type is an accuracy bottleneck, the key optimization metric is the detection accuracy value, and the frame throughput and board-level power are coupled metrics of concern; when the bottleneck type is a throughput bottleneck, the key optimization metric is the frame throughput, and the detection accuracy value and board-level power are coupled metrics of concern; when the bottleneck type is a power consumption bottleneck, the key optimization metric is the board-level power, and the detection accuracy value and frame throughput are coupled metrics of concern. Based on the predicted values ​​of various performance indicators and fluctuation characteristics, as well as the target values ​​of various performance indicators and fluctuation characteristics, a first score, a second score, and a third score are calculated: the first score includes the positive difference between the predicted value of the key optimization indicator and its target value; the second score includes the positive difference between the predicted value of each coupled concern indicator and its target value; and the third score includes the degree of reduction of the predicted value of the fluctuation characteristic relative to its current value. A comprehensive score is obtained by weighted summation of the first, second, and third scores; the weight of the first score is greater than that of the second score, and the weight of the second score is greater than that of the third score.

9. The FPGA prototype energy efficiency verification and iteration method for power inspection according to claim 7, characterized in that, The strategy library includes: detection accuracy optimization strategies, throughput optimization strategies, power consumption optimization strategies, and / or interference suppression strategies; The detection accuracy optimization strategy is used to increase the global quantization bit width of the model, increase the bit width of the classification layer at the end of the network, and / or adjust the dynamic range of activation values. The throughput optimization strategies are used to increase the number of parallel channels in the convolutional computation unit, increase the clock frequency, increase the upper limit of the clock frequency, and / or adjust the on-chip cache size. The power optimization strategies are used to reduce voltage, reduce clock frequency, reduce switching activity, and / or skip calculations for zero weights. The interference suppression strategies are used to increase the upper limit of the voltage threshold, smooth the transition curve of voltage frequency with load, and / or reduce the clock frequency based on temperature.

10. The FPGA prototype energy efficiency verification and iteration method for power inspection according to claim 1, characterized in that, The method further includes a second stage, which involves randomly mixing images from each scene subsequence to generate a mixed sequence, and repeatedly performing the following steps until the performance indicators are met: The mixed sequence of image data is input into the FPGA prototype verification board for target detection, and the board-level power consumption data is acquired at the same time. Based on the target detection results and board-level power consumption data, the performance index of the hybrid sequence is calculated; Assess current performance metrics: If performance metrics are not met, determine the bottleneck type based on the relationship between the performance metrics and the performance target value, and update the hardware configuration plan according to the bottleneck type.

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