Fast recovery diode and power semiconductor device
By embedding a P+ type semiconductor island on the cathode side and introducing a heat-conducting structure on the anode side of the fast recovery diode, the problem of reverse recovery waveform oscillation under high voltage and high current conditions in traditional FRDs is solved, improving the reverse recovery safe operating area and stability of the device, making it suitable for high-end application scenarios such as flexible DC transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHUZHOU CRRC TIMES SEMICON CO LTD
- Filing Date
- 2026-01-15
- Publication Date
- 2026-05-29
AI Technical Summary
When traditional fast recovery diodes (FRDs) reverse recover under high voltage and high current conditions, the reverse recovery current is prone to step changes, causing waveform oscillations and leading to device breakdown failure, which cannot meet the safe operating area requirements for high voltage and high power applications.
Multiple P+ type semiconductor islands are embedded in the cathode-side semiconductor layer to form a composite structure. Holes are injected into the P+ type semiconductor islands to compensate for the electron concentration during reverse recovery, suppressing the reverse recovery current step. Low-temperature bonding transition metal layer and thermally conductive metal layer are introduced on the anode side to form an efficient heat conduction channel, optimizing reverse recovery characteristics and thermal management.
The reverse recovery softness factor of the FRD was improved, the peak electric field during the reverse recovery process was reduced, the safe operating area was widened, and the stability and reliability of the device under high voltage and high -diF/dt conditions were improved.
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Figure CN122121180A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a fast recovery diode and a power semiconductor device. Background Technology
[0002] In the field of power electronics, Insulated Gate Bipolar Transistors (IGBTs) and Integrated Gate Commutated Thyristors (IGCTs) are typically used in anti-parallel connection with Fast Recovery Diodes (FRDs). When the IGBT or IGCT is turned off, the FRD provides freewheeling current, preventing damage to the IGBT / IGCT due to overvoltage or overcurrent. As power systems develop towards higher voltage and higher power, high-voltage, high-current press-fit IGBTs and IGCTs are gradually being applied in key areas such as flexible DC transmission, placing higher demands on the performance of the matching FRDs: they need to have a wider safe operating area (SOA), i.e., capable of operating at higher currents, higher voltages, and higher current change rates (-di). F Under the condition of / dt), reverse recovery can be completed without failure.
[0003] However, traditional FRD cathodes are mostly single N-type. + The doped structure has a high peak reverse recovery voltage, which makes it prone to current step and waveform oscillation, leading to device breakdown failure, thus presenting a technical defect. Summary of the Invention
[0004] The purpose of this application is to provide at least one fast recovery diode and power semiconductor device, which can at least avoid the problem of FRD device failure caused by the oscillation of the reverse recovery waveform due to the step of the reverse recovery current.
[0005] To address the aforementioned technical problems, at least one embodiment of this application provides a fast recovery diode, comprising: The cathode electrode is configured as the cathode lead of the fast recovery diode and is used to realize the electrical connection to the external circuit. The cathode-side semiconductor layer includes a composite structure layer and an N-type semiconductor layer sequentially stacked along a direction away from the cathode electrode. The composite structure layer includes P+ type semiconductor islands and N+ type semiconductor layers. A plurality of the P+ type semiconductor islands are spaced apart and embedded in the N+ type semiconductor layer to optimize the reverse recovery characteristics of the device. An anode-side PN junction structure is located on the side of the cathode-side semiconductor layer away from the cathode electrode; The anode structure is located on the side of the anode-side PN junction structure away from the cathode-side semiconductor layer.
[0006] In an optional embodiment, the P+ type semiconductor islands are circular or regular polygonal in shape, and the plurality of P+ type semiconductor islands are regularly distributed in a regular polygonal pattern within the N+ type semiconductor layer.
[0007] In an optional embodiment, the anode structure includes an anode electrode and a low-temperature bonding transition metal layer stacked sequentially on the side away from the cathode-side semiconductor layer; the low-temperature bonding transition metal layer is configured as a heat-conducting channel in the junction termination region, and the anode electrode is configured as the anode lead of the fast recovery diode.
[0008] In an optional embodiment, the anode structure further includes a thermally conductive metal layer, which is pressed and fixed to the side of the low-temperature bonding transition metal layer away from the anode electrode to dissipate heat from the junction terminal region. The thermally conductive metal layer includes molybdenum metal.
[0009] In an optional embodiment, the anode-side PN junction structure includes an N-type drift region and a P-type semiconductor layer; The N-type drift region is adjacent to the cathode-side semiconductor layer, and the P-type semiconductor layer is located on the side of the N-type drift region away from the cathode-side semiconductor layer. The N-type drift region and the P-type semiconductor layer form a main PN junction.
[0010] In an optional embodiment, it further includes: The P+ type doped region is located between the anode electrode and the P type semiconductor layer, and is used to reduce the contact resistance between the anode electrode and the P type semiconductor layer.
[0011] In an optional embodiment, the doping concentration of the P+ type semiconductor island ranges from 1 × 10⁻⁶. 18 cm -3 ~1×10 22 cm -3 .
[0012] In an optional embodiment, the junction depth of the P+ type semiconductor island is 1 / 3 to 1 / 2 of the thickness of the cathode-side semiconductor layer.
[0013] At least one embodiment of this application also provides a power semiconductor device, including a fast recovery diode as described in any of the preceding claims.
[0014] In an optional embodiment, the fast recovery diode has a rated voltage greater than or equal to 4500V and a rated current greater than or equal to 1000A.
[0015] The fast recovery diode and power semiconductor device provided in this application, compared with the prior art, have a composite structure formed by interleaving multiple P+ type semiconductor islands as a substrate in the cathode-side semiconductor layer, including N-type and N+ type semiconductor layers. During the reverse recovery process of the FRD, the P+ type semiconductor islands inject holes into the N-type semiconductor layer. The holes injected by the P+ type semiconductor islands can compensate for the electron concentration during the reverse recovery period, avoid the step jump of the reverse recovery current, and suppress the N+ type semiconductor layer. - The peak electric field of the junction avoids the problem of FRD device failure caused by oscillation of the reverse recovery waveform due to the step of the reverse recovery current. This structure improves the reverse recovery softness factor of the FRD and reduces the peak electric field during the reverse recovery process, enabling it to operate under high voltage and high-di conditions. F Working safely under / dt improves the reverse recovery safe working area of FRD. Attached Figure Description
[0016] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0017] Figure 1 This is a schematic diagram of the structure of a fast recovery diode according to an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a fast recovery diode according to another embodiment of this application; Figures 3-11 This is a schematic diagram of the structure involved in the fabrication process of a fast recovery diode according to another embodiment of this application. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of this application to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.
[0019] To facilitate understanding of the embodiments of this application, relevant content about conventional FRDs will be introduced first.
[0020] The safe operating area of an FRD refers to the voltage, current, power, temperature, and switching stress (such as -di) during normal operation of the device. FWithin the range of parameters such as / dt), the device will not be damaged by electrical breakdown, thermal runaway, reverse recovery failure, etc.
[0021] For high-voltage, high-power scenarios (such as flexible DC transmission), the core requirement for a high-safety operating range is the ability to operate under higher reverse voltage (≥4500V), larger conduction current (≥1000A), and higher current change rate (-di). F Reverse recovery was completed under conditions of / dt>5000A / μs, and the junction terminal region temperature was stable with no risk of stress failure.
[0022] Traditional FRDs have the following technical limitations: they cannot operate at higher currents, higher voltages, and higher current change rates (-di). F Under the condition of / dt), reverse recovery can be completed without failure: (1) Poor reverse recovery characteristics: The cathode side is mostly a single N + In the case of a doped structure, the reverse recovery current will step, the reverse recovery peak voltage is high, the electrical stress is concentrated, and the reverse recovery waveform is prone to oscillation, which can lead to device breakdown failure and limit the safe operating area. Therefore, the traditional FRD cathode-side impurity distribution structure is difficult to balance dynamic performance (reverse recovery characteristics) and static performance (forward voltage drop).
[0023] The existing FRD anode-side structure design does not specifically enhance junction terminal thermal management and electrical performance adaptation, making the junction terminal prone to failure due to thermal and electrical stress, further compressing the safe operating area.
[0024] This application provides a high-voltage, high-power fast recovery diode, significantly improving its safe operating area and reliability, making it suitable for high-end applications such as flexible DC transmission. The embodiments of this application relate to a fast recovery diode. Compared to existing technologies, the embodiments of this application include an N-type semiconductor layer and a composite structure formed by interleaving multiple P+ type semiconductor islands on an N+ type semiconductor layer as a substrate. During the reverse recovery process of the FRD, P... + Holes are injected into the N-type semiconductor layer by the P+ type semiconductor islands. These holes can compensate for the electron concentration during reverse recovery, preventing a step jump in the reverse recovery current and suppressing the electron concentration in the N+ type semiconductor islands. - The peak electric field of the junction avoids the problem of FRD device failure caused by oscillation of the reverse recovery waveform due to the step of the reverse recovery current. This structure improves the reverse recovery softness factor of the FRD and reduces the peak electric field during the reverse recovery process, enabling it to operate under high voltage and high-di conditions. F Working safely under / dt improves the reverse recovery safe working area of FRD.
[0025] Example 1: The following is a detailed description of the implementation details of the fast recovery diode in this embodiment. The following content is only for the convenience of understanding and is not necessary for implementing this solution.
[0026] Embodiments of this application provide a fast recovery diode, comprising: The cathode electrode is configured as the cathode lead of a fast recovery diode and is used to realize the electrical connection to the external circuit. The cathode-side semiconductor layer includes a composite structure layer and an N-type semiconductor layer stacked sequentially in a direction away from the cathode electrode. The composite structure layer includes P+ type semiconductor islands and N+ type semiconductor layers. Multiple P+ type semiconductor islands are interleaved within the N+ type semiconductor layers to optimize the reverse recovery characteristics of the device. The anode-side PN junction structure is located on the side of the cathode-side semiconductor layer away from the cathode electrode; The anode structure is located on the side of the PN junction structure on the anode side that is far from the semiconductor layer on the cathode side.
[0027] like Figure 1 As shown, the fast recovery diode (FRD) includes a cathode-side semiconductor layer 100, a cathode electrode 200 located on one side of the cathode-side semiconductor layer 100, an anode-side PN junction structure 300 located on the other side of the cathode-side semiconductor layer 100, and an anode structure 400 located on the side of the anode-side PN junction structure 300 away from the cathode-side semiconductor layer 100.
[0028] Specifically, the cathode electrode 200 serves as the cathode lead of the fast recovery diode, enabling electrical connection between the device and the external circuit and providing a path for current outflow. The cathode electrode 200 is preferably made of aluminum (Al), which can be prepared by vacuum evaporation or PVD process. After subsequent alloying treatment, it forms an ohmic contact with the cathode-side semiconductor layer 100 with low contact resistance, reducing conduction losses.
[0029] In the cathode-side semiconductor layer 100, an N-type semiconductor layer 110 is used as the substrate, and multiple P+ type semiconductor islands 121 are embedded at intervals within the N-type semiconductor layer 110. The area outside the multiple P+ type semiconductor islands 121 is the N+ type semiconductor layer 122. The N+ type semiconductor layer 122 and the P+ type semiconductor islands 121 form a composite structure layer 120. The N+ type semiconductor layer 122 ensures current conduction capability. During the FRD reverse recovery process, the P+ type semiconductor islands 121 inject holes into the N-type semiconductor layer 110 to optimize the reverse recovery softness factor, prevent reverse recovery current step, reduce the reverse recovery peak voltage, and thus improve the reverse recovery safe operating area.
[0030] Specifically, by introducing a P-type island (P+ type semiconductor island 121) structure on the cathode side, it is equivalent to embedding multiple P-type islands in the N-type region of the cathode. When the FRD is in the reverse recovery process, these P-type islands inject holes into the N-type semiconductor layer, preventing the reverse recovery current from taking a step and suppressing the N-type current. - The peak electric field of the junction avoids the problem of FRD device failure caused by oscillation of the reverse recovery waveform due to the step of the reverse recovery current. This structure improves the reverse recovery softness factor of the FRD, reduces the peak voltage and peak electric field during the reverse recovery process, and enables it to operate under high voltage and high-di conditions. F Working safely under / dt improves the reverse recovery safe working area of FRD.
[0031] In one embodiment, the doping concentration of the P+ type semiconductor island 121 ranges from 1 × 10¹ 8 cm - ³~1×10²²cm - ³, ensuring that the region can form a low-resistance ohmic contact with the cathode electrode layer and inject the required concentration of holes.
[0032] In one embodiment, reference Figure 1 As shown, the junction depth of the P+ type semiconductor island 121 is 1 / 3 to 1 / 2 of the thickness of the cathode-side semiconductor layer 100, in order to balance the hole injection efficiency and the cathode-side current conduction capability. For example, the junction depth of the P+ type semiconductor island 121 is greater than that of the N+ type semiconductor layer 122.
[0033] In one embodiment, such as Figure 8 or Figure 9 As shown, an exemplary schematic diagram of the layout of P+ type semiconductor islands 121 within an N+ type semiconductor layer 122 is illustrated. The P+ type semiconductor islands 121 are circular or regular polygonal in shape, such as squares or regular hexagons. Multiple P+ type semiconductor islands 121 are distributed in a regular polygonal pattern within the N+ type semiconductor layer 122, such as equilateral triangles, squares, or regular hexagons, ensuring uniform hole injection and avoiding localized current concentration.
[0034] In one embodiment, such as Figure 1 As shown, the anode-side PN junction structure 300 includes an N-type drift region 310 and a P-type semiconductor layer 320 stacked sequentially. The N-type drift region 310 is adjacent to the cathode-side semiconductor layer 100 and is the core region of the device that withstands reverse voltage. The P-type semiconductor layer 320 is located on the side of the N-type drift region 310 away from the cathode-side semiconductor layer 100, and forms the main PN junction of the fast recovery diode with the N-type drift region 310, realizing the basic functions of forward conduction and reverse cutoff.
[0035] For example, by precisely controlling the resistivity and thickness of the N-type drift region 310, it can be further ensured that the device does not break down under high voltage conditions. For instance, setting the resistivity of the N-type drift region to the range of 200 Ω·cm-400 Ω·cm and the thickness to 400 μm-700 μm can improve the reverse breakdown capability.
[0036] In one embodiment, such as Figure 1 As shown, the fast recovery diode also includes a P+ type doped region 500 located between the anode electrode 410 and the P-type semiconductor layer 320, which is highly P+ type doped; the P+ type doped region 500 reduces the contact resistance between the anode electrode 410 and the P-type semiconductor layer 320, reduces contact loss during forward conduction, and optimizes the static performance of the device.
[0037] Example 2: According to an exemplary embodiment, most of the fast recovery diode in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that this embodiment is a specific implementation of the anode structure.
[0038] like Figure 2 As shown, the fast recovery diode (FRD) includes a cathode-side semiconductor layer 100, a cathode electrode 200 located on one side of the cathode-side semiconductor layer 100, an anode-side PN junction structure 300 located on the other side of the cathode-side semiconductor layer 100, and an anode structure 400 located on the side of the anode-side PN junction structure 300 away from the cathode-side semiconductor layer 100.
[0039] The anode structure 400 includes an anode electrode 410 and a low-temperature bonded transition metal layer 420, which are stacked sequentially on the side of the anode-side PN junction structure 300 away from the cathode-side semiconductor layer 100.
[0040] The anode electrode 410 is located at the anode lead of the fast recovery diode. It is preferably made of aluminum (Al) and has a thickness of 10μm to 20μm to achieve the anode electrical connection between the device and the external circuit.
[0041] The low-temperature bonded transition metal layer 420 is located in a high-efficiency heat conduction channel that serves as the junction terminal, and the material is preferably a Ti / Ni / Ag multilayer composite metal or gold (Au).
[0042] For example, the low-temperature bonding transition metal layer 420 is a Ti layer, a Ni layer, and an Ag layer stacked sequentially (Ti / Ni / Ag multilayer composite metal), which can be deposited by PVD or electroplating processes. Figure 2As shown, the anode structure 400 is located on the side of the P+ type doped region 500 away from the cathode-side semiconductor layer 100. When the low-temperature bonding transition metal layer 420 is a Ti / Ni / Ag multilayer composite metal, the preferred thickness of the Ti layer is 50nm~100nm, the preferred thickness of the Ni layer is 100nm~200nm to prevent Ag layer diffusion, and the preferred thickness of the Ag layer is 300nm~500nm to improve thermal conductivity. The low-temperature bonding transition metal layer 420 can be welded to the molybdenum metal 430 through a low-temperature bonding process of 200℃~300℃ to avoid high-temperature damage to the main PN junction and the cathode-side composite structure.
[0043] The junction termination region of an FRD (the edge region of the PN junction structure on the anode side) is a concentration area of thermal and electrical stress, making it prone to failure due to overheating or electrical breakdown. However, by using a low-temperature bonded transition metal layer, a highly efficient heat conduction channel can be formed at the anode junction termination. This channel can quickly dissipate heat from the junction termination region, reducing the junction termination temperature and minimizing thermal stress damage to the device. Simultaneously, good thermal management also helps improve the electrical breakdown tolerance of the junction termination, ultimately enhancing the safe operating area at the junction termination location.
[0044] In this embodiment, the thermal conductivity of the low-temperature bonded transition metal layer 420 is much higher than that of semiconductor materials. The low-temperature bonded transition metal layer 420 provides a highly efficient heat conduction channel for the junction termination, which can quickly dissipate the heat generated by the junction termination from the device and reduce the junction temperature. By improving the heat distribution of the junction termination, the damage of thermal stress to the junction termination is reduced, and the electrical breakdown withstand capability of the junction termination is indirectly improved, avoiding junction termination failure due to overheating or electrical stress.
[0045] Because traditional press-fit FRDs have a suspended junction terminal with no heat conduction path, in the blocked state, the junction terminal region generates heat due to leakage current. However, this heat cannot be dissipated through the electrodes, creating a positive thermal feedback loop that leads to increased temperature, increased leakage current, more heat, and further temperature increases, ultimately causing junction terminal breakdown and device failure. Therefore, in one embodiment, such as... Figure 2 As shown, the anode structure 400 also includes a thermally conductive metal layer 430 located on the side of the low-temperature bonded transition metal layer 420 away from the anode electrode 410.
[0046] For example, the thermally conductive metal layer 430 is pressed and fixed to the side of the low-temperature bonding transition metal layer 420 away from the anode electrode 410 by a low-temperature bonding process, for dissipating heat from the junction termination region. The thermally conductive metal layer 430 is preferably made of a metal with a thermal conductivity ≥150 W / (m·K) to ensure rapid heat dissipation from the junction termination. Simultaneously, the material must be compatible with the low-temperature bonding temperature to avoid semiconductor lattice defects or deterioration of PN junction characteristics due to high temperatures. The material can be silver (Ag), gold (Au), copper (Cu), or molybdenum (Mo). For example, the thermally conductive metal layer 430 is preferably made of molybdenum (Mo) metal with a thickness of 1.0 mm to 6.0 mm, which can quickly dissipate heat from the junction termination region, balance the temperature between the junction termination and the active region, and avoid failure caused by thermal stress. For example, a silver metal layer is attached to the surface of the molybdenum metal near the chip, and a solder layer is attached to the surface of the silver metal layer.
[0047] In this embodiment, the combination of the thermally conductive metal layer 430 and the low-temperature bonding transition metal layer 420 constitutes a thermally conductive path from the junction termination to the low-temperature bonding transition metal layer, and then to the thermally conductive metal layer and the packaging structure, which can directly conduct the heat generated by the junction termination to the external heat dissipation structure. Since the leakage current of semiconductor materials increases exponentially with increasing temperature, the reduction of the junction termination temperature directly suppresses the thermal excitation growth of leakage current, avoids excessive leakage current from further aggravating heat generation, and ensures the current stability of the device under long-term high-voltage blocking conditions.
[0048] Furthermore, as the edge of the anode-side PN junction structure 300, the anode structure 400 is prone to electric field concentration, and temperature increases can lead to a decrease in the breakdown field strength of the semiconductor material. The thermal management function of the thermally conductive metal layer 430 indirectly enhances the electrical performance of the junction termination. Specifically, the thermally conductive metal layer 430 dissipates heat, keeping the junction termination temperature constant, such as below 140°C, thus preventing the degradation of blocking capability caused by temperature increases. This ensures that the breakdown risk is reduced by more than 90% during long-term operation at the rated reverse voltage (≥4500V). The thermally conductive metal layer 430 also provides uniform heat dissipation, controlling the temperature distribution difference at the junction termination to within 5°C, suppressing local overheating, and widening the voltage and current boundaries of the reverse safe operating region by 20%.
[0049] In this embodiment, the combination of a thermally conductive metal layer and a low-temperature bonded transition metal layer not only solves the thermal runaway problem of traditional structures but also directly expands the reverse safe operating region and dynamic stress tolerance. Simultaneously, it considers the compatibility with industrial-scale processes and long-term stability, ultimately enabling the FRD to stably meet the requirements of rated voltage ≥4500V, rated current ≥1000A, and -di F The high-voltage, high-power requirements of / dt>5000A / μs have become one of the core technological guarantees for high-end application scenarios such as flexible DC transmission.
[0050] Example 3: The embodiments of this application also provide a method for fabricating a fast recovery diode. To achieve the above structure, the method for fabricating a fast recovery diode provided by this application includes the following specific steps: Step 10: Provide silicon wafers.
[0051] like Figure 3 As shown, an N-type silicon single crystal wafer with resistivity, thickness, diameter, and crystal orientation that meet the design requirements can be selected, and the anode surface of silicon wafer 101 is marked; the silicon wafer 101 is then cleaned and dried.
[0052] Step 11: Anode P-type doping.
[0053] The preferred P-type impurity for the anode is aluminum. After cleaning and drying the silicon wafer, it is placed into an aluminum pre-deposition process source tube and then placed in a diffusion furnace for aluminum impurity doping. After the process is completed, the resistivity of the thin film on the anode surface is measured. If it does not reach the design value, the aluminum pre-deposition operation is repeated until the thin film resistivity meets the requirements. Figure 4 As shown, a PNP-type vertical structure is formed inside silicon wafer 101 at this time.
[0054] Step 12: Remove the PN junction on the cathode surface.
[0055] In this step, photoresist or other corrosion-resistant materials are preferentially used to protect the anode surface of the silicon wafer. Then, an acid solution, such as a mixture of hydrofluoric acid and nitric acid, or an alkaline solution (such as potassium hydroxide solution), is used to etch the cathode surface to remove the PN junction on the cathode side. Figure 5 As shown, this forms a PN-type vertical structure inside the silicon wafer 101.
[0056] Step 13: Anode boron ion and cathode phosphorus ion implantation.
[0057] After cleaning and drying, silicon wafer 101 is placed in a diffusion furnace for oxidation, forming a thin SiO2 layer on the surface (not shown in the figure), with a thickness of 10nm~30nm, thus forming an amorphous structure on the silicon wafer surface.
[0058] P+ type impurities, such as boron ions, are implanted on the anode side of silicon wafer 101. N-type doping, such as phosphorus ions, is implanted on the cathode side. The implantation deflection angle and dosage are set according to the design values and process conditions, and the implantation order of boron ions and phosphorus ions can be interchanged.
[0059] Step 14: Deep-seated diffusion of aluminum, boron, and phosphorus impurities.
[0060] After ion implantation, silicon wafer 101 is cleaned and dried, then placed in a diffusion furnace for oxidation propagation. By controlling the diffusion temperature (1100℃~1250℃) and time, aluminum, boron, and phosphorus impurities are allowed to diffuse deep into the silicon wafer. Figure 6As shown, a P+PN-N type vertical structure is formed, namely, an anode-side PN junction structure 300 is formed. A P+ type doped region 500 is formed on one side of the P-type semiconductor layer 320 of the anode-side PN junction structure 300, and an N-type semiconductor layer 110 is formed on the cathode side. At the same time, a thick oxide layer (not shown in the figure) with a thickness of 1000nm~1500nm is formed on the silicon wafer surface for use as a mask in subsequent photolithography processes.
[0061] Step 15: Cathode-side P-type island boron ion implantation and diffusion.
[0062] like Figure 7 As shown, the thick oxide layer of the pre-set P-type island region on one side of the N-type semiconductor layer 110 in the silicon wafer 101 is removed by photolithography to expose the region to be doped; boron ions are implanted into the exposed P-type island region, and the implantation parameters are set according to the doping concentration and junction depth design value of the P+ type semiconductor island.
[0063] The silicon wafer 101 is then placed in a diffusion furnace for an oxidation advance process, allowing boron impurities to diffuse to the designed junction depth, forming a P+ type semiconductor island 121 on the cathode side of the silicon wafer 101, as shown below. Figure 7 As shown, at this time, the region perpendicular to the P-type island within the silicon wafer 101 forms a P+PN-NP+ type vertical structure.
[0064] like Figure 8 As shown, an exemplary schematic diagram illustrates the shape and distribution of the P+ type semiconductor islands 121. In this diagram, the P+ type semiconductor islands are circular in shape and arranged in a square configuration. Figure 9 As shown, an exemplary schematic diagram of another P+ type semiconductor island 121 shape and distribution is illustrated. In this diagram, the P+ type semiconductor islands are circular in shape and distributed in an equilateral triangle in relative positions.
[0065] Step 16: Phosphorus doping in the region outside the P-type island on the cathode side.
[0066] The thick oxide layer outside the P-type island (P+ type semiconductor island 121) region on the cathode surface of the silicon wafer is removed by photolithography; high-concentration phosphorus impurity doping is performed in this region using phosphorus pre-deposition or phosphorus ion implantation; the phosphorus impurities are diffused to the designed depth via thermal diffusion to form the N+ type semiconductor layer 122, and then the residual SiO2 layer on the silicon wafer surface is removed; such as Figure 10 As shown, the P+ type semiconductor island 121 and the N+ type semiconductor layer 122 constitute the composite structure layer 120, and the N-type semiconductor layer 110 and the composite structure layer 120 together constitute the cathode-side semiconductor layer 100. Figure 10 As shown, P+PN-NP+ type vertical structures are formed simultaneously in the P-type island region and P+PN-NN+ type vertical structures are formed in the region outside the P-type island.
[0067] Step 17: Electrode preparation and alloying.
[0068] like Figure 11 As shown, after cleaning the silicon wafer 101, it is placed in a vacuum evaporator to evaporate the aluminum layer, forming a cathode electrode 200 on the side corresponding to the semiconductor layer on the cathode side, and forming an anode electrode 410 on the side corresponding to the P+ type doped region. After aluminum evaporation, the silicon wafer 101 is placed in an alloy furnace and alloyed under a nitrogen protective atmosphere, such as at a temperature of 450℃~550℃ and a time of 30min~60min, so that an ohmic contact with low contact resistance is formed between aluminum and silicon, and finally a fast recovery diode is formed.
[0069] Step 18: Axial minority carrier lifetime adjustment and aluminum electrode size adjustment Proton implantation is performed on at least one of the cathode and anode surfaces of the silicon wafer. The implantation dose is set according to the axial minority carrier lifetime design value. After implantation, annealing treatment is performed (temperature 200℃~350℃) to repair ion implantation damage and precisely adjust the axial minority carrier lifetime of the chip to improve reverse recovery characteristics. The size of the aluminum electrode is adjusted to the design value through photolithography and etching processes; the order of proton implantation and annealing steps in this step can be interchanged.
[0070] Step 19: Silicon wafer cutting and deposition of anode low-temperature bonding transition metal layer.
[0071] Silicon wafers are cut into circular chips of a predetermined size using laser cutting or diamond cutting processes; for example... Figure 11 As shown, a low-temperature bonding transition metal layer 420, such as a Ti / Ni / Ag multilayer metal or Au, can be deposited on the anode electrode 410 surface of the chip by physical vapor deposition (PVD) or electroplating. The order of this step and the chip dicing step can be interchanged to form a fast recovery diode.
[0072] Step 20: Bonding of the anodic thermally conductive metal layer.
[0073] Furthermore, low-temperature bonding processes can also be employed, such as temperatures of 200℃~300℃ and pressures of 10MPa~20MPa. Figure 2 As shown, the low-temperature bonding transition metal layer 420 and the thermally conductive metal layer 430, such as a molybdenum sheet, are pressed together on the anode surface of the chip to form a stable thermal conductivity interface. A silver metal layer is attached to the surface of the molybdenum sheet near the chip, and a solder layer is attached to the surface of the silver metal layer.
[0074] Step 21: Terminal processing.
[0075] As shown in the figure, the bonded chip undergoes junction termination processing, with the junction termination area cut to the designed dimensions. An etching process is used to remove the mechanical damage layer on the junction termination surface, and a passivation layer (not shown in the figure) is deposited on the junction termination surface to isolate it from external moisture and contaminants. Fluororubber is coated onto the chip edges to form a protective rubber layer 600 to buffer the mechanical stress during packaging.
[0076] Step 22, Electron Irradiation and Performance Testing.
[0077] The chip is subjected to electron irradiation. By controlling the irradiation dose, the minority carrier lifetime of each region of the chip is uniformly adjusted to achieve the optimal trade-off between the device's dynamic parameters (reverse recovery loss) and static parameters (forward voltage drop). The chip's minority carrier lifetime, forward voltage drop, reverse breakdown voltage, and reverse recovery characteristics are tested. If the design values are not met, the electron irradiation dose is adjusted until the parameters are qualified. The qualified chips are packaged and then subjected to factory testing, including high-temperature reverse bias testing and reverse recovery parameter testing, to ensure device reliability.
[0078] Example 4: This application also provides a power semiconductor device, including the fast recovery diode from any of the above embodiments. This power semiconductor device can be used in high-voltage, high-power scenarios such as flexible DC transmission and high-voltage frequency converters. The fast recovery diode has a voltage ≥4500V and a current ≥1000A, and can be connected in anti-parallel with power switching devices such as IGBTs and IGCTs to achieve freewheeling and protection functions, thereby improving the safe operating range and operational stability of the entire power semiconductor device.
[0079] The fast recovery diode (FRD) in the power semiconductor device provided in this application has a cathode-side semiconductor layer comprising a composite structure with an N+ semiconductor layer as the substrate and multiple P+ type semiconductor islands embedded therein. During the reverse recovery process of the FRD, the P+ type semiconductor islands inject holes into the N-type semiconductor layer, improving the reverse recovery softness factor by more than 30% and reducing the peak reverse recovery voltage by 25%, effectively suppressing current step oscillations and avoiding high voltage and high-di voltage. F The dynamic avalanche failure under the / dt condition enables the device to operate stably at a rated voltage of ≥4500V and a rated current of ≥1000A, meeting the needs of high-end applications such as flexible DC transmission and filling the technological gap of high-voltage high-power FRD in China.
[0080] In addition, the combination of a low-temperature bonding transition metal layer and a thermally conductive metal layer on the anode side in the anode structure provides an efficient heat conduction channel for the junction terminal, reducing the junction terminal temperature by 40°C to 60°C and improving leakage current stability by 50%, thus breaking the positive feedback of thermal runaway in the traditional structure.
[0081] It should be understood that the terms "mechanism," "device," "component," etc., used in this application are merely one method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they can be replaced by other expressions.
[0082] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application. In practical applications, the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification, and various changes can be made to them in form and detail without departing from the spirit and scope of this application.
Claims
1. A fast recovery diode, characterized in that, include: The cathode electrode is configured as the cathode lead of the fast recovery diode and is used to realize the electrical connection to the external circuit. The cathode-side semiconductor layer includes a composite structure layer and an N-type semiconductor layer sequentially located away from the cathode electrode. The composite structure layer includes P+ type semiconductor islands and N+ type semiconductor layers. A plurality of the P+ type semiconductor islands are spaced apart and embedded in the N+ type semiconductor layer to optimize the reverse recovery characteristics of the device. An anode-side PN junction structure is located on the side of the cathode-side semiconductor layer away from the cathode electrode; The anode structure is located on the side of the anode-side PN junction structure away from the cathode-side semiconductor layer.
2. The fast recovery diode according to claim 1, characterized in that, The P+ type semiconductor islands are circular or regular polygonal in shape, and multiple P+ type semiconductor islands are distributed in a regular polygonal pattern within the N+ type semiconductor layer.
3. The fast recovery diode according to claim 1 or 2, characterized in that, The anode structure includes an anode electrode and a low-temperature bonding transition metal layer stacked sequentially on the side away from the cathode-side semiconductor layer; the low-temperature bonding transition metal layer is configured as a heat-conducting channel in the junction termination region, and the anode electrode is configured as the anode lead of the fast recovery diode.
4. The fast recovery diode according to claim 3, characterized in that, The anode structure further includes a thermally conductive metal layer, which is pressed and fixed to the side of the low-temperature bonding transition metal layer away from the anode electrode to dissipate heat from the junction terminal region. The thermally conductive metal layer includes molybdenum metal.
5. The fast recovery diode according to claim 3, characterized in that, The anode-side PN junction structure includes an N-type drift region and a P-type semiconductor layer; The N-type drift region is adjacent to the cathode-side semiconductor layer, and the P-type semiconductor layer is located on the side of the N-type drift region away from the cathode-side semiconductor layer. The N-type drift region and the P-type semiconductor layer form a main PN junction.
6. The fast recovery diode according to claim 5, characterized in that, Also includes: The P+ type doped region is located between the anode electrode and the P type semiconductor layer, and is used to reduce the contact resistance between the anode electrode and the P type semiconductor layer.
7. The fast recovery diode according to claim 1, characterized in that, The doping concentration range of the P+ type semiconductor island is 1×10⁻⁶. 18 cm -3 ~1×10 22 cm -3 .
8. The fast recovery diode according to claim 1, characterized in that, The junction depth of the P+ type semiconductor island is 1 / 3 to 1 / 2 of the thickness of the cathode-side semiconductor layer.
9. A power semiconductor device, characterized in that, Includes the fast recovery diode as described in any one of claims 1 to 8.
10. The power semiconductor device according to claim 9, characterized in that, The fast recovery diode has a rated voltage greater than or equal to 4500V and a rated current greater than or equal to 1000A.