SOI MOS device based on strain technology and preparation method thereof

By introducing silicon nitride reinforcement structures and high thermal conductivity paths into SOI MOS devices, the self-heating and total dose effects caused by buried oxide layer materials are resolved, thereby improving the device's radiation resistance and heat dissipation capabilities.

CN122121199APending Publication Date: 2026-05-29XI'AN PETROLEUM UNIVERSITY
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
XI'AN PETROLEUM UNIVERSITY
Filing Date
2026-01-28
Publication Date
2026-05-29

AI Technical Summary

Technical Problem

SOI MOS devices face challenges in resisting single-event effects and thermal conduction, especially due to the self-heating effect and total dose effect caused by the low thermal conductivity of the buried oxide layer material. Existing improvements such as material replacement or the addition of a silicon nitride sacrificial layer cannot effectively solve these problems.

Method used

The SOI buried oxide layer and silicon nitride reinforcement structure are fabricated using intelligent stripping technology. A high thermal conductivity path is formed by filling silicon nitride through local trenching. The threshold voltage is adjusted and the source and drain structures are prepared by ion implantation technology to form self-aligned source and drain electrodes. Finally, silicon nitride films are deposited on the substrate and gate surface as stress layers.

Benefits of technology

It effectively mitigates the total dose effect and self-heating effect, improves the device's radiation resistance and heat dissipation capacity, and suppresses threshold voltage drift and carrier mobility degradation.

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Abstract

The application discloses an SOI MOS device based on a strain technology and a preparation method thereof. The method comprises the following steps: providing a substrate; using an intelligent stripping technology to manufacture an SOI buried oxygen layer and a silicon nitride reinforcing structure, the SOI buried oxygen layer is located in the substrate, the silicon nitride reinforcing structure is located in the buried oxygen layer and is formed by locally slotting and filling silicon nitride; performing phosphorus doping on the substrate to adjust a threshold voltage; manufacturing a dummy gate on the surface of the upper body silicon, performing oxidation treatment on the sidewall of the dummy gate to form a sidewall; sequentially preparing a Halo and a source-drain extension region through an ion implantation technology; performing active region implantation to form self-aligned source and drain electrodes, removing the dummy gate, and manufacturing a gate in the exposed gate area; and depositing a silicon nitride film on the surface of the substrate and the gate as a stress layer to obtain the prepared SOI MOS device. By introducing the SOI buried oxygen layer and the silicon nitride reinforcing structure, the anti-radiation performance and the heat dissipation capacity of the SOI MOS device are optimized.
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