Method for manufacturing a power semiconductor device with a reduced oxygen concentration

Abstract

A method for forming a power semiconductor device, the method comprising: Providing a semiconductor wafer (101) with a phosphorus doping concentration of less than 10 15 / cm 3 , which has grown through a Czochralski process and has a first page (101a); Forming an n-type substrate doping layer (105) with phosphorus as the dopant in the semiconductor wafer (101) at the first side (101a), wherein the substrate doping layer (105) has a doping concentration of at least 10 17 / cm 3 , typically of at least 10 18 / cm 3 exhibits; Forming an epitaxial layer (110) on the first side (101a) of the semiconductor wafer (101) after forming the substrate doping layer (105) Images of a dopant layer (115) in the epitaxial layer (110) during growth of the epitaxial layer (110) by diffusion of dopants from the substrate dopant layer (105) into the epitaxial layer (110); and Forming a power semiconductor device (100) with the doping layer (115) as a functional layer of the power semiconductor device (100).

Description

TECHNICAL AREA

[0001] The embodiments described here relate to methods for manufacturing power semiconductor devices with a reduced oxygen concentration. BACKGROUND

[0002] To manufacture power devices, a so-called zoned fusion semiconductor substrate is used, which is doped during the semiconductor substrate fabrication process. A cost-effective alternative is Czochralski semiconductor materials, which can be supplied as large-diameter wafers. Zoned fusion substrates are limited to 200 mm. Semiconductor materials produced using the Czochralski process exhibit a high concentration of oxygen, which diffuses into the material during fabrication. Zoned fusion materials have a much lower oxygen concentration.

[0003] Interstitial oxygen can act as unwanted doping centers or influence the diffusion of dopants. Therefore, there is a desire to have a cost-effective semiconductor material with a low oxygen concentration. The following publications deal with semiconductor devices and / or their fabrication: US 2017 / 0018457A1, DE 102004060624A1, US 6271061B1, US 2017 / 0207124A1, US 2012 / 0056304A1, and DE 2130928A.

[0004] In light of the above, there is room for improvement. SUMMARY

[0005] The invention relates to a method for forming a power semiconductor device according to claim 1. According to one embodiment, a method for forming a power semiconductor device is provided. The method comprises the following: providing a semiconductor wafer grown by a Czochralski process and having a first side; forming an n-type substrate doping layer in the semiconductor wafer at the first side, wherein the substrate doping layer has a doping concentration of at least 10 17 / cm 3 , typically of at least 10 18 / cm 3 exhibits; and forming an epitaxial layer on the first side of the semiconductor wafer after forming the substrate doping layer.

[0006] According to one embodiment, a power semiconductor device is provided. The power semiconductor device comprises the following: an epitaxial layer with a first side and a second side, wherein at least one pn junction is formed in the epitaxial layer, and a dopant layer of a first conductivity type formed in the epitaxial layer at the second side, wherein the dopant layer has a doping concentration of at least 10 17 / cm 3 , typically of at least 10 18 / cm 3 exhibits an oxygen concentration in the epitaxial layer that decreases exponentially, at least in part, from the doping layer at the second side to the first side.

[0007] Additional features and advantages will become apparent to a specialist upon reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The components in the figures are not necessarily to scale; instead, the emphasis is on illustrating the principles of the invention. Furthermore, identical reference numerals in the figures denote corresponding parts. The following applies to the drawings: Fig. Figure 1 illustrates a power semiconductor device according to embodiments; Fig. Figures 2A to 2C illustrate processes according to embodiments in a cross-sectional view of a semiconductor substrate; Fig. 2A and Fig. 3B illustrates further processes according to embodiments in a cross-sectional view of a semiconductor substrate; Fig. Figure 4 illustrates a power semiconductor device according to further embodiments; Fig. 5A and Fig. 5B illustrates further processes according to embodiments in a cross-sectional view of a semiconductor substrate; Fig. Figures 6A to 6C illustrate processes according to embodiments in a cross-sectional view of a semiconductor substrate; Fig. Figure 7 illustrates a flowchart of a process according to embodiments; Fig. 8A and Fig. 8B illustrates 2D graphs of two forward voltage measurements; Fig. Figure 9 illustrates a simulation graph of the oxygen concentration in a semiconductor wafer after the growth of an epitaxial layer on the semiconductor wafer; Fig. 10A and Fig. 10B illustrates graphs showing the doping concentration of a substrate doping layer; Fig. Figure 11 illustrates graphs showing concentration profiles for an implanted phosphorus concentration and oxygen concentration; and Fig. Figure 12 shows graphs that illustrate a change in the forward voltage drop. DETAILED DESCRIPTION

[0009] The following detailed description refers to the accompanying drawings, which form part thereof and illustrate specific embodiments in which the invention can be practiced. In this context, directional terminology such as "top," "bottom," "front," "back," "anterior," "rear," "side," "vertical," etc., is used with reference to the orientation of the described figure(s). These terms are intended to encompass various orientations of the device in addition to those shown in the figures. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for illustrative purposes and is in no way limiting.Furthermore, terms such as "first," "second," and the like are used to describe various elements, areas, sections, etc., and these are not intended to be limiting. Throughout the entire description, the same terms refer to the same elements. It is understood that other embodiments may be used and structural or logical modifications may be made without deviating from the scope of protection of the present invention. The following detailed description is therefore not to be understood in a limiting sense, and the scope of protection of the present invention is defined by the accompanying claims. The described embodiments use specific language, which is not to be interpreted as limiting the scope of protection of the attached claims.

[0010] In this description, a second surface of a semiconductor substrate is considered to be formed by the bottom or back surface, while a first surface is considered to be formed by the top, front, or main surface of the semiconductor substrate. The terms "above" and "below," as used in this description, therefore describe the relative position of one structural feature with respect to another, taking this orientation into account.

[0011] The terms "electrical connection" and "electrically connected" describe an ohmic connection between two elements.

[0012] Some embodiments are described below with reference to the figures. Each example is provided as an explanation of the disclosure and is not intended to limit the disclosure. Furthermore, features illustrated or described as part of an embodiment may be applied to or combined with other embodiments to obtain yet another embodiment. The description is intended to include such modifications and variations.

[0013] The embodiments illustrated in the figures relate mainly, but are not limited to, power semiconductor devices. These devices typically include a first main electrode on the top or first side of a semiconductor substrate and a second main electrode on the bottom or second side of the semiconductor substrate. A current path is defined between the first and second main electrodes, extending across the at least one pn junction formed in the semiconductor substrate between the first and second sides. The current path can be controlled by a control electrode, also referred to as a gate electrode.

[0014] Next, an embodiment is described with reference to Fig. 1 described.

[0015] Fig. Figure 1 shows a power semiconductor device 100. For example, the power semiconductor device 100 can be an insulated-gate bipolar transistor (IGBT), a diode such as a freewheeling diode, or the like. According to embodiments, the power semiconductor device 100 can be designed for a voltage of 100 V or higher and / or 1200 V or lower.

[0016] The power semiconductor device 100 comprises an epitaxial layer 110 with a first side 110a and a second side 110b, wherein at least one pn junction is formed in the epitaxial layer 110. A dopant layer 115 of a first conductivity type can be formed in the epitaxial layer 110 at the second side 110b. The dopant layer can contain at least one dopant of the first conductivity type with a dopant concentration above a certain impurity level. Specifically, the dopant layer 115 can have a dopant concentration of at least 10 17 / cm 3 , typically of at least 10 18 / cm 3exhibiting the following characteristics: The dopant of the first conductivity type can be an n-type dopant, such as a group V material. For example, the dopant can contain phosphorus. Specifically, one of the at least one dopant can be phosphorus. According to embodiments, the dopant layer can contain only one dopant, for example, phosphorus.

[0017] In addition to the dopant concentration of the dopant of the first conductivity type, the epitaxial layer 110 can contain oxygen with an oxygen concentration, i.e., a concentration of oxygen in the epitaxial layer. In particular, the oxygen concentration in the epitaxial layer 110 can decrease exponentially, at least in part, from the dopant layer 115 at the second side 110b to the first side 110a.

[0018] Fig. Figures 2A to 2C illustrate processes according to embodiments in a cross-sectional view of a semiconductor substrate 101. In particular, they show Fig. 2A to 2C different phases of a method for forming the power semiconductor device 100.

[0019] As in Fig. As shown in Figure 2A, a semiconductor wafer 101 grown by a Czochralski process can be provided. The semiconductor wafer 101 can include a first side 101a. Furthermore, the semiconductor wafer 101 can include a second side that faces the first side 101a.

[0020] In the context of the present disclosure, a Czochralski process, such as a Czochralski process for growing semiconductor wafer 101, can be considered a crystal growth method used to obtain single crystals of semiconductors (e.g., silicon, germanium, and gallium arsenide). In particular, a Czochralski process can be used to grow silicon (Si). A semiconductor wafer 101 with a diameter of 300 mm or more can be grown in a Czochralski process. Specifically, semiconductor wafers with a larger diameter than those grown in other processes, such as a zone melting process, can be grown using a Czochralski process.

[0021] On the other hand, a semiconductor wafer 101 grown by a Czochralski process contains a higher impurity concentration of oxygen, nitrogen, and / or carbon. In the case of a magnetic Czochralski process, the incorporation of oxygen can be reduced by applying a magnetic field during the drawing process. However, a semiconductor wafer grown by a magnetic Czochralski process exhibits a significantly higher oxygen concentration compared to a semiconductor wafer grown by a zone melting process. In the context of the present disclosure, an oxygen concentration may specifically refer to a concentration of interstitial oxygen.

[0022] Specifically, a semiconductor wafer grown by a zone melting process can have an oxygen concentration of less than 1·10 16 cm -3exhibit, whereas a semiconductor wafer grown by a Czochralski process can have an oxygen concentration two orders of magnitude greater, i.e., 1·10 17 cm -3 and 1·10 18 cm -3 For the simplest and most cost-effective Czochralski material, the oxygen concentration can even be greater than 1 × 10⁻⁶. 18 cm -3Oxygen, specifically interstitial oxygen, tends to form thermal donors in a temperature range of 300 °C to 550 °C due to interactions with point defects in the semiconductor lattice, e.g., Si lattice (vacancies, intrinsic interstitial atoms). A distinction can be made between deep thermal double donors (TDDs), which can be considered oxygen complexes and may contain three or more oxygen atoms, and shallow thermal donors (STDHs), whose formation requires the additional presence of hydrogen and which are therefore mainly observed after proton irradiation. Since proton irradiation is typically a process performed during BEOL (back-end-of-line) processing, i.e., from the second side of the semiconductor wafer 101 and / or the epitaxial layer 110, e.g.,To form donors for a field stop of the power semiconductor device 100, a desired dose for the charge quantity in the field stop can only be ensured if the concentration of TDD complexes (which can correlate with the oxygen concentration) does not become too high. Furthermore, there can be an interaction with carbon, which can also affect the doping efficiency of the proton irradiation.

[0023] In order to enable a semiconductor wafer grown by a Czochralski process, such as semiconductor wafer 101, to be used to form a power semiconductor device, such as power semiconductor device 100, diffusion of oxygen from the semiconductor wafer to layers formed on the semiconductor wafer can be reduced.

[0024] According to embodiments, an n-type substrate doping layer 105 can be placed in the semiconductor wafer 101 at the first side 101a (see e.g. Fig. 2B). The n-type substrate doping layer 10 can have a high doping concentration of an n-type dopant. For example, the doping layer 105 can have a doping concentration of at least 10 17 / cm 3 , typically of at least 10 18 / cm 3 exhibit. Furthermore, the doping layer 105 can be a surface layer, i.e., the doping layer 105 can have a small thickness.

[0025] The substrate doping layer 105 can have a retarding effect on the oxygen diffusion from the semiconductor wafer 101 to a layer formed on the substrate doping layer 105. In particular, the substrate layer 105 can reduce the amount of oxygen diffusing from the semiconductor wafer 101 to a layer formed on the substrate doping layer 105.

[0026] As in Fig. As shown in Figure 2C, an epitaxial layer 110 can be formed on the first side 101a of the semiconductor wafer 101, particularly after the formation of the substrate doping layer 105. That is, the epitaxial layer 110 can be formed on the substrate doping layer 105. Accordingly, oxygen diffusion from the semiconductor wafer 101 to the epitaxial layer 110 can be reduced. In particular, oxygen diffusion from the semiconductor wafer 101 to the epitaxial layer 110 can be reduced to a level that is lower than it would occur without the substrate doping layer 105.

[0027] Furthermore, heat treatment can be performed before the epitaxial layer 110 is formed. Due to the heat treatment, oxygen can diffuse out of the semiconductor wafer 101. Accordingly, the amount of oxygen in the semiconductor wafer 101 can be reduced when the epitaxial layer 110 is formed. Therefore, an epitaxial layer 110 with an even lower oxygen content can be provided. In embodiments, a dose of oxygen diffusion from the semiconductor wafer 101 to the epitaxial layer 110 can be controlled by the growth of the epitaxial layer to, for example, 3.5 × 10⁻⁶. 13 cm -2 The amount of oxygen diffusing into the epitaxial layer 110 can be reduced. In particular, heat treatment can reduce the amount of oxygen diffusing into the epitaxial layer 110 by approximately 25%. For example, an epitaxial layer 110 can be provided in which the oxygen concentration is 3 × 10⁻⁵. 17 cm -3on the second page 110b to a non-critical value of approximately 1·10 17 cm -3 decreases within 1-2 µm.

[0028] According to the embodiments described herein, the dopant layer 115 of the first conductivity type can be formed in the epitaxial layer 110 during the growth of the epitaxial layer 110. In particular, the dopant layer 115 can be formed by diffusion of dopants from the substrate dopant layer 105 into the epitaxial layer 110. Accordingly, the dopant layer 115 can have the same type of dopants as the substrate dopant layer 105. According to the embodiments described herein, the dopant layer 115 can have a thickness of 0.5 µm or greater, specifically 0.7 µm or greater, and in particular 1.0 µm or greater.

[0029] Additionally or alternatively, heat treatment can also be carried out before the substrate doping layer 105 is applied. This can further improve the effect described above.

[0030] For example, the substrate doping layer 105 may have a high concentration of phosphorus. During the growth of the epitaxial layer 110 on the substrate doping layer 105, some of the phosphorus dopants may diffuse from the substrate doping layer 105 into the epitaxial layer 110 and may therefore form the doping layer 115 with a higher phosphorus concentration than an adjacent part of the epitaxial layer 110.

[0031] According to the embodiments described here, the dopant layer 115 has a higher doping concentration than an adjacent part of the epitaxial layer 110. Accordingly, the dopant layer 115 can be used as a functional layer of the power semiconductor device 100. For example, in the case of a MOSFET, the dopant layer 115 can be used as a drain zone. Furthermore, in the case of a diode, the dopant layer 115 can be used as a cathode emitter.

[0032] As in Fig. As illustrated by example in Figure 3B, the method for forming the power semiconductor device 100 can include one or more FEOL (Front-End-Of-Line) processes, such as forming pn / np junctions, forming metallizations, insulations, gate module formation, 5. source and drain module formation, and the like.

[0033] Fig. Figure 3B shows an example of the formation of an upper dopant layer 125 or a dopant region 125 from the first side 110a of the epitaxial layer 110. For example, the upper dopant layer 125 can contain dopants of the first conductivity type. That is, the dopant layer 115 and the upper dopant layer 125 can be of the same conductivity type. In particular, the first conductivity type can be an n-type. Accordingly, the dopant layer 115 and the upper dopant layer 125 can be n-type layers.

[0034] Furthermore, the epitaxial layer 110 can be undoped or can contain dopants of a first conductivity type. Similarly, if the dopant layer 115 contains n-type dopants, the epitaxial layer 110 can also contain n-type dopants. According to the embodiments described here, a pn junction can be formed in the epitaxial layer 110 either between the background doping of the epitaxial layer 110 and an additional p-type dopant layer, or between the dopant layer 115 and the additional p-type dopant layer.

[0035] Furthermore, an np junction of the epitaxial layer 110 can be formed by creating the upper dopant layer 125. According to the embodiments described here, at least one pn junction and at least one np junction can be formed in the epitaxial layer 110. In particular, an emitter zone can be formed between the second face 110b and the np junction, a base zone can be formed between the np junction and the pn junction, and / or a body zone can be formed between the pn junction and the first face 110a. For example, the emitter zone can correspond to the additional p-type dopant layer, and / or the body zone can correspond to the upper dopant layer 125. The base zone or drift zone can be the portion of the epitaxial layer 110 between the additional p-type dopant layer and the upper dopant layer 125.According to the embodiments described herein, the emitter zone can have a thickness of at least 2% of the thickness of the base zone. In particular, the thickness of the emitter zone can be at least within the range of one thickness variation of the base zone.

[0036] According to one embodiment, the power semiconductor device is an IGBT having, extending from the second side 110b to the first side 110a, an emitter zone or emitter region of a second conductivity type, such as p-doped, an optional field-stop zone or field-stop region of the first conductivity type, such as n-doped, a drift zone or drift region of a first conductivity type, also referred to as the base zone, a body zone or body region of the second conductivity type, and a source zone or source region of the first conductivity type. The field-stop zone has a higher doping concentration than the drift zone.

[0037] According to one embodiment, the power semiconductor device is a MOSFET having, extending from the second side 110b to the first side 110a, a drain zone or drain region of a first conductivity type, an optional field-stop zone or field-stop region of a first conductivity type, a drift zone or drift region of a first conductivity type, a body zone or body region of a second conductivity type, and a source zone or source region of a first conductivity type. The field-stop zone has a higher doping concentration than the drift zone.

[0038] According to the embodiments described here, although not shown in the figures, a first metallization can be formed on the epitaxial layer 110. Additionally or alternatively, a second metallization can be formed on the second side of the semiconductor wafer, opposite the first side 101a. Specifically, the second metallization can be formed without thinning the semiconductor wafer, e.g., on the unstretched semiconductor wafer. Furthermore, the second metallization can be formed after thinning the semiconductor wafer 101, e.g., after at least partial removal of the semiconductor wafer 101.

[0039] According to the embodiments described here, the semiconductor wafer 101 can be at least partially removed after the formation of the epitaxial layer 110 (see e.g. Fig. 4) be removed. In particular, the semiconductor wafer 101 can be removed after the pn junction has been formed. For example, the semiconductor wafer 101 can be removed by etching the material of the semiconductor wafer 101. The removal of the semiconductor wafer 101 can be considered part of and / or the beginning of the BEOL processing. The BEOL processing can include some processing operations, such as forming the second metallization. In particular, BEOL processing can include some processing operations that are performed on the second side of the semiconductor wafer 101.

[0040] According to the embodiments described herein, the semiconductor wafer 101 can be removed to such an extent that the substrate doping layer 105 is exposed. Accordingly, the exposed substrate doping layer 105 can be part of the power semiconductor device 100. For example, the substrate doping layer 105 can function as a high-conductivity layer of the power semiconductor device 100. Furthermore, the substrate doping layer 105 can be accessible for further processing operations. For example, a metal layer can be formed on the exposed substrate doping layer 105. Additionally or alternatively, the exposed substrate doping layer 105 can be structured and / or patterned.

[0041] Alternatively, the semiconductor wafer 101 can be completely or substantially completely removed. In particular, the semiconductor wafer 101 can be removed to such an extent that the dopant layer 115 is exposed. Accordingly, the exposed dopant layer 115 can be accessible for further processing operations. For example, a metal layer can be formed on the exposed dopant layer 115. Additionally or alternatively, the exposed dopant layer 115 can be structured and / or patterned from the first side 101a.

[0042] Fig. Figure 5A illustrates the formation of a glass layer 102 to form the substrate doping layer 105.

[0043] According to the embodiments described herein, a glass layer 102 can be formed on the first side 101a of the semiconductor wafer 101. The glass layer 102 can contain dopants. Specifically, the upper glass layer 102 can contain dopants of the first conductivity type. In particular, the glass layer 102 can contain phosphorus. Furthermore, the semiconductor wafer 101 can be subjected to heat treatment. The heat treatment can drive the dopants into the semiconductor wafer 101, thereby forming the substrate doping layer 105.

[0044] According to the embodiments described here, the semiconductor wafer 101 is exposed at an elevated temperature to an oxidation gas atmosphere containing a gaseous dopant precursor in order to form the glass layer 102. For example, the dopant precursor can contain phosphine (PH3).

[0045] The raised temperature can be equal to or greater than 750 °C, specifically equal to or greater than 900 °C, particularly equal to or greater than 1000 °C, and / or equal to or less than 1450 °C, specifically equal to or less than 1300 °C, particularly equal to or less than 1200 °C. According to the embodiments described herein, the glass layer 102 can be at a temperature of equal to or greater than 750 °C, specifically equal to or greater than 900 °C, particularly equal to or greater than 1000 °C, and / or equal to or less than 1450 °C, specifically equal to or less than 1300 °C, particularly equal to or less than 1200 °C.

[0046] The semiconductor wafer 101 can be exposed to the elevated temperature and / or the oxidation gas atmosphere for 120 minutes or more, specifically 180 minutes or more, in particular 210 minutes or more, and / or 360 minutes or less, specifically 300 minutes or less, in particular 270 minutes or less.

[0047] According to the embodiments described here, the glass layer 102 can be removed before the semiconductor wafer 101 is subjected to heat treatment.

[0048] According to the embodiments described herein, the heat treatment for driving the dopants into the semiconductor wafer 101 can be carried out at a temperature of 800 °C or greater, specifically 900 °C or greater, specifically 1000 °C or greater, in particular 1100 °C or greater, specifically 1400 °C or less, in particular 1300 °C or less.

[0049] The semiconductor wafer 101 can be subjected to heat treatment for driving the dopants into the semiconductor wafer 101 for 60 minutes or more, specifically 90 minutes or more, in particular 110 minutes or more, and / or 180 minutes or less, specifically 150 minutes or less, in particular 130 minutes or less.

[0050] According to the embodiments described herein, the substrate doping layer 105 can have a thickness of 5 µm or greater, specifically 10 µm or greater, in particular 15 µm or greater, and / or 30 µm or less, specifically 25 µm or less, in particular 20 µm or less.

[0051] Furthermore, the substrate doping layer 105 can have a doping concentration of at least 10 17 / cm 3 , especially of at least 10 18 / cm 3, especially of 10 19 / cm 3 exhibit very high doping concentrations of 10 20 / cm 3or even more can be obtained. Doping concentrations can be measured by spreading resistance profiling (SRP) and / or secondary ion mass spectrometry (SIMS) analysis. In particular, the process parameters for forming the substrate doping layer 105 can be optimized such that, on the one hand, the doping concentration is high enough to ensure diffusion of a certain amount of dopants into the epitaxial layer 110. On the other hand, the process parameters for forming the substrate doping layer 105 can be optimized such that the doping concentration in the substrate doping layer 105 is not too high, e.g., does not reach saturation, which could lead to deformation of the lattice of the semiconductor wafer 101 and, consequently, to impaired growth of the epitaxial layer 110 on the semiconductor wafer 101.

[0052] Fig. Figure 5B illustrates the formation of the substrate doping layer 105 by implantation.

[0053] According to the embodiments described here, dopants can be implanted into the first face 101a of the semiconductor wafer 101. The semiconductor wafer 101 can be subjected to heat treatment to drive the dopants into the semiconductor wafer 101, thereby forming the substrate doping layer 105. For example, the dopants can include n-type dopants, such as phosphorus.

[0054] According to the embodiments described here, the dopants are added in a dose of at least 10 14 / cm 2 , especially of at least 5·10 14 / cm 2 , in particular of at least 10 15 / cm 2 implanted.

[0055] According to the embodiments described herein, the heat treatment for driving the dopants into the semiconductor wafer 101 can be carried out at a temperature of 800 °C or greater, specifically 900 °C or greater, specifically 1000 °C or greater, in particular 1100 °C or greater, and / or 1400 °C or less, specifically 1300 °C or less, in particular 1200 °C or less.

[0056] According to the embodiments described herein, the heat treatment for driving the dopants into the semiconductor wafer 101 can be carried out for 100 minutes or more, in particular 400 minutes or more, in particular 700 minutes or more, specifically 900 minutes or more, in particular 1000 minutes or more, and / or for 1500 minutes or less, in particular 1300 minutes or less, in particular 1200 minutes or less. According to the embodiments described herein, the diffusion time can be made shorter the higher the temperature. Accordingly, a shorter diffusion time can be compensated for by a high temperature, and vice versa.

[0057] If embodiments are implemented, a doping concentration of approximately 1.5·10⁻⁶ at the first side 101a of the conductive wafer 101 can be achieved. 19 cm -3The thickness of the substrate doping layer 105 can be similar to or equal to the thickness obtained by the process involving the glass layer 102, with reference to Fig. 5A is described. In contrast to the one with reference to Fig. In the process described in section 5A, the implanted dopants are electrically activated, and the achievable doping concentration is below the upper values ​​described for the glass layer process. In particular, the doping concentration of the implantation process typically results in a concentration below a saturation level. Therefore, no lattice deformation occurs.

[0058] Fig. Figures 6A to 6C show further FEOL processes. In particular, the FEOL processes can be carried out while the substrate wafer 101 is attached to the epitaxial layer 110.

[0059] According to the embodiments described here, a trench 130 can be made in the epitaxial layer 110 (see e.g. Fig. 6A). The trench 130 can comprise a side wall 130b and a bottom surface 130a. The side wall 130b can be considered the circumferential surface, which is substantially parallel to a direction extending from the first side 110a to the second side 110b of the epitaxial layer 110, i.e., a top-bottom direction. A dimensional extension of the side wall 130b in the top-bottom direction can be considered a depth of the trench 130. The bottom surface 130a can be considered the surface of the trench 130, which is substantially perpendicular to the side wall 130b. A dimensional extension of the bottom surface 130a along the direction substantially perpendicular to the top-bottom direction can be considered a width of the trench 130.

[0060] Without being limited to this, the trench 130 can be formed, for example, by forming a hard mask (not shown) or a photoresist (not shown) on the epitaxial layer 110, specifically on the first side 110a of the epitaxial layer 110. For example, the hard mask can be formed by depositing an inorganic material, such as an oxide. An example is the deposition of TEOS (tetraethyl orthosilicate). A photoresist can be deposited on the deposited inorganic material. A portion of the photoresist corresponding to the location of the trench 130 to be formed can be removed by photolithography techniques, exposing a portion of the deposited material corresponding to the location of the trench 130. Similarly, the portion of the deposited material corresponding to the trench 130 can be removed, for example, by etching, to form the hard mask. The photoresist can then be removed.The trench 130 can be formed by etching the epitaxial layer 110 using the hard mask as an etching mask. According to the embodiments described here, the trench 130 can be formed such that it has an aspect ratio of depth to smallest lateral extent of at least 2:1, in particular at least 4:1.

[0061] As in Fig. As shown in Figure 6A, more than one trench 130 can be formed in the epitaxial layer 110. In particular, at least one trench 130 can be formed in the epitaxial layer 110. Specifically, several trenches 130 can be formed in the epitaxial layer 110. Accordingly, features described with reference to one trench 130 can, in the case of more than one trench 130, be a subset of all trenches 130, unless otherwise specified.

[0062] As in Fig. As shown in Figure 6B, an auxiliary layer 132 can be formed on the side wall 130b and the underside 130a of the trench 130. For example, the auxiliary layer 132 can be an insulating layer 132. Furthermore, the auxiliary layer 132 can comprise several sublayers, such as a first auxiliary layer, a second auxiliary layer, a third auxiliary layer, etc. The sublayers of the auxiliary layer 132 can be made of different materials. The sublayers of the auxiliary layer 132 can be formed in a similar manner.

[0063] The auxiliary layer 132 can be formed by depositing an auxiliary material on the epitaxial layer 110 and / or in the trench 130, specifically in such a way that the underside 130b of the trench 130 is covered, and can extend from the underside 130a of the trench 130 along the side walls 130b of the trench 130 to the first side 110a of the epitaxial layer 110. For example, the auxiliary material can be deposited by CVD (Chemical Vapor Deposition), HTO-CVD (High Temperature Oxide CVD), HDP-CVD (High-Density Plasma Chemical Vapor Deposition), TEOS deposition (TEOS: Tetraethyl Orthosilicate), PSG deposition (PSG: Phosphorosilicate Glass), or BPSG deposition (BPSG: Boron Phosphorosilicate Glass). The auxiliary material can be an oxide, such as silicon dioxide, silicon dioxide, hafnium oxide, or zirconium oxide.Furthermore, the auxiliary material can be a combination of an oxidized and deposited oxide, such as silicon dioxide.

[0064] As in Fig. As shown in Figure 6C, a filler material 140 can be deposited on the auxiliary layer 132 to at least partially fill the trench 130. For example, the filler material 140 can be a conductive material 140. Specifically, the conductive material 140 can be a metal compound or a doped, e.g., phosphorus-doped, or undoped polycrystalline semiconductor material, such as poly-Si, doped amorphous silicon, tungsten silicide, refractory metal silicide, titanium nitride, refractory metal, and / or combinations thereof.

[0065] Fig. Figure 7 illustrates a method 300 for forming a power semiconductor device 100. At block 310, a semiconductor wafer, such as the semiconductor wafer 101 grown by a Czochralski process and having a first side 101a, can be provided. At block 320, an n-type substrate doping layer, such as the substrate doping layer 105, can be formed in the semiconductor wafer at the first side. The substrate doping layer can have a doping concentration of at least 10 17 / cm 3 , typically of at least 10 18 / cm 3 exhibit. In block 330, an epitaxial layer, such as epitaxial layer 110, can be formed on the first side of the semiconductor wafer after the formation of the substrate doping layer.

[0066] Fig. 8A and Fig. Figure 8B illustrates 2D graphs of two forward voltage measurements performed on two different conventional 1200 V freewheeling diodes formed using different semiconductor wafers as substrates. Specifically, the diode made of... Fig. 8A uses a semiconductor wafer grown through a Czochralski process, while for the diode made of Fig. 8B uses a semiconductor wafer grown by a magnetic Czochralski process. As outlined here, these semiconductor wafers can differ in their oxygen concentration. In particular, the semiconductor wafer can be made of Fig. 8B, which was grown using a magnetic Czochralski process, has a lower oxygen concentration than the semiconductor wafer made of Fig. 8 A, which grew through a Czochralski process. As from Fig. 8A and Fig. As can be seen in Figure 8B, the forward voltage drop varies considerably across the surface of conventional freewheeling diodes. The semiconductor wafer is typically removed by etching during BEOL processing. However, the etching is usually not completely homogeneous, resulting in varying remaining thicknesses of the semiconductor wafer or the layer formed on top of it. Since the semiconductor wafer material and / or the layer formed on top of it typically has a relatively low conductivity, the resistivity of the power semiconductor device along the top-and-side will depend on the remaining amount of semiconductor wafer material or the layer formed on top of it, leading to the inhomogeneous forward voltage drop distribution shown in Figure 8B. Fig. 8A and Fig. 8 B is shown. A difference in the drop in forward voltage between Fig. 8A and Fig. 8B can be caused by a difference in oxygen concentration and / or oxygen diffusion out of the semiconductor wafers. As outlined above, the semiconductor wafer can consist of Fig. 8B, which was grown using a magnetic Czochralski process, has a lower oxygen concentration than the semiconductor wafer made of Fig. 8A, which has grown through a Czochralski process, exhibits a different characteristic of the drop in forward voltage.

[0067] According to the embodiments described herein, the dopant layer 115 and / or the substrate dopant layer 105 can provide a high conductivity range during at least partial removal of the semiconductor wafer 101. Specifically, the dopant layer 115 and / or the substrate dopant layer 105 can exhibit a comparatively high conductivity. Accordingly, if the dopant layer 115 and / or the substrate dopant layer 105 are removed inhomogeneously, the influence on the one-state resistance (forward voltage drop Vf) of the power semiconductor device 100 in the top-bottom direction is low. If these embodiments are implemented, a power semiconductor device 100 with an improved, and in particular homogeneous, forward voltage distribution can be provided.

[0068] BEOL processes can be divided into long thin-wafer processes and short thin-wafer processes. In long thin-wafer processes, high-temperature processes for the back side of the wafer, such as emitter annealing and field-stop annealing and / or Pt (platinum) diffusion to determine the charge carrier lifetime, are performed when the wafer is in a thin state, i.e., when the semiconductor wafer 101 has been at least partially removed. In short thin-wafer processes, the high-temperature processes, in particular all high-temperature processes, are performed in an unsilken state, i.e., before the semiconductor wafer 101 has been at least partially removed. Back-side doping can be performed by "cold" processes. For example, the field stop can be formed by proton irradiation and / or the back-side emitter can be formed by ion implantation and laser annealing.This ensures that the front of the wafer is not exposed to a critical temperature (for example, above 400 °C).

[0069] Since handling problems in processing the thinned state become yield-limiting with increasing wafer size, e.g., wafer diameter, even for short thinner-wafer processes, a stabilizing ring can be left on the peripheral part of the wafer, especially for wafers with a diameter greater than 200 mm. The formation of the stabilizing ring can be carried out as follows: The wafer can be thinned to a desired height of the stabilizing ring. Furthermore, material from the wafer can be removed to a certain thickness, e.g., 650 µm, by grinding, for example. Afterward, the remaining wafer material can be etched to remove crystal defects introduced by the grinding process.Unlike processes that remove material from the entire surface of the wafer, typically used for wafers up to 150 mm in diameter, thinning a large-diameter wafer is achieved through a non-uniform grinding process. For example, a cup-shaped depression can be created in the wafer, leaving a stabilizing ring (a so-called TAIKO ring) to stabilize it during handling. However, the resulting topology can increase or affect the flow rate of an etchant during etching, depending on the angle of the topology. Etching can be performed as a spin-etching process, for which the wafer can be rotated. The topology or geometry of the stabilizing ring can impair laminar flow of the etchant, causing the amount of etched material to increase or decrease near the stabilizing ring.Consequently, the wafers can systematically exhibit a greater or smaller wafer thickness near the stabilizing ring compared to the center of the wafer.

[0070] The resulting thickness variation can range from 5 to 10 µm. This thickness variation can influence the electrical properties of, for example, a 600 V diode. The diode may be specified for a thickness of 65 µm. The specific resistance of the wafer's base material can be 30 Ωcm. If an avalanche voltage V R When a voltage of approximately 770 V is reached, an electric field strength can be achieved at the nn +The transition voltage from the base zone to the field stop can be almost 100 kV / cm. Accordingly, an increase in wafer thickness of approximately 9 to 10 µm can account for the measured variation in a breakdown voltage of 90 V. This can be confirmed by measuring a thickness variation between the center of the wafer and a peripheral part of the wafer. A corresponding variation in the forward voltage drop Vf can be 300 mV. Compared to an intended forward voltage drop Vf, this can represent an increase of 20%. Together with YB losses (YB can be understood as a yield in an electrical power comparison during wafer testing) in continuous production, current processes limit the development of thin semiconductor devices, e.g., with a wafer device thickness of 40 µm or less.

[0071] Furthermore, the processes for forming structures on the back side of the wafer may be limited in terms of their heat budget. Accordingly, a backside emitter may only be formed with a shallow penetration depth. For example, boron implantation for a p-type emitter of an IGBT (at a dose of 1.3 × 10⁻⁶) 13 cm -2 at an energy of 45 keV and annealing at 880 °C for 30 minutes) or phosphorus implantation of a cathode emitter of a diode (at a dose of 1.1·10 15 cm -2 at an energy of 45 keV and simultaneous activation by Pt diffusion at 854 °C for 2 hours) to a penetration depth of less than 1 µm.

[0072] Compared to the lateral dimensions of the field stop and drift zone, the backside emitters formed by the process described above are infinitesimally thin. The thickness of these layers can be determined, for example, by spreading resistance profiling.

[0073] Since the variation in electrical parameters results mainly from the variation in base thickness, a back-side emitter with greater thickness and heavy doping can be formed to compensate for the variation in electrical parameters resulting from a variation in the thickness of a material with a comparatively low resistivity. According to embodiments described herein, the dopant layer 115 and / or the substrate doping layer 105 can provide a wide conductivity range. According to embodiments described herein, the dopant layer 115 and / or the substrate doping layer 105 can have a thickness of at least 10% of the base thickness, e.g., for a 600 V diode.According to the embodiments described herein, the doping layer 115 and / or the substrate doping layer 105 can have a thickness of 3 µm or greater, specifically 5 µm or greater, and particularly 6 µm or greater. Furthermore, the base thickness can be kept constant or unchanged. By using the epitaxy process described herein, additional degrees of freedom can be obtained for the formation of the doping gradient of the field stop and the base zone.

[0074] Without being bound by theory, a current-voltage characteristic of a pin diode with reduced emitter efficiency as well as an emitter-controlled diode can be approximated by: j=q⋅(μm+μpwB)2⋅(UF−Uj)H⋅[(UF−Uj)−UH]

[0075] where j is the current density, q is the elementary charge, and µ is the . n and µ p the mobility of electrons or holes, is U Fthe flux voltage, Uj the voltage drop in the boundary zones and U H the voltage drop in the central zone.

[0076] The voltage drop in the central zone can be mitigated by the long injection lifetime τ. HL be determined. U H can be determined by: UH=HB2(μm+μp)⋅τHL

[0077] This is w B the base width. This term can also be used to describe an IGBT current-voltage characteristic in a fully controlled state, since the IGBT forward characteristics are mainly determined by the emitter.

[0078] Good agreement with the measurement can be achieved, for example, for current densities of 30 A / cm². 2 This can be obtained, which may correspond to one tenth of the nominal current density of 600 V PC diodes.

[0079] Taking the above into account, a current-voltage characteristic curve for a diode with a device thickness of 65 µm can be calculated for different boundary conditions. The current density can be 260 A / cm². 2 The corresponding voltage drop at a rated current can be measured during a final test and expressed as V F These values ​​can be labelled. A typical value might be 1.55 V.

[0080] Without lifetime reduction, i.e. for a device without Pt diffusion, τ HL approximately 5 µs. This value takes into account recombination in the emitter zone. The mobility µ n and µ p can be about 1400 cm 2 The transmission characteristics can be calculated by adjusting the lifetime and the factor H so that they correspond to experimentally verified V. F-values ​​approximate. For this purpose, the experimentally obtained values ​​for Pt-diffuse devices with a thickness of 65 µm and 75 µm can be taken into account.

[0081] The following values ​​can be fitted: τ HL = 40 ns, a corresponding ambipolar diffusion length of approximately 11 µm and H = 5.5·10 -12 cm -4 / s The V F -value of a diode without Pt (τ HL = 5 µs) would be calculated to be 1.05 V, which could also be verified experimentally.

[0082] A current-voltage characteristic for an IGBT with a device thickness of 70 µm can also be calculated. Since the forward bias of an IGBT can usually be adjusted by its emitter efficiency, τ HL Assuming a VCESAT value of 5 µs, an experimentally observed VCESAT value of 1.6 V can be expected at a current density of 200 A / cm². 2 A value of H = 3.2·10 -11 cm -4 / s can be fitted.

[0083] Following Ohm's law, the power resistance of the emitter region can be calculated by: j=q⋅n⋅μ(ND)⋅E

[0084] Assuming that no significant recombination of minority charge carriers takes place in the emitter zone, n ≈ N D This assumption can be justified by a numerical simulation of the steady-state conduction of an EC diode, as outlined above. A hole current can be assumed to exist at a distance of 300 nm from the start of an n + The -zone can be completely reduced. This can correspond to almost the depth of a typical emitter zone. The hole density can start from a value similar to the electrode concentration and can be on the order of 5 × 10 16 cm -3 The electrode concentration can rise rapidly and reach a value determined by the doping of the detector.

[0085] The reduction of the minority current in the emitter, which exists over a distance much smaller than the ambipolar diffusion length (which determines a reduction in the basal zone), can be caused by an additional recombination mechanism in a region of high doping concentration. While a concentration of recombination centers (such as substitutional platinum) may be the dominant factor in the basal zone (compare Shockley-Read-Hall statistics), a mutual dependence with donors and acceptors (compare Scharfetter relationship) and Auger recombination can play a significant role.

[0086] Apart from a transition zone, whose tension contribution is already in V F The additional voltage drop Un in the path zone for a thick cathode emitter (>>300 nm) with a dimension d may be as follows: Un≈j⋅dq⋅ND⋅μ(ND) or for a p-type back-side emitter of an IGBT Up≈j⋅dq⋅NA⋅μ(NA).

[0087] Taking these relationships into account, the respective voltage drop in the emitter regions at a rated current could be calculated. Here, the dependence of the mobility on the doping can be considered. For a diode emitter with N D = 10 20 cm -3 can µ n = 78 cm 2 / Vs can be obtained. For a p-type emitter of an IGBT with N A = 6·10 17 cm -3 can µ p = 185 cm 2 / Vs will be obtained.

[0088] By increasing the device thickness starting from a target value of 65 µm for the diode and 70 µm for the IGBT, an increase in V can be achieved. Fand VCESAT can be calculated for variations in base thickness and emitter thickness. While an improvement in VF variation of three orders of magnitude can be obtained for the diode by shifting the thickness variation in the emitter region, an improvement of one order of magnitude can be expected for the IGBT.

[0089] Fig. Figure 9 illustrates a simulation graph of the oxygen concentration in the semiconductor wafer 101 after the growth of an epitaxial layer 110 on the semiconductor wafer 201. Fig. 9 represents the right axis the depth [µm] in the semiconductor wafer 201 from the first side 101a and the left axis represents the oxygen concentration [cm³]. -3 ]. Specifically illustrated Fig. 9 the remaining oxygen in the semiconductor wafer 201 after the growth of an epitaxial layer 110 on the semiconductor wafer 201. Assuming a constant volume oxygen concentration of 10 18 cm-3 (the asymptote for large depth values) is the amount of oxygen that has diffused into the epitaxial layer 110, the area between a straight line that has the volume value of 10 18 cm -3 represented, and the respective graph.

[0090] Fig. Figure 90 shows two graphs: one for a semiconductor wafer 201 with a substrate doping layer 105 with a high doping concentration (C(x)@D_HP; upper line), and one for a semiconductor wafer 201 with a substrate doping layer 105 with a low doping concentration (C(x)@D_LP; lower line). In the context of Fig. 9. “High dopant concentration” and “low dopant concentration” can mean a higher dopant concentration than the other or a lower dopant concentration than the other, respectively. In both cases, a temperature of 1100 °C for 50 minutes was assumed for the substrate to form the substrate dopant layer 105.

[0091] As from Fig. As can be seen in Figure 9, the remaining oxygen concentration in the semiconductor wafer 101 depends on the dopant concentration. Specifically, a higher dopant concentration will result in more oxygen remaining in the semiconductor wafer 101. Accordingly, less oxygen diffuses into the epitaxial layer 110, and therefore the epitaxial layer will have a lower oxygen concentration. Specifically, in the case of a low dopant concentration, an oxygen dose or amount of approximately 1.5 × 10⁻⁶ diffuses. 14 cm -2from the semiconductor wafer 101 into the epitaxial layer 110. In the case of a high dopant concentration (approximately 1·10 19 cm -3 ) oxygen diffusion was reduced, so that the oxygen dose or amount diffusing into the epitaxial layer 110 was reduced by about 20%.

[0092] Fig. Figure 10A illustrates a graph showing the dopant concentration of a substrate doping layer formed by a glass layer 102. The formation of the substrate doping layer 105 is carried out by exposing the semiconductor wafer 101 to an oxidation gas atmosphere containing a phosphine (PH3) precursor at an elevated temperature of 1110 °C for 240 minutes. Subsequently, the semiconductor wafer 101 was subjected to a heat treatment at a temperature of 1200 °C for 120 minutes to drive the dopants into the semiconductor wafer 101.

[0093] As from Fig. As can be seen in 10a, a substantially constant phosphorus concentration of 10 20 cm -3 a depth of approximately 15 µm can be obtained. At this depth, the phosphorus concentration rapidly drops to a lower value of less than 10. 15 cm -3 ab. Accordingly, the substrate doping layer in this example can be considered to have a thickness of 15 µm.

[0094] Fig. Figure 10B illustrates graphs showing the dopant concentration of a substrate doping layer formed by implantation. For the three graphs in Fig. Figure 10B shows the formation of the substrate doping layer 105 by implanting phosphorus at different doses. For the top graph, a dose of 5 × 10⁻⁵ was used. 15 cm -2 applied. A dose of 10 was applied to the middle graph. 15 cm -2applied. A dose of 10 was applied to the lowest graph. 14 cm -2 applied. Subsequently, the semiconductor wafer 101 was subjected to a heat treatment at a temperature of 1150 °C for 1100 minutes to drive the dopants into the semiconductor wafer 101.

[0095] Fig. Figure 11 illustrates graphs showing experimentally verified concentration profiles for the implanted phosphorus concentration (31P C[atoms / cm³]). 3 ]; the graph with the peak at 10 to 11 µm depth) or the oxygen concentration (16O C[atoms / cm³) 3 ]; the graph, which slopes from right to left) show. The implanted phosphorus dose was approximately 5 × 10 15 cm -2A heat treatment at 1150 °C for 400 minutes was applied. Subsequently, an epitaxial layer 110 with a thickness of approximately 100 µm was grown on the semiconductor wafer 101. The interface between the second side 110b of the epitaxial layer 110 and the first side 101a of the semiconductor wafer 101 is represented by the vertical dashed line at a depth of 10 µm. The epitaxial layer 110 lies to the left of the vertical dashed line, and the semiconductor wafer 101 lies to the right of the dashed line.

[0096] As from Fig. As can be seen, the oxygen concentration falls exponentially from the volume value within the semiconductor wafer 101 to the first side 101a of the semiconductor wafer 101 and from the second side 110b of the epitaxial layer 110 to a value below 10 17 cm -3The implanted phosphorus concentration reaches its peak value within semiconductor wafer 101. As compared to Fig. As can be seen in Figure 10B, the implanted phosphorus concentration reaches its maximum value at the first side 101a of the semiconductor wafer 101. Accordingly, the phosphorus dose diffuses out of the semiconductor wafer 101 into the epitaxial layer 110 on the left side of the vertical dashed line (see also Figure 10B). Fig. 9) If embodiments are implemented, the amount of oxygen diffusion into the epitaxial layer can be reduced and / or a doping layer can be formed in the epitaxial layer 110.

[0097] Fig. Figure 12 illustrates graphs showing a change in the forward voltage drop (ΔV). F [V]) as a function of a thickness variation [µm] in the process of at least partial removal of the semiconductor wafer 101. Fig. Figure 12 shows two graphs: one for heat treatment at 1150 °C for 400 minutes (the graph with the higher value at 10 µm), and one for heat treatment at 1150 °C for 1100 minutes (the graph with the lower value at 10 µm). For both graphs, phosphorus was added at a dose of 5 × 10 15 cm -2 implanted.

[0098] As from Fig.As can be seen in Figure 12, the dependence of the change in the forward voltage drop can be reduced by two orders of magnitude by forming different substrate doping layers 105. The dependence of the change in the forward voltage drop on the thickness variation of the remaining part of the semiconductor wafer 101 can be reduced even further compared to a semiconductor wafer without a substrate doping layer. If embodiments are implemented, a power semiconductor device 100 can be provided that exhibits improved forward voltage drop homogeneity.

[0099] As used here, the terms "possessing," "containing," "encompassing," "comprehensive," and the like are open terms that indicate the presence of specified elements or features but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and the singular unless the context clearly indicates otherwise.

Claims

[1] Method for forming a power semiconductor device, the method comprising: Providing a semiconductor wafer (101) with a phosphorus doping concentration of less than 10 15 / cm 3 , which has grown through a Czochralski process and has a first page (101a); Forming an n-type substrate doping layer (105) with phosphorus as the dopant in the semiconductor wafer (101) at the first side (101a), wherein the substrate doping layer (105) has a doping concentration of at least 10 17 / cm 3 , typically of at least 10 18 / cm 3 exhibits; Forming an epitaxial layer (110) on the first side (101a) of the semiconductor wafer (101) after forming the substrate doping layer (105) Images of a dopant layer (115) in the epitaxial layer (110) during growth of the epitaxial layer (110) by diffusion of dopants from the substrate dopant layer (105) into the epitaxial layer (110); and Forming a power semiconductor device (100) with the doping layer (115) as a functional layer of the power semiconductor device (100). [2] The method of claim 1, further comprising: Formation of a pn junction in the epitaxial layer (110). [3] The method of claim 1 or 2, further comprising: Formation of an initial metallization on the epitaxial layer (110); and Forming a second metallization on a second side of the semiconductor wafer, opposite the first side (101a). [4] Method according to any of the preceding claims, wherein forming the substrate doping layer (105) comprises: Forming a glass layer (102) on the first side (101a) of the semiconductor wafer (101), wherein the glass layer comprises dopants; and Subjecting the semiconductor wafer (101) to a heat treatment to drive the dopants into the semiconductor wafer (101) to form the substrate doping layer (105). [5] Method according to claim 4, wherein forming the glass layer on the first side (101a) comprises: Exposure of the semiconductor wafer (101) to an oxidation gas atmosphere containing a gaseous doping precursor at an elevated temperature. [6] Method according to claim 4 or 5, wherein the glass layer is formed at a temperature of 750 °C or greater, specifically 900 °C or greater, in particular 1000 °C or greater, and / or 1400 °C or less, specifically 1300 °C or less, in particular 1200 °C or less. [7] Method according to any one of claims 4 to 6, wherein the glass layer is removed before the semiconductor wafer (101) is subjected to heat treatment. [8] Method according to any one of claims 4 to 7, wherein the heat treatment for driving the dopants into the semiconductor wafer is carried out at a temperature of 800 °C or greater, specifically 1000 °C or greater, in particular 1100 °C or greater, and / or 1600 °C or less, specifically 1400 °C or less, in particular 1300 °C or less. [9] Method according to any one of claims 1 to 3, wherein forming the substrate doping layer (105) comprises: Implanting dopants into the first side (101a) of the semiconductor wafer (101); and Subjecting the semiconductor wafer (101) to a heat treatment to drive the dopants into the semiconductor wafer (101) to form the substrate doping layer (105). [10] Method according to claim 9, wherein the dopants are present in a dose of at least 10 14 / cm 2 , typically of at least 5·10 14 / cm 2 be implanted. [11] A method according to any of the preceding claims, further comprising: at least partial removal of the semiconductor wafer (101) after formation of the epitaxial layer (110), in particular after formation of the pn junction. [12] Method according to claim 11, wherein the semiconductor wafer (101) is removed to such an extent that the substrate doping layer (105) is exposed. [13] The method of claim 12, further comprising: Formation of a metal layer on the exposed substrate doping layer (105). [14] Method according to any of the preceding claims, wherein the doping layer (115) has a thickness of 0.5 µm or greater, specifically 0.7 µm or greater, and in particular 1.0 µm or greater. [15] Method according to any of the preceding claims, wherein the doping layer (115) has a higher doping concentration than an adjacent part of the epitaxial layer (110). [16] Method according to any of the preceding claims, wherein the doping layer (115) provides a high conductivity range during at least partial removal of the semiconductor wafer (101). [17] A method according to any of the preceding claims, further comprising: Etching of a trench (130) with a side wall (130b) and a bottom (130a) in the epitaxial layer (110); Forming an auxiliary layer (132) on the side wall (130a) and the underside (130a) of the trench (130); and Deposition of a conductive material (140) on the auxiliary layer (132) to at least partially fill the trench (130).

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