Low concentration phosphorus doped structure, preparation method thereof and solar cell

Abstract

This invention belongs to the field of semiconductor technology, and particularly relates to a low-concentration phosphorus-doped structure, its fabrication method, and solar cells. Compared with existing technologies, this invention introduces a low-concentration phosphorus diffusion region on the front side of the silicon substrate, which has a gettering effect on metal impurities and helps to improve bulk lifetime. Secondly, the introduction of a phosphorus front field on the front surface allows some electrons to be transferred to the N-type doped region through the front field, thereby helping to maintain the battery's flyback factor (FF) without decreasing while increasing the area ratio of the P-type doped region on the back side and the short-circuit current. Furthermore, the structure with a front-side phosphorus-doped diffusion region can reduce the degree of lifetime decay and efficiency reduction of the battery under ultraviolet irradiation, and the phosphorus-doped diffusion region can introduce impurities such as carbon and phosphorus into the silicon substrate, thereby improving the mechanical properties of the silicon substrate.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and particularly relates to a low-concentration phosphorus-doped structure, its preparation method, and solar cells. Background Technology

[0002] Surface passivation is a key element in improving the performance of silicon-based semiconductor devices. Furthermore, to reduce light loss from the grid lines on the front side of the cell, cell structures are shifting towards either full back contact or back junction structures. For back junction PN junction cells, common types include N-type BC (full back contact) cells or N-type BJ (back junction) cells, both using N-type silicon wafers as the electron carrier. Therefore, their front surface can have two options: completely undoped or using a phosphorus-doped front-field structure. Regardless of the front-field structure, the cell's front surface structure needs to simultaneously meet multiple requirements, including surface passivation and battery electrical performance.

[0003] Currently, N-type BC cells are commonly used high-efficiency solar cells in industry. The passivation structure applied to the front surface of BC cells is typically AlO₂. x / SiN x AlO x / SiN x The passivation performance of the stacked passivation film on a diffusionless N-type silicon wafer is approximately 1~3 fA / cm. 2 Faced with the industry's demands for improved efficiency and structural evolution in solar cells, existing front-side structures can no longer simultaneously achieve passivation, electrical performance, and UV resistance. The specific reasons are as follows (taking N-type silicon substrates as an example): 1) Increasing the proportion of PN junctions on the back side leads to higher photocurrent (Jsc). A small P-region results in ineffective minority carrier collection, leading to current loss. However, an excessively large P-region causes excessively long majority carrier transport distances and excessive series resistance losses, resulting in a decrease in the fill factor (FF); 2) Existing BC cells have no doping on the front side, leading to significant performance degradation under UV irradiation, resulting in a substantial decrease in module power and impacting product competitiveness; 3) Research indicates that introducing phosphorus doping to the front surface of N-type BC cells can reduce UV irradiation degradation to some extent. However, existing low-pressure phosphorus diffusion technology based on POCl3 sources can only introduce phosphorus doping at concentrations greater than 1E+20 cm⁻¹ on the surface. -3 Phosphorus diffusion junctions, under such high phosphorus concentration conditions, AlO x / SiN x The passivation quality of phosphorus diffusion junctions is very poor due to the fixed negative charge. J 0 is usually greater than 60 fA / cm 2 If the passivation quality of SiOx / SiNx for phosphorus diffusion junctions is also poor, J 0 is generally higher than 30 fA / cm 2Furthermore, it cannot be applied to high-efficiency BC batteries. Therefore, the front side of existing N-type BC batteries cannot employ a phosphorus diffusion structure.

[0004] N-type BJ batteries have relatively few industrial applications, but they face the same problems as the aforementioned n-type BC batteries.

[0005] In summary, existing N-type BC and N-type BJ batteries lack a diffusion region on the front side, which limits the adoption of front-field phosphorus diffusion structures, poor UV resistance, and the inability to balance current and fill factor, thus restricting further improvements in battery performance. Summary of the Invention

[0006] In view of this, the technical problem to be solved by the present invention is to provide a low-concentration phosphorus doped structure, its preparation method and a solar cell, which has the advantages of high front surface passivation quality, high cell efficiency, strong resistance to ultraviolet radiation and help to improve FF.

[0007] This invention provides a low-concentration phosphorus-doped structure, comprising a silicon substrate; the silicon substrate includes a front surface and a back surface opposite to each other; all or part of the front surface of the silicon substrate has a phosphorus-doped diffusion region; the phosphorus-doped diffusion region includes activated phosphorus atoms and unactivated phosphorus atoms; the concentration of activated phosphorus atoms in the phosphorus-doped diffusion region does not exceed 1 × 10⁻⁶. 19 cm -3 The depth of the phosphorus-doped diffusion region does not exceed 2 μm.

[0008] Preferably, the concentration of activated phosphorus atoms in the phosphorus-doped diffusion region does not exceed 4 × 10⁻⁶. 18 cm -3 The depth of the phosphorus-doped diffusion region is 0.01~1 μm.

[0009] Preferably, the silicon substrate is an N-type silicon substrate or a P-type silicon substrate; The phosphorus-doped diffusion region also includes oxygen and / or hydrogen elements; And / or, the phosphorus-doped diffusion region further includes carbon and / or nitrogen elements.

[0010] Preferably, a PN junction is provided on the back surface of the silicon substrate.

[0011] Preferably, the back surface of the silicon substrate is provided with alternating P-type doped regions and N-type doped regions; The front surface has a phosphorus-doped diffusion region in all or part; if it has a phosphorus-doped diffusion region in part, the phosphorus-doped diffusion region includes a P-type doped region in the vertical projection plane of the back surface.

[0012] Preferably, an intrinsic region is provided between the P-type doped region and the N-type doped region; The front surface portion has a phosphorus-doped diffusion region; the vertical projection of the phosphorus-doped diffusion region onto the back surface overlaps with the P-type doped region and the intrinsic region.

[0013] Preferably, the back surface of the silicon substrate is provided with an element-doped region, the polarity of the element-doped region being opposite to that of the silicon substrate, and the back surface does not contain a doped region with the same polarity as the silicon substrate.

[0014] Preferably, a tunneling oxide layer is further disposed between the P-type doped region and the silicon substrate; A tunneling oxide layer is also disposed between the N-type doped region and the silicon substrate; A tunneling oxide layer is also provided between the element-doped region and the silicon substrate; And / or, a passivation layer is provided on the positive surface of the silicon substrate.

[0015] The present invention also provides a method for preparing the above-mentioned low-concentration phosphorus-doped structure, comprising the following steps: S1) provides a silicon substrate; S2) A phosphorus-doped diffusion source layer is prepared on the positive surface of the silicon substrate; the phosphorus-doped diffusion source layer comprises a nano-silicon oxide layer and a phosphorus-containing functional layer in a direction away from the silicon substrate; the phosphorus-containing functional layer is selected from a phosphorus-containing silicon oxide layer and / or a phosphorus-containing amorphous silicon layer. S3) The silicon substrate on which the phosphorus-doped diffusion source layer is prepared is subjected to high-temperature annealing, and then the phosphorus-doped diffusion source layer is removed to obtain a low-concentration phosphorus-doped structure.

[0016] Preferably, the thickness of the nano-silicon oxide layer is 1~10 nm; The thickness of the phosphorus-containing functional layer is 10~50 nm; And / or, the phosphorus-containing functional layer further includes carbon and / or nitrogen elements; And / or, an intermediate layer is further provided between the nano-silicon oxide layer and the phosphorus-containing functional layer; the intermediate layer is selected from one or more of the intrinsic silicon oxide layer, carbon-containing silicon oxide layer, nitrogen-containing silicon oxide layer, amorphous silicon layer, carbon-containing amorphous silicon layer and nitrogen-containing amorphous silicon layer; the thickness of the intermediate layer is 5~50 nm; And / or, the surface of the phosphorus-containing functional layer away from the silicon substrate is further provided with an outer surface layer; the outer surface layer is selected from one or more of intrinsic silicon oxide layer, carbon-containing silicon oxide layer, nitrogen-containing silicon oxide layer, amorphous silicon layer, carbon-containing amorphous silicon layer and nitrogen-containing amorphous silicon layer; the thickness of the outer surface layer is 5~50 nm; And / or, the high-temperature annealing temperature in step S3) is greater than or equal to 700°C.

[0017] The present invention also provides a solar cell comprising the aforementioned low-concentration phosphorus doping structure.

[0018] Compared with the prior art, the preparation method provided by the present invention has the following advantages: This invention introduces a low-concentration phosphorus diffusion region on the front side of the silicon substrate, which has a gettering effect on metal impurities and helps to improve the bulk lifetime. Secondly, the introduction of a phosphorus front field on the front surface allows some electrons to be transferred to the N-type doped region through the front field, thereby helping to maintain the battery's fairing without decreasing even when the area ratio of the P-type doped region on the back side and the short-circuit current are increased. Furthermore, the structure with a phosphorus-doped diffusion region on the front side can reduce the degree of battery lifetime decay and efficiency reduction under ultraviolet irradiation, and the phosphorus-doped diffusion region can introduce impurities such as carbon and phosphorus into the silicon substrate, thereby improving the mechanical properties of the silicon substrate. Attached Figure Description

[0019] Figure 1 A schematic diagram of a specific low-concentration phosphorus-doped structure provided by the present invention; Figure 2 A schematic diagram of a specific process for preparing a low-concentration phosphorus-doped structure is provided by the present invention; Figure 3 This is a schematic diagram of the structure of the product prepared in Comparative Example 1 of the present invention; Figure 4 This is a schematic diagram of the structure of the product prepared in Comparative Example 2 of the present invention; Figure 5 This is a schematic diagram of the structure of the product prepared in Comparative Example 3 of the present invention; Figure 6 This is a schematic diagram of the structure of the product prepared in Comparative Example 4 of the present invention; Figure 7 This is a schematic diagram of the structure of the product prepared in Comparative Example 5 of the present invention; Figure 8 This is a schematic diagram of the structure of the product prepared in Comparative Example 6 of the present invention; Figure 9 This is a schematic diagram of the structure of the product prepared in Comparative Example 7 of the present invention; Figure 10 This is a schematic diagram of the structure of the product prepared in Example 1 of the present invention; Figure 11 This is a schematic diagram of the structure of the product prepared in Example 5 of the present invention; Figure 12 This is a schematic diagram of the structure of the product prepared in Example 6 of the present invention; Figure 13 This is a schematic diagram of the structure of the product prepared in Example 7 of the present invention; Figure 14 This is a schematic diagram of the structure of the product prepared in Example 8 of the present invention; Figure 15This is a schematic diagram of the structure of the product prepared in Example 9 of the present invention; Figure 16 This is an ECV curve of the product prepared in Comparative Example 5 of the present invention; Figure 17 The ECV curves of the products obtained in Examples 1 to 4 of this invention are shown. Figure 18 This is a high-resolution TEM image of the AlOx product prepared in Comparative Example 6 of this invention. Figure 19 This is a high-resolution TEM image of the AlOx product prepared in Example 7 of this invention; Figure 20 This is an EDS-HAADF atomic-level elemental distribution diagram under TEM of the AlOx product prepared in Comparative Example 6 of this invention; Figure 21 This is an EDS-HAADF atomic-level elemental distribution diagram under TEM of the AlOx product prepared in Example 7 of this invention; Figure 22 TEM of the AlOx product prepared in Comparative Example 6 of this invention (…). Figure 18 Local analysis, IFFT, FFT, and related gravity analysis data plots; Figure 23 TEM of the AlOx product prepared in Example 7 of this invention ( Figure 19 Local analysis, IFFT, FFT, and related gravity analysis data plots; Figure 24 To illustrate the present invention, SIMS testing was performed on the samples obtained from Comparative Example 6 and Example 7 to obtain a comparison diagram of the P element distribution in the silicon substrate. Detailed Implementation

[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0021] This invention provides a low-concentration phosphorus-doped structure, comprising a silicon substrate; the silicon substrate includes a front surface and a back surface opposite to each other; all or part of the front surface of the silicon substrate has a phosphorus-doped diffusion region; the phosphorus-doped diffusion region includes activated phosphorus atoms and unactivated phosphorus atoms; the concentration of activated phosphorus atoms in the phosphorus-doped diffusion region does not exceed 1 × 10⁻⁶. 19 cm -3 The depth of the phosphorus-doped diffusion region does not exceed 2 μm.

[0022] In one specific embodiment of the present invention, the silicon substrate may be an N-type silicon substrate or a P-type silicon substrate.

[0023] In one specific embodiment of the present invention, a PN junction is preferably provided on the back side of the silicon substrate.

[0024] In one specific embodiment of the present invention, at least one surface of the silicon substrate has a textured structure; specifically, the textured structure has a reflectivity of 11% to 13% in the visible light band.

[0025] In this invention, all or part of the positive surface of the silicon substrate has a phosphorus-doped diffusion region; when the entire positive surface has a phosphorus-doped diffusion region, the phosphorus-doped diffusion region is an integral layer structure; when part of the positive surface has a phosphorus-doped diffusion region, the phosphorus-doped diffusion region only covers part of the surface and is not an integral layer structure.

[0026] In one specific embodiment of the present invention, the concentration of activated phosphorus atoms in the phosphorus-doped diffusion region does not exceed 1 × 10⁻⁶. 19 cm -3 That is, the highest concentration of activated phosphorus atoms in the phosphorus-doped diffusion region does not exceed 1×10 19 cm -3 Further preferably, the highest concentration of activated phosphorus atoms in the phosphorus-doped diffusion region does not exceed 4 × 10⁻⁶. 18 cm -3 More preferably, the highest concentration of activated phosphorus atoms in the phosphorus-doped diffusion region is 1 × 10⁻⁶. 17 ~4×10 18 cm -3 More preferably, the highest concentration of activated phosphorus atoms in the phosphorus-doped diffusion region is 2 × 10⁻⁶. 17 ~4×10 18 cm -3 More preferably, the highest concentration of activated phosphorus atoms in the phosphorus-doped diffusion region is 5 × 10⁻⁶. 17 ~4×10 18 cm -3 More preferably, the highest concentration of activated phosphorus atoms in the phosphorus-doped diffusion region is 6 × 10⁻⁶. 17 ~4×10 18 cm -3 More preferably, the highest concentration of activated phosphorus atoms in the phosphorus-doped diffusion region is 7 × 10⁻⁶. 17 ~4×10 18 cm -3 More preferably, the highest concentration of activated phosphorus atoms in the phosphorus-doped diffusion region is 8 × 10⁻⁶.17 ~4×10 18 cm -3 More preferably, the highest concentration of activated phosphorus atoms in the phosphorus-doped diffusion region is 8 × 10⁻⁶. 17 ~3×10 18 cm -3 .

[0027] In one specific embodiment of the present invention, the concentration of activated phosphorus atoms in the phosphorus-doped diffusion region preferably does not exceed 1 × 10⁻⁶. 18 cm -3 .

[0028] In one specific embodiment of the present invention, the depth of the phosphorus-doped diffusion region does not exceed 1 μm; more preferably, the depth of the phosphorus-doped diffusion region is 0.01~1 μm; even more preferably, the depth of the phosphorus-doped diffusion region is 0.01~0.5 μm; even more preferably, the depth of the phosphorus-doped diffusion region is 0.01~0.2 μm; even more preferably, the depth of the phosphorus-doped diffusion region is 0.01~0.1 μm; optionally, the depth of the phosphorus-doped diffusion region is 0.01 μm, 0.02 μm, 0.03 μm, 0.04 μm, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm or a range between any two of the above values.

[0029] In one specific embodiment of the present invention, the concentration of phosphorus in the phosphorus doped diffusion region decreases sequentially from the surface to the interior of the silicon substrate.

[0030] In one specific embodiment of the present invention, the phosphorus-doped diffusion region further includes oxygen and / or hydrogen elements.

[0031] In one specific embodiment of the present invention, the concentration of oxygen and / or hydrogen in the phosphorus-doped diffusion region decreases sequentially from the surface to the interior of the silicon substrate.

[0032] In one specific embodiment of the present invention, the highest concentration of oxygen in the phosphorus-doped diffusion region is preferably higher than 1 × 10⁻⁶. 20 cm -3 More preferably, higher than 1×10 21 cm -3 The highest concentration of hydrogen in the phosphorus-doped diffusion region is preferably higher than 1×10⁻⁶. 20 cm -3 More preferably, higher than 1×10 21 cm -3 More preferably, higher than 1×10 22 cm-33 The concentration of hydrogen in the phosphorus-doped diffusion region is preferably no higher than 5 × 10⁻⁶. 22 cm -3 .

[0033] In one specific embodiment of the present invention, the phosphorus doped diffusion region further includes carbon and / or nitrogen elements; by introducing impurities such as carbon and nitrogen, surface passivation can be further improved and bulk lifetime increased.

[0034] In one specific embodiment of the present invention, the concentration of carbon and / or nitrogen elements in the phosphorus doped diffusion region decreases sequentially from the surface to the interior of the silicon substrate.

[0035] In a specific embodiment of the present invention, the back surface of the silicon substrate is provided with alternating P-type doped regions and N-type doped regions; at this time, the low-concentration phosphorus doped structure is a BC cell structure; a portion of the front surface has a phosphorus doped diffusion region; the vertical projection plane of the phosphorus doped diffusion region on the back surface preferably includes a P-type doped region; more specifically, the vertical projection plane of the phosphorus doped diffusion region on the back surface does not overlap with the N-type doped region. Setting the phosphorus doped diffusion region so that its vertical projection plane on the back surface does not overlap with the N-type doped region can further improve the efficiency of the solar cell; using a local phosphorus diffusion region enhances the lateral transport of photogenerated carriers on the front side to the area directly above the corresponding N(P) region on the back side through this layer, reducing excessive series resistance loss caused by excessive electron transmission distance. More preferably, a tunneling oxide layer is further disposed between the P-type doped region and the silicon substrate; a tunneling oxide layer is also disposed between the N-type doped region and the silicon substrate; the thickness of the tunneling oxide layer is preferably 1~5 nm; optionally, the thickness of the tunneling oxide layer is 1 nm, 2 nm, 3 nm, 4 nm, 5 nm or any two of the above values. By providing a tunneling oxide layer, surface dangling bonds can be eliminated, providing good chemical passivation.

[0036] In a specific embodiment of the present invention, a back passivation layer is provided on the surface of the P-type doped region and the N-type doped region away from the silicon substrate; the back passivation layer can be any passivation layer known to those skilled in the art, and there are no special limitations, including but not limited to hydrogen-containing dielectric films with fixed negative charge, fixed positive charge, or no charge; the hydrogen-containing dielectric film includes but is not limited to silicon oxide, aluminum oxide, silicon nitride, nitrogen / carbon polycrystalline silicon, and combinations thereof; specifically, the hydrogen-containing dielectric film with fixed negative charge includes stacked AlOx (a 1-3 nm nano-SiOx layer is commonly found between AlOx and silicon) and SiNx; the hydrogen-containing dielectric film with fixed positive charge includes SiNx or stacked SiOx and SiNx; the hydrogen-containing dielectric film without charge includes stacked nano-SiOx, nitrogen (or carbon) polycrystalline silicon, AlOx (AlOx can be omitted) and SiNx.

[0037] In one specific embodiment of the present invention, the back passivation layer comprises a silicon oxide layer and a hydrogen-containing dielectric film stacked sequentially; the hydrogen-containing dielectric film is preferably AlOx and / or SiNx; the thickness of the silicon oxide layer is preferably 1~3 nm.

[0038] In a specific embodiment of the present invention, an intrinsic region is provided between the P-type doped region and the N-type doped region; when a portion of the positive surface has a phosphorus doped diffusion region, the vertical projection of the phosphorus doped diffusion region on the back surface overlaps with the P-type doped region and the intrinsic region.

[0039] In one specific embodiment of the present invention, a back passivation layer is provided on the surface of the intrinsic region away from the silicon substrate; the back passivation layer is the same as described above, and will not be repeated here.

[0040] In a specific embodiment of the present invention, a passivation layer is disposed on the positive surface of the silicon substrate; the passivation layer can be any passivation layer known to those skilled in the art, and there are no special limitations, including but not limited to hydrogen-containing dielectric films with fixed negative charge, fixed positive charge, or no charge; the hydrogen-containing dielectric film includes but is not limited to silicon oxide, aluminum oxide, silicon nitride, nitrogen / carbon polycrystalline silicon, and combinations thereof; specifically, the hydrogen-containing dielectric film with fixed negative charge includes stacked AlOx (a 1-3 nm nano-SiOx layer is commonly found between AlOx and silicon) and SiNx; the hydrogen-containing dielectric film with fixed positive charge includes SiNx or stacked SiOx and SiNx; the hydrogen-containing dielectric film without charge includes stacked nano-SiOx, nitrogen (or carbon) polycrystalline silicon, AlOx (AlOx can be omitted) and SiNx.

[0041] In one specific embodiment of the present invention, the passivation layer on the positive surface comprises a silicon oxide layer and a hydrogen-containing dielectric film stacked sequentially; the hydrogen-containing dielectric film is preferably AlOx and / or SiNx; the thickness of the silicon oxide layer is preferably 1~3 nm.

[0042] In one specific embodiment provided by the present invention, the low-concentration phosphorus-doped structure has Figure 1 The structure shown.

[0043] In another specific embodiment provided by the present invention, the back surface of the silicon substrate is provided with an element-doped region, the polarity of which is opposite to that of the silicon substrate, and the back surface does not contain a doped region with the same polarity as the silicon substrate. That is, when the silicon substrate is an N-type silicon substrate, the element-doped region is a P-type doped region, and when the silicon substrate is a P-type silicon substrate, the element-doped region is an N-type doped region. In this case, the low-concentration phosphorus doped structure is a BJ battery structure. Under this structure, even if only a portion of the front surface of the silicon substrate has a phosphorus doped diffusion region, its position is not restricted.

[0044] In a specific embodiment of the present invention, a tunneling oxide layer is preferably further disposed between the element-doped region and the silicon substrate; the thickness of the tunneling oxide layer is preferably 1~5 nm; optionally, the thickness of the tunneling oxide layer is 1 nm, 2 nm, 3 nm, 4 nm, 5 nm or any two of the above values.

[0045] In a specific embodiment of the present invention, the back side of the element-doped region away from the silicon substrate and the surface of the back surface of the silicon substrate where the element-doped region is not disposed are preferably further provided with a back passivation layer; the back passivation layer is the same as described above, and will not be repeated here.

[0046] In a specific embodiment of the present invention, a tunneling oxide layer is preferably provided between the back surface of the silicon substrate without element-doped regions and the back passivation layer; the tunneling oxide layer is the same as described above and will not be repeated here.

[0047] The low-concentration phosphorus-doped structure provided by this invention can effectively transport charge carriers while also achieving passivation, which helps to achieve a higher fill factor FF, less charge carrier loss, and promotes the improvement of battery efficiency.

[0048] The present invention also provides a method for preparing the above-mentioned low-concentration phosphorus-doped structure, comprising the following steps: S1) providing a silicon substrate; S2) preparing a phosphorus-doped diffusion source layer on the positive surface of the silicon substrate; the phosphorus-doped diffusion source layer comprises a nano-silicon oxide layer and a phosphorus-containing functional layer in a direction away from the silicon substrate; the phosphorus-containing functional layer is selected from a phosphorus-containing silicon oxide layer and / or a phosphorus-containing amorphous silicon layer; S3) subjecting the silicon substrate on which the phosphorus-doped diffusion source layer is prepared to high-temperature annealing, and then removing the phosphorus-doped diffusion source layer to obtain a low-concentration phosphorus-doped structure.

[0049] In this invention, there are no special restrictions on the source of any raw materials; commercially available materials are acceptable. The silicon substrate is the same as described above and will not be repeated here.

[0050] In one specific embodiment of the present invention, the thickness of the nano-silicon oxide layer is preferably 1-10 nm; optionally, the thickness of the nano-silicon oxide layer is 1 nm, 1.5 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. nm or any two of the above values; the nano-silicon oxide layer can be prepared according to methods well known to those skilled in the art, without any special limitations, including but not limited to oxidation or chemical vapor deposition (CVD); the oxidation method includes but is not limited to thermal oxidation, wet oxidation, or ozone oxidation; the chemical vapor deposition includes but is not limited to plasma-enhanced chemical vapor deposition (PECVD), microwave plasma chemical vapor deposition (MWCVD), hot filament chemical vapor deposition (HWCVD), etc.; specifically, in this invention, thermal oxidation is preferably used to prepare the nano-silicon oxide layer; the thermal oxidation method preferably specifically involves annealing in an oxygen-containing atmosphere; the volume concentration of oxygen in the atmosphere is preferably 80%~100%; the annealing temperature is preferably 200℃~600℃; optionally, the annealing temperature is 200℃, 300℃, 400℃, 500℃, 600℃ or any two of the above values; the annealing time is preferably 5~15 min; optionally, the annealing time is 5 min, 8 min, 10 min, 12 min, 15 min, etc. min or the range between any two of the above values.

[0051] In a specific embodiment of the present invention, the thickness of the phosphorus-containing functional layer is preferably 10-50 nm; optionally, the thickness of the phosphorus-containing functional layer is 10 nm, 12 nm, 20 nm, 30 nm, 40 nm, 50 nm, or any two of the above values; specifically, the phosphorus-containing functional layer is preferably a phosphorus-containing silicon oxide layer; the proportion of each element in the phosphorus-containing functional layer can be adjusted, specifically, the phosphorus concentration in the phosphorus-containing functional layer is preferably higher than 1×10⁻⁶.20 cm -3 More preferably, higher than 1×10 21 cm -3 More preferably, higher than 1×10 22 cm -3 The phosphorus concentration in the phosphorus-containing functional layer is preferably no higher than 5 × 10⁻⁶. 22 cm -3 .

[0052] In one specific embodiment of the present invention, the phosphorus-containing functional layer preferably further includes hydrogen; the concentration of hydrogen in the phosphorus-containing functional layer is preferably greater than or equal to 1 × 10⁻⁶. 20 cm -3 .

[0053] In this invention, the phosphorus-containing functional layer is preferably prepared by chemical vapor deposition (CVD); the chemical vapor deposition (CVD) includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD), microwave plasma chemical vapor deposition (MWCVD), and hot-wire chemical vapor deposition (HWCVD); specifically, in this invention, PECVD is preferably used to prepare the phosphorus-containing functional layer; the phosphorus source used in preparing the phosphorus-containing functional layer by chemical vapor deposition is preferably PH3; the silicon source used is preferably SiH4; the oxygen source used is preferably N2O; further specifically, hydrogen gas is preferably introduced when preparing the phosphorus-containing functional layer by chemical vapor deposition; the deposition temperature of the chemical deposition is preferably 100℃~600℃; optionally, the deposition temperature of the chemical deposition is 100℃, 200℃, 300℃, 400℃, 500℃, 600℃ or any two of the above values.

[0054] In a specific embodiment of the present invention, an intermediate layer is further provided between the nano-silicon oxide layer and the phosphorus-containing functional layer; the intermediate layer is preferably one or more of the following: intrinsic silicon oxide layer, carbon-containing silicon oxide layer, nitrogen-containing silicon oxide layer, amorphous silicon layer, carbon-containing amorphous silicon layer, and nitrogen-containing amorphous silicon layer; the thickness of the intermediate layer is preferably 5~50 nm; optionally, the thickness of the intermediate layer is 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, or any two of the above values; the intermediate layer is preferably prepared by chemical vapor deposition (CVD); the chemical vapor deposition (CVD) includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD), microwave plasma chemical vapor deposition (MWCVD), and hot-wire chemical vapor deposition (HWCVD).

[0055] In a specific embodiment of the present invention, an outer surface layer is further disposed on the surface of the phosphorus-containing functional layer away from the silicon substrate; the outer surface layer is preferably one or more of an intrinsic silicon oxide layer, a carbon-containing silicon oxide layer, a nitrogen-containing silicon oxide layer, an amorphous silicon layer, a carbon-containing amorphous silicon layer, and a nitrogen-containing amorphous silicon layer; the thickness of the outer surface layer is preferably 5-50 nm; optionally, the thickness of the outer surface layer is 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, or any two of the above values; the outer surface layer is preferably prepared by chemical vapor deposition (CVD); the chemical vapor deposition (CVD) includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD), microwave plasma chemical vapor deposition (MWCVD), and hot-wire chemical vapor deposition (HWCVD). Each layer of the phosphorus-doped diffusion source layer has good fabrication controllability and a wide process window, making it suitable for large-scale industrialization.

[0056] The silicon substrate for preparing the phosphorus-doped diffusion source layer is subjected to high-temperature annealing; the high-temperature annealing is preferably carried out in a tube annealing furnace; the high-temperature annealing temperature is preferably 600℃~1200℃; optionally, the high-temperature annealing temperature is 600℃, 700℃, 750℃, 800℃, 850℃, 900℃, 1000℃, 1100℃, 1200℃ or any two of the above values; the high-temperature annealing time is preferably 10~300 min; optionally, the high-temperature annealing time is 10 min, 20 min, 30 min, 40 min, 50 min, 60 min, 70 min, 80 min, 90 min, 100 min, 120 min, 150 min, 180 min, 200 min, 220 min, 250 min, 280 min, 300 min or any two of the above values. During the high-temperature annealing process, active atoms such as phosphorus in the phosphorus-doped diffusion source layer diffuse into the silicon substrate, forming a shallow diffusion layer on its surface. At the same time, atoms such as carbon, nitrogen, and oxygen also diffuse to the surface of the silicon substrate. By controlling the high-temperature annealing temperature, the diffusion depth of phosphorus can be controlled, thereby controlling the depth of the phosphorus-doped diffusion region. Furthermore, in this invention, the high-temperature annealing temperature is much lower than the annealing temperature of the back n-poly layer, so the preparation of the diffusion layer will not affect the overall passivation of the battery if the back structure is intact.

[0057] In a specific embodiment of the present invention, the temperature of the high-temperature annealing is preferably 750℃~900℃, more preferably 800℃~900℃; and the time of the high-temperature annealing is 30~60 min.

[0058] In one specific embodiment of the present invention, the high-temperature annealing can be performed during the preparation of the N-type doped region on the back surface.

[0059] After high-temperature annealing, the phosphorus-doped diffusion source layer is removed to obtain a low-concentration phosphorus-doped structure. In this invention, hydrofluoric acid solution is preferably used for cleaning to remove the phosphorus-doped diffusion source layer. If the phosphorus-doped diffusion source layer contains amorphous silicon, it is preferable to remove the phosphorus-doped diffusion source layer by cleaning with a combination of hydrofluoric acid solution and alkaline solution. Since the innermost layer of the phosphorus-doped diffusion source layer is a nano-silicon oxide layer, the entire phosphorus-doped diffusion source layer is easy to clean and leaves no residue.

[0060] In another specific embodiment of the present invention, if a portion of the positive surface of the silicon substrate has a phosphorus-doped diffusion region, a patterning process is required. The patterning process can be performed before the preparation of the phosphorus-doped diffusion source layer, such as by polymer coating, to expose only the surface of the silicon substrate where the phosphorus-doped diffusion region needs to be prepared. Alternatively, it can be performed after high-temperature annealing, in which case the patterning process can be laser etching to remove part of the phosphorus-doped diffusion region. More specifically, wet cleaning is performed after the patterning process.

[0061] In one specific embodiment of the present invention, a PN junction is preferably prepared on the back surface of the silicon substrate before preparing a phosphorus-doped diffusion source layer on the front surface of the silicon substrate; the PN junction is prepared by a method known to those skilled in the art.

[0062] In a specific embodiment of the present invention, after removing the phosphorus-doped diffusion source layer, a passivation layer is prepared on the front surface and the back surface; the passivation layer is the same as described above, and will not be repeated here.

[0063] In one specific embodiment provided by the present invention, see [link to specific embodiment]. Figure 2 , Figure 2 This invention provides a schematic diagram of a specific fabrication process for a low-concentration phosphorus-doped structure; the preferred method for fabricating the low-concentration phosphorus-doped structure is as follows: A1) providing a silicon substrate, with the structure as shown in the diagram. Figure 2 As shown in (a), a P-type doped layer is prepared on the back surface of a silicon substrate. Specifically, chemical vapor deposition is preferably used to prepare the P-type doped layer on the back surface of the silicon substrate. More specifically, a tunneling oxide layer and an amorphous silicon layer are sequentially deposited on the back surface of the silicon substrate, followed by annealing to obtain the P-type doped layer, with the structure shown in Figure 1. Figure 2 (b) and Figure 2 As shown in (c); A2) Texturing is performed on the positive surface of the silicon substrate, with the structure as shown in [image]. Figure 2 As shown in (d); A3) A phosphorus-doped diffusion source layer is prepared on the positive surface of the texturized silicon substrate, with the structure shown in Figure 1. Figure 2As shown in (e); A4) Remove the region corresponding to the N-type doped region in the P-type doped layer (and also remove the corresponding position of the intrinsic region if applicable), retaining only the part of the P-type doped region, the structure is as follows. Figure 2 As shown in (f); the removal method can be any method well known to those skilled in the art, specifically laser etching; after etching, it is preferable to further clean the damaged layer with an alkaline solution; the mass concentration of the alkaline solution is preferably 2%~5%; the alkaline solution is preferably sodium hydroxide and / or potassium hydroxide solution; A5) An N-type doped layer is prepared on the back surface, with the structure as shown in (f). Figure 2 (g) and Figure 2 As shown in (h); specifically, it is preferable to prepare an N-type doped layer on the back surface of a silicon substrate using chemical vapor deposition; more specifically, a tunneling oxide layer and an amorphous silicon layer are sequentially deposited on the back surface of the silicon substrate, followed by high-temperature annealing; during the high-temperature annealing process, not only is the conversion of amorphous silicon to polycrystalline silicon achieved, forming an N-type doped region, but also active atoms such as phosphorus in the phosphorus doping diffusion source layer on the front surface diffuse into the silicon substrate, achieving the formation of a phosphorus doped diffusion region on the front surface; A6) Remove part of the N-type doped layer deposited on the surface of the P-type doped region and the intrinsic region on the back surface, such as if the front surface only has a partial phosphorus doped diffusion region, and also remove part of the phosphorus doped diffusion region on the front surface, resulting in a structure as shown in Figure 2 As shown in (i); the preferred removal method is laser etching, and after etching, the damaged layer is preferably cleaned with an alkaline solution; the alkaline solution is the same as described above, and will not be repeated here; A7) texturing is performed on the N-type doped region of the back surface, with the structure as shown in Figure 2 As shown in (j); A8) Remove the phosphorus-doped diffusion source layer, the structure is as follows Figure 2 As shown in (k); A9) Passivation layers are prepared on the front and back surfaces, specifically by sequentially preparing a silicon oxide layer and an aluminum oxide / silicon nitride layer, as shown in the diagram. Figure 2 As shown in (l); A10) is subjected to a low-temperature heat treatment process (FGA treatment) under a nitrogen-hydrogen mixed gas atmosphere, and the structure is as follows. Figure 2 As shown in the middle (m).

[0064] The preparation method provided by this invention can prepare diffusion structures with low surface phosphorus concentration, and the concentration is adjustable.

[0065] The present invention also provides a solar cell comprising the aforementioned low-concentration phosphorus doping structure.

[0066] To further illustrate the present invention, the following detailed description of a low-concentration phosphorus-doped structure, its preparation method, and a solar cell provided by the present invention is provided in conjunction with embodiments.

[0067] All reagents used in the following examples are commercially available.

[0068] Comparative Example 1

[0069] An N-type double-textured silicon wafer with a thickness of 140 μm and a resistivity of 2.4 Ω·cm was used. This wafer has a reflectivity of 11%–13% in the visible light band. After standard RCA cleaning, it was placed in an ALD chamber for AlO₂ deposition. x Trimethylaluminum (TMA):H₂O = 0.3:0.15 (flow ratio), 200℃, deposition thickness 12 nm. Then transferred to a tube furnace for annealing at 450℃ for 30 min under nitrogen atmosphere; subsequently transferred to a PECVD chamber at 380℃ to deposit SiN. x The SiH4:NH3 ratio was 2:18 (flow rate), the deposition thickness was 75 nm, and finally transferred to a tube furnace for annealing at 490℃ for 60 min in a nitrogen / hydrogen mixed gas (N2 flow rate 1500 sccm, H2 flow rate 150 sccm). The resulting product structure is as shown below. Figure 3 As shown. Sinton test, single-sided. J 0~2.5~3 fA / cm 2 .

[0070] Comparative Example 2

[0071] An N-type double-textured silicon wafer with a thickness of 140 μm and a resistivity of 2.4 Ω·cm was used. This wafer exhibited a reflectivity of 11%–13% in the visible light band. After standard RCA cleaning, thermo-oxidative silicon oxide was grown in a tube furnace under a pure oxygen atmosphere at 400 °C for 10 min. Subsequently, AlOx was deposited in an ALD chamber at 200 °C with a TMA:H2O flow ratio of 0.3:0.15 to a thickness of 12 nm. The wafer was then transferred to a tube furnace for annealing at 450 °C for 30 min under a nitrogen atmosphere. Next, SiNx was deposited in a PECVD chamber under the same conditions as in Comparative Example 1. Finally, the wafer was transferred to a tube furnace for annealing at 490 °C for 60 min in a nitrogen / hydrogen mixture (N2 flow rate 1500 sccm, H2 flow rate 150 sccm). The resulting product structure is shown below. Figure 4 As shown. Sinton test, single-sided. J 0~2.5~2.8fA / cm 2 .

[0072] Comparative Example 3

[0073] Using an n-type silicon wafer with a thickness of 140 μm and a resistivity of 2.4 Ω·cm, after standard RCA cleaning, the following steps were performed: S1) PECVD backside preparation p -TOPCon: Tubular annealing furnace: O2 flow rate 1000 sccm, 400 °C, 10 min; Deposition of ultrathin silicon oxide: N2O flow rate 30 sccm, temperature 180 °C, deposition thickness 1.2 nm; Deposition of doped amorphous silicon: SiH4:H2:B2H6=10:6:1.5 (flow ratio), temperature 180 °C, deposition thickness 30 nm; Tube annealing furnace: nitrogen atmosphere, 900 °C, 130 min; S2) Laser ablation of the corresponding i-region (4% of the area) and n-region (15% of the area). The default image size here is 182×182cm. 2 Clean the damaged layer with a 3% sodium hydroxide solution; S3) Preparation of n-TOPCon by PECVD on the back side: Deposition of ultrathin silicon oxide: N2O flow rate 30 sccm, temperature 180 °C, deposition time 350 s; Deposition of doped amorphous silicon: SiH4:H2:PH3=1:3:1 (flow ratio), temperature 180 °C, deposition time 150 s, deposition thickness 90 nm; Tube annealing furnace: nitrogen atmosphere, 800 °C, 30 min; Laser removal of the corresponding back i-region (occupying 4% of the area) and cleaning of the damaged layer with 3% sodium hydroxide solution; S4) A texturing agent is used to prepare the i-zone of the front and back sides to make its reflectance in the visible light band 11%~13%; S5) Preparation of passivation layer: Standard RCA cleaning, followed by preparation according to the method of Comparative Example 1, yielded the product structure as shown below. Figure 5 As shown.

[0074] Comparative Example 4

[0075] Using an n-type silicon wafer with a thickness of 140 μm and a resistivity of 2.4 Ω·cm, after standard RCA cleaning, the following steps were performed: S1) PECVD backside preparation p -TOPCon: Tubular annealing furnace: O2 flow rate 1000 sccm, 400 °C, time 10 min; Deposition of ultrathin silicon oxide: N2O flow rate 30 sccm, temperature 180 °C, deposition thickness 1.2 nm; Deposition of doped amorphous silicon: SiH4:H2:B2H6=10:6:1.5 (flow ratio), temperature 180 °C, deposition thickness 30 nm; Tube annealing furnace: nitrogen atmosphere, 900 °C, 130 min; S2) Laser ablation of the corresponding i-region (4% of the area) and n-region (15% of the area). The default image size here is 182×182cm. 2 Clean the damaged layer with a 3% sodium hydroxide solution; S3) Preparation of n-TOPCon by PECVD on the back side: Deposition of ultrathin silicon oxide: N2O flow rate 30 sccm, temperature 180 °C, deposition time 350 s; Deposition of doped amorphous silicon: SiH4:H2:PH3 = 1:3:1 (flow ratio), temperature 180 °C, deposition time 150 s, deposition thickness 90 nm; Tube annealing furnace: nitrogen atmosphere, 800 °C, 30 min; Laser removal of the corresponding back i-region (occupying 4% of the area) and cleaning of the damaged layer with 3% sodium hydroxide solution; S4) A texturing agent is used to prepare the front and the texturized surface (the back is not texturized), so that its reflectance in the visible light band is 11%~13%; S5) Preparation of passivation layer: Standard RCA cleaning, followed by preparation according to the method of Comparative Example 2, yielded the product structure as shown below. Figure 6 As shown.

[0076] Comparative Example 5

[0077] N-type double-textured silicon wafers (for 140 μm, 2.4 Ω·cm N-type double-textured silicon wafers, pre-deposited at approximately 800°C for about 20 minutes using the low-pressure POC13 method, with O2 and POCl3 flow rates of 480 sccm and 400 sccm respectively, supplemented by deposition at 840°C for 6 minutes), after standard RCA cleaning, thermo-oxygen silicon oxide is grown at 400°C for 15 minutes in pure oxygen in a tubular annealing furnace; then placed in an ALD chamber for AlO₂ deposition. x The TMA:H2O ratio was 0.3:0.15, the deposition temperature was 200 °C, and the deposition thickness was 12 nm. The material was then transferred to a tube furnace and annealed at 450 °C for 30 min under a nitrogen atmosphere. Subsequently, it was transferred to a PECVD reactor to deposit SiNx under the same deposition conditions as Comparative Example 1. Finally, it was transferred to a tube furnace and annealed at 490 °C for 60 min in a nitrogen / hydrogen mixture (N2 flow rate 1500 sccm, H2 flow rate 150 sccm). The resulting product structure is as shown below. Figure 7 As shown. Sinton test, single-sided. J 0~60fA / cm 2 .

[0078] Comparative Example 6

[0079] N-type double-textured silicon wafers (for 140 μm N-type double-textured silicon wafers with a resistivity of 2.4 Ω·cm and a reflectivity of 11%~13% in the visible light band, pre-deposition was performed at approximately 800°C for about 20 minutes using the low-pressure POC13 method, with O2 and POCl3 flow rates of 480 sccm and 400 sccm respectively, followed by deposition at 840°C for 6 minutes), after standard RCA cleaning, were placed in an ALD chamber for AlOx deposition, with TMA:H2O = 0.3:0.15, at 200°C, to a deposition thickness of 12 nm. The product was then transferred to a tube furnace and annealed at 450 °C for 30 min under a nitrogen atmosphere. Subsequently, it was transferred to PECVD for SiNx deposition under the same conditions as Comparative Example 1. Finally, it was transferred to a tube furnace and annealed at 490 °C for 60 min in a nitrogen / hydrogen mixed gas atmosphere (N2 flow rate 1500 sccm, H2 flow rate 150 sccm), yielding the product structure shown below. Figure 8 As shown.

[0080] Comparative Example 7

[0081] N-type double-textured silicon wafers (for 140 μm N-type double-textured silicon wafers with a resistivity of 2.4 Ω·cm and a reflectivity of 11%–13% in the visible light band, pre-deposited at approximately 800°C for about 20 minutes using the low-pressure POC13 method, with O2 and POCl3 flow rates of 480 sccm and 400 sccm respectively, followed by deposition at 840°C for 6 minutes), after standard RCA cleaning, thermo-oxidative silicon growth in a tube furnace with pure oxygen at 400°C for 15 minutes; then SiN deposition in PECVD. x The deposition conditions were the same as in Comparative Example 1. Finally, the mixture was transferred to a tube furnace and annealed at 490 °C for 60 min in a nitrogen / hydrogen mixture (N2 flow rate 1500 sccm, H2 flow rate 150 sccm). The resulting product structure was as shown in the figure. Figure 9 As shown.

[0082] Example 1

[0083] An N-type double-textured silicon wafer with a thickness of 140 μm and a resistivity of 2.4 Ω·cm was used. This wafer has a reflectivity of 11%–13% in the visible light band. After standard RCA cleaning, the following steps were performed: S1) Shallow phosphorus diffusion is achieved by growing phosphorus-doped silica via PECVD: An ultrathin silicon oxide layer, an intrinsic silicon oxide layer, and a phosphorus-doped silicon oxide layer were deposited sequentially. The precursor for the ultrathin silicon oxide was N2O, with a flow rate of 30 sccm, a deposition temperature of 180 °C, and a deposition thickness of approximately 1.3 nm. The gas flow rate ratio of the intrinsic silicon oxide precursor was SiH4:H2:N2O = 1.5:15:30 (flow rate ratio), with a deposition temperature of 180 °C and a deposition thickness of 5 nm. The gas flow rate ratio of the phosphorus-doped silicon oxide precursor was SiH4:PH3:H2:N2O = 1.5:3:15:300 (flow rate ratio), with a deposition temperature of 180 °C and a deposition thickness of 12 nm. High-temperature annealing and cleaning: Anneal at 800℃ for 30 min, immerse in HF for 20~30 min. If the surface is still light yellow, it is not clean. It needs to be briefly cleaned with 3% TMAH solution at 25℃ for 10 s, and then deionized water.

[0084] S2) Passivation layer preparation: After standard RCA cleaning, thermo-oxidative silicon oxide was grown in a tube furnace in pure oxygen at 400 °C for 10 min. Then, AlOx was deposited in an ALD chamber with a TMA:H2O ratio of 0.3:0.15 (flow rate ratio) at 200 °C, resulting in a deposition thickness of 12 nm. The layer was then transferred to a tube furnace for annealing at 450 °C for 30 min under a nitrogen atmosphere. Subsequently, SiNx was deposited in a PECVD chamber under the same conditions as Comparative Example 1. Finally, the layer was transferred to a tube furnace for annealing at 490 °C for 60 min in a nitrogen / hydrogen mixed gas atmosphere (N2 flow rate 1500 sccm, H2 flow rate 150 sccm). The resulting product structure is as shown below. Figure 10 As shown. Sinton test, single-sided. J 0~2~2.5 fA / cm 2 .

[0085] Example 2

[0086] The preparation method is the same as in Example 1, except that the annealing temperature of phosphorus-doped silicon oxide or polycrystalline silicon is changed. Annealing is performed at 750 °C for 30 min, followed by Sinton testing on one side. J 0~3 - 4 fA / cm 2 The minority carrier lifetime is 4000~4500 μs.

[0087] Example 3

[0088] The preparation method is the same as in Example 1, except that the annealing temperature of phosphorus-doped silicon oxide or polycrystalline silicon is changed. Annealing is performed at 850°C for 30 min, followed by Sinton testing on one side. J 0~3 - 4 fA / cm 2 Minority carrier lifetime is 2000-2500 μs.

[0089] Example 4

[0090] The preparation method is the same as in Example 1, except that the annealing temperature of phosphorus-doped silicon oxide or polycrystalline silicon is changed. Annealing is performed at 900°C for 30 min, followed by Sinton testing on one side. J 0~1 - 2 fA / cm 2 The minority carrier lifetime is 1000-2000 μs.

[0091] Example 5

[0092] An N-type double-textured silicon wafer with a thickness of 140 μm and a resistivity of 2.4 Ω·cm was used. This wafer exhibited a reflectivity of 11%–13% in the visible light band. After standard RCA cleaning and the same light phosphorus diffusion steps as in Example 1, it was placed in an ALD chamber for AlOx deposition at 200 °C with a TMA:H2O ratio of 0.3:0.15 (flow rate), achieving a deposition thickness of 12 nm. The wafer was then transferred to a tube furnace and annealed at 450 °C for 30 min under a nitrogen atmosphere. Subsequently, it was transferred to a PECVD chamber for SiNx deposition under the same conditions as Comparative Example 1. Finally, it was transferred to a tube furnace and annealed at 490 °C for 60 min in a nitrogen / hydrogen mixture with an N2 flow rate of 1500 sccm and an H2 flow rate of 150 sccm. The resulting product structure is as shown below. Figure 11 As shown. Sinton test, single-sided. J 0.6 ~ 8 fA / cm 2 .

[0093] Example 6

[0094] An N-type double-textured silicon wafer with a thickness of 140 μm and a resistivity of 2.4 Ω·cm was used. This wafer exhibited a reflectivity of 11%–13% in the visible light band. After standard RCA cleaning and the same light phosphorus diffusion steps as in Example 1, it was placed in a tube furnace in pure oxygen at 400 °C for 10 min to grow thermo-oxidative silicon. Subsequently, it was placed in a PECVD furnace to deposit SiNx under the same deposition conditions as Comparative Example 1. Finally, it was transferred to a tube furnace and annealed at 490 °C for 60 min in a nitrogen / hydrogen mixture (N2 flow rate 1500 sccm, H2 flow rate 150 sccm). The resulting product structure is as shown below. Figure 12 As shown. Sinton test, single-sided. J 0~6 - 7 fA / cm 2 .

[0095] Example 7

[0096] An N-type double-textured silicon wafer with a thickness of 140 μm and a resistivity of 2.4 Ω·cm was used. The reflectivity of this silicon wafer in the visible light band was 11%~13%. After standard RCA cleaning, the shallow phosphorus diffusion process was the same as in Example 1. Then, the phosphorus-doped silicon oxide on the front side corresponding to the n-region on the back side of the TBC was removed by laser, removing 15% of the area. The damaged layer was then retextured using a 3 wt% KOH solution and an alkaline etching agent at room temperature for 30 seconds, so that its reflectivity in the visible light band was 11%~13%.

[0097] Then, thermo-oxygenated silicon dioxide was grown in a tube furnace at 400 °C for 10 min using pure oxygen, followed by AlOx deposition via ALD (Transfer Ma:H₂O = 0.3:0.15 flow rate ratio) at 200 °C to a thickness of 12 nm. After annealing at 450 °C for 30 min in the tube furnace, SiNx was deposited via PECVD under the same conditions as Comparative Example 1. Finally, the product was annealed at 490 °C for 60 min in a tube furnace under a nitrogen / hydrogen mixed atmosphere (N₂ flow rate 1500 sccm, H₂ flow rate 150 sccm). The resulting product structure is as shown below. Figure 13 As shown. Sinton test, single-sided. J 0~2.5~2.7 fA / cm 2 .

[0098] Example 8

[0099] The TBC battery was fabricated with a front-side structure consistent with the shallow phosphorus diffused / SiOx / AlOx / SiNx front-side structure of Example 1. The back-side fabrication method is detailed in the specific implementation process. The battery structure is as follows. Figure 14 As shown: Using an n-type silicon wafer with a thickness of 140 μm and a resistivity of 2.4 Ω·cm, after standard RCA cleaning, the following steps were performed: S1) PECVD backside preparation p -TOPCon: Tubular annealing furnace: O2 flow rate 1000 sccm, 400 °C, deposition time 10 min; Deposition of ultrathin silicon oxide: N2O flow rate 30 sccm, temperature 180 °C, deposition thickness 1.2 nm; Deposition of doped amorphous silicon: SiH4:H2:B2H6=10:6:1.5, temperature 180 °C, deposition thickness 30 nm; Tube annealing furnace: nitrogen atmosphere, 900 °C, 130 min; S2) A texturing agent is used to prepare a textured surface on the front side, so that its reflectivity in the visible light band is 11%~13%; S3) Shallow phosphorus diffusion is achieved by growing phosphorus-doped silica via PECVD: An ultrathin silicon oxide layer, an intrinsic silicon oxide layer, and a phosphorus-doped silicon oxide layer were deposited sequentially. The precursor for the ultrathin silicon oxide was N2O, with a flow rate of 30 sccm, a deposition temperature of 180°C, and a thickness of approximately 1.3 nm. The gas flow rate ratio of the intrinsic silicon oxide precursor was SiH4:H2:N2O = 1.5:15:30 (flow rate ratio), with a deposition temperature of 180°C and a deposition thickness of 5 nm. The gas flow rate ratio of the phosphorus-doped silicon oxide precursor was SiH4:PH3:H2:N2O = 1.5:3:15:30 (flow rate ratio), with a deposition temperature of 180°C and a deposition thickness of 12 nm. S4) Laser removal of the corresponding i-region (4% of the area) and n-region (15% of the area). The default image size here is 182×182cm. 2 Clean the damaged layer with a 3% sodium hydroxide solution; S5) Preparation of n-TOPCon by PECVD on the back side: Deposition of ultrathin silicon oxide: N2O flow rate 30 sccm, temperature 180 °C, deposition time 350 s; Deposition of doped amorphous silicon: SiH4:H2:PH3 = 1:3:1 (flow ratio), temperature 180 °C, deposition time 150 s, deposition thickness 90 nm; Tube annealing furnace: nitrogen atmosphere, 800 °C, 30 min; S6) Laser-remove the corresponding back i-region (occupying 4% of the area), and clean the damaged layer with 3% sodium hydroxide solution; S7) A texturing agent is used to prepare the back surface of the fabric, so that its reflectance in the visible light band is 11%~13%; S8) Preparation of passivation layer: After HF washing for 30 min, followed by standard RCA cleaning, thermo-oxygen silicon oxide was grown in a tube furnace at 400 °C for 10 min in pure oxygen. Then, AlOx was deposited in an ALD chamber with a TMA:H2O ratio of 0.3:0.15 (flow rate ratio) at 200 °C to a thickness of 12 nm. The deposit was then transferred to a tube furnace and annealed at 450 °C for 30 min in a nitrogen atmosphere. Subsequently, SiNx was deposited in a PECVD chamber under the same conditions as Comparative Example 1. Finally, the deposit was transferred to a tube furnace and annealed at 490 °C for 60 min in a nitrogen / hydrogen mixture at an N2 flow rate of 1500 sccm and an H2 flow rate of 150 sccm.

[0100] Example 9

[0101] TBC battery fabrication, with a front structure similar to that of Example 7, featuring localized shallow phosphorus diffusion / SiO2. x / AlO x / SiNx Consistent, battery structure as Figure 15 As shown.

[0102] An n-type silicon wafer with a thickness of 140 μm and a resistivity of 2.4 Ω·cm was used. After standard RCA cleaning, the following steps were performed: S1) PECVD backside preparation p -TOPCon: Tubular annealing furnace: O2 flow rate 1000 sccm, 400 °C, 10 min; Deposition of ultrathin silicon oxide: N2O flow rate 30 sccm, temperature 180 °C, deposition thickness 1.2 nm; Deposition of doped amorphous silicon: SiH4:H2:B2H6=10:6:1.5 (flow ratio), temperature 180 °C, deposition thickness 30 nm; Tube annealing furnace: nitrogen atmosphere, 900 °C, 130 min; S2) A texturing agent is used to prepare a textured surface on the front side, so that its reflectivity in the visible light band is 11%~13%; S3) Shallow phosphorus diffusion is achieved by growing phosphorus-doped silica via PECVD: An ultrathin silicon oxide layer, an intrinsic silicon oxide layer, and a phosphorus-doped silicon oxide layer were deposited sequentially. The precursor for the ultrathin silicon oxide was N2O, with a flow rate of 30 sccm, a deposition temperature of 180 °C, and a deposition thickness of approximately 1.3 nm. The gas flow rate ratio of the intrinsic silicon oxide precursor was SiH4:H2:N2O = 1.5:15:30 (flow rate ratio), with a deposition temperature of 180 °C and a deposition thickness of 5 nm. The gas flow rate ratio of the phosphorus-doped silicon oxide precursor was SiH4:PH3:H2:N2O = 1.5:3:15:30 (flow rate ratio), with a deposition temperature of 180 °C and a deposition thickness of 12 nm. S4) Laser removal of the corresponding i-region (4% of the area) and n-region (15% of the area). The default image size here is 182×182cm. 2 Clean the damaged layer with a 3% sodium hydroxide solution; S5) Preparation of n-TOPCon by PECVD on the back side: Deposition of ultrathin silicon oxide: N2O flow rate 30 sccm, temperature 180 °C, deposition time 350 s; Deposition of doped amorphous silicon: SiH4:H2:PH3 = 1:3:1 (flow ratio), temperature 180 °C, deposition time 150 s, deposition thickness 90 nm; Tube annealing furnace annealing: nitrogen atmosphere, 800℃, 30 min; S6) Laser remove the corresponding back i area (occupying 4% of the area) and the area on the front corresponding to the back i and n areas, and clean the damaged layer with 3% sodium hydroxide solution; S7) A texturing agent is used to prepare the i-zone of the front and back sides to make its reflectance in the visible light band 11%~13%; S8) Preparation of passivation layer: After soaking in HF for 30 min and cleaning with standard RCA, thermo-oxidative silicon dioxide was grown in a tube furnace in pure oxygen at 400 °C for 10 min. Then, AlOx was deposited in an ALD chamber with a TMA:H2O ratio of 0.3:0.15 (flow rate ratio) at 200 °C to a thickness of 12 nm. The deposit was then transferred to a tube furnace and annealed at 450 °C for 30 min under a nitrogen atmosphere. Subsequently, SiNx was deposited in a PECVD chamber under the same conditions as Comparative Example 1. Finally, the deposit was transferred to a tube furnace and annealed at 490 °C for 60 min in a nitrogen / hydrogen mixture at an N2 flow rate of 1500 sccm and an H2 flow rate of 150 sccm.

[0103] The performance of the products prepared in Examples 1 to 9 was tested. Multiple samples of each product were tested, and the results are shown in Tables 1 to 4. The passivation data in Tables 1, 3, and 4 were measured using quasi-steady-state conductivity (QSSPC, Sinton WCT-120) technology. The relevant data in Table 2 were obtained by device simulation using an IV characteristic tester and / or Quokka 3. The electroactive doping concentration in Table 1 was measured using an electrochemical capacitance-voltage (ECV) test system (Buchanan CVP21). Table 1 shows the minimum to maximum values ​​of multiple samples, and Table 2 shows the average values ​​of multiple samples.

[0104] The product obtained in Comparative Example 5 was tested, and its ECV curve was obtained as follows: Figure 16 As shown.

[0105] The products obtained in Examples 1 to 4 were tested, and their ECV curves were obtained as follows: Figure 17 As shown.

[0106] The samples obtained in Comparative Example 6 and Example 7 were subjected to TEM imaging, and the resulting HR-TEM images are shown below. Figure 18 , Figure 19 As shown.

[0107] TEM images of the samples obtained in Comparative Example 6 and Example 7 were taken, and the EDS-HAADF atomic-level elemental distribution images are shown below. Figure 20 , Figure 21 As shown.

[0108] TEM images were taken of the samples obtained in Comparative Example 6 and Example 7. Figure 18 , Figure 19 The HR-TEM image of the area within the red box was analyzed, and the IFFT, FFT, and related gravity analysis data are shown in the figure below. Figure 22 , Figure 23 As shown.

[0109] SIMS testing was performed on the samples obtained in Comparative Example 6 and Example 7 to obtain the distribution of P element in the silicon substrate as follows: Figure 24 As shown.

[0110] Table 1. Passivation performance of passivation sheets in the examples and comparative examples.

[0111]

[0112] Table 2 Battery performance of Examples 8-9 and Comparative Examples 3-4

[0113]

[0114] Table 3 UV irradiation attenuation of Comparative Example 1, Comparative Example 2 and Example 1

[0115]

[0116] Table 4 UV irradiation attenuation of Comparative Example 1, Comparative Example 2 and Example 1

[0117]

[0118] In summary, the structure provided by this invention has the following advantages: 1) This structure can be used to prepare diffusion structures with low surface phosphorus concentrations, the concentration of which is adjustable, and the actual concentration can be lower than 1×18 cm⁻¹. -3 The surface phosphorus concentration is two orders of magnitude lower than that of existing industrial methods; 2) Due to the lower surface phosphorus concentration, AlOx / SiNx, currently used in industry, can be used for surface passivation with high passivation quality; J0 can be achieved below 3 fA / cm. 2 Under optimized conditions, it can reach 1 fA / cm 2 ; 3) Introducing positive surface phosphorus diffusion has a gettering effect on metal impurities, which helps to improve bulk lifetime; combined with excellent surface passivation effect, the bulk lifetime of mainstream n-type silicon wafers (1~7 Ω·cm) can be increased to more than 15 ms, which is significantly better than the passivation effect of most existing passivation films. 4) This method can introduce impurities such as carbon and nitrogen, which can further improve surface passivation and increase bulk lifespan; 5) Introducing a phosphorus front field into the front surface can allow some electrons to be transferred to the n-region collection region through the front field, thereby helping to maintain the battery's FF without decreasing while increasing the area ratio of the p-region on the back side and the short-circuit current. 6) The phosphorus diffusion annealing temperature is between 700℃ and 900℃, which is moderate and compatible with existing battery diffusion technologies; 7) It has a positive phosphorus diffusion structure, which can reduce the battery's lifespan degradation and efficiency decline under ultraviolet irradiation; 8) The membranes involved in this process all have good controllability in preparation and a wide process window, making them suitable for large-scale industrialization; 9) This low-concentration phosphorus doping structure can introduce impurities such as carbon and phosphorus into the silicon wafer substrate, which can improve the mechanical properties of the silicon wafer.

[0119] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A low-concentration phosphorus-doped structure, characterized in that, A silicon substrate; the silicon substrate includes opposite front and back surfaces; all or a portion of the front surface of the silicon substrate has a phosphorus-doped diffusion region; the phosphorus-doped diffusion region includes activated phosphorus atoms and non-activated phosphorus atoms; the concentration of activated phosphorus atoms in the phosphorus-doped diffusion region is no more than 1 x 1019 atoms / cm3; and the depth of the phosphorus-doped diffusion region is no more than 2 μm. 19 cm -3 ​ 2. The low-concentration phosphorus-doped structure according to claim 1, characterized in that, The concentration of activated phosphorus atoms in the phosphorus-doped diffusion region does not exceed 4 × 10⁻⁶. 18 cm -3 The depth of the phosphorus-doped diffusion region is 0.01~1 μm.

3. The low-concentration phosphorus-doped structure according to claim 1, characterized in that, The silicon substrate is an N-type silicon substrate or a P-type silicon substrate; The phosphorus-doped diffusion region also includes oxygen and / or hydrogen elements; And / or, the phosphorus-doped diffusion region further includes carbon and / or nitrogen elements.

4. The low-concentration phosphorus-doped structure according to claim 1, characterized in that, A PN junction is provided on the back surface of the silicon substrate.

5. The low-concentration phosphorus-doped structure according to claim 1, characterized in that, The back surface of the silicon substrate is provided with alternating P-type doped regions and N-type doped regions. The front surface has a phosphorus-doped diffusion region in all or part; if it has a phosphorus-doped diffusion region in part, the phosphorus-doped diffusion region includes a P-type doped region in the vertical projection plane of the back surface.

6. The low-concentration phosphorus-doped structure according to claim 5, characterized in that, An intrinsic region is provided between the P-type doped region and the N-type doped region.

7. The low-concentration phosphorus-doped structure according to any one of claims 5 to 6, characterized in that, A tunneling oxide layer is also disposed between the P-type doped region and the silicon substrate; A tunneling oxide layer is also disposed between the N-type doped region and the silicon substrate; And / or, a passivation layer is provided on the positive surface of the silicon substrate.

8. A method for preparing a low-concentration phosphorus-doped structure, characterized in that, The preparation of the low-concentration phosphorus-doped structure according to claim 1 includes the following steps: S1) provides a silicon substrate; S2) A phosphorus-doped diffusion source layer is prepared on the positive surface of the silicon substrate; the phosphorus-doped diffusion source layer comprises a nano-silicon oxide layer and a phosphorus-containing functional layer in a direction away from the silicon substrate; the phosphorus-containing functional layer is selected from a phosphorus-containing silicon oxide layer and / or a phosphorus-containing amorphous silicon layer. S3) The silicon substrate on which the phosphorus-doped diffusion source layer is prepared is subjected to high-temperature annealing, and then the phosphorus-doped diffusion source layer is removed to obtain a low-concentration phosphorus-doped structure.

9. The preparation method according to claim 8, characterized in that, The thickness of the nano-silicon oxide layer is 1~10 nm; The thickness of the phosphorus-containing functional layer is 10~50 nm; And / or, the phosphorus-containing functional layer further includes carbon and / or nitrogen elements; And / or, an intermediate layer is further provided between the nano-silicon oxide layer and the phosphorus-containing functional layer; the intermediate layer is selected from one or more of the intrinsic silicon oxide layer, carbon-containing silicon oxide layer, nitrogen-containing silicon oxide layer, amorphous silicon layer, carbon-containing amorphous silicon layer and nitrogen-containing amorphous silicon layer; the thickness of the intermediate layer is 5~50 nm; And / or, the surface of the phosphorus-containing functional layer away from the silicon substrate is further provided with an outer surface layer; the outer surface layer is selected from one or more of intrinsic silicon oxide layer, carbon-containing silicon oxide layer, nitrogen-containing silicon oxide layer, amorphous silicon layer, carbon-containing amorphous silicon layer and nitrogen-containing amorphous silicon layer; the thickness of the outer surface layer is 5~50 nm; And / or, the high-temperature annealing temperature in step S3) is greater than or equal to 700°C.

10. A solar cell, characterized in that, This includes the low-concentration phosphorus-doped structure as described in any one of claims 1 to 7, or the low-concentration phosphorus-doped structure prepared by the preparation method described in claim 8 or 9.

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