A method for preparing a surface metal layer of a power semiconductor chip

Abstract

The application relates to the technical field of power semiconductor chip manufacturing, and particularly discloses a preparation method of a power semiconductor chip surface metal layer, which comprises the following steps: taking SiC or GaN as a substrate, carrying out surface cleaning, plasma etching and interface modification pretreatment, sequentially adopting magnetron sputtering to prepare a titanium-tantalum alloy transition layer, adopting cyanide-free electroplating to prepare a silver-copper-tin alloy main body layer, adopting electron beam evaporation to prepare a gold-palladium alloy oxidation-resistant protective layer, and then carrying out segmented collaborative annealing and post-treatment detection to obtain a finished product. Through the combination of interface modification and layered alloy preparation, the application improves the bonding strength of the metal layer and the substrate, optimizes the electric conduction and heat conduction performance, is environmentally friendly in the cyanide-free process, solves the pain points of the prior art, adapts to the demand of high-voltage and high-current chips, and is high in reliability.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor chip manufacturing technology, specifically to a method for preparing a surface metal layer for a power semiconductor chip. Background Technology

[0002] Power semiconductor chips are core components in fields such as new energy vehicles, rail transportation, and smart grids. Their surface metal layers primarily play a crucial role in current transmission, heat dissipation, and packaging interconnection. The quality of the metal layer fabrication directly determines the chip's power density, reliability, and service life. Current methods for fabricating surface metal layers in power semiconductor chips mainly include sputtering, evaporation, electroplating, and chemical vapor deposition. Among these, sputtering has become the mainstream technology due to its good step coverage and excellent film uniformity.

[0003] However, existing fabrication technologies still have many drawbacks: First, the interfacial bonding between the metal layer and the chip substrate is insufficient, and peeling and detachment are prone to occur under high temperature and high frequency conditions, leading to chip failure; second, the metal layers prepared by traditional sputtering processes have problems such as coarse grains and many lattice defects, and the electrical and thermal conductivity is difficult to meet the extreme requirements of high-end power chips; third, existing processes mostly use a single metal or simple alloy system, which cannot take into account the ohmic contact characteristics, anti-electromigration ability and packaging compatibility of the metal layer; fourth, some processes pose environmental risks and do not conform to the industrial trend of green manufacturing.

[0004] To address the aforementioned issues, existing technologies have primarily improved the process by optimizing sputtering parameters and adding transition layers, but none of these methods fundamentally resolve the synergistic problems of interface bonding, performance balance, and environmental friendliness. Therefore, developing a method for preparing surface metal layers for power semiconductor chips that is free from existing patent references, exhibits high bonding strength, superior performance, and is environmentally friendly has become an urgent need for current industry development. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for preparing a metal layer on the surface of a power semiconductor chip. Through innovative interface modification, layer preparation and synergistic annealing processes, a strong bond between the metal layer and the substrate, high electrical and thermal conductivity and high stability are achieved, which meets the usage requirements of high-end power chips and green manufacturing requirements.

[0006] To solve the above-mentioned technical problems, the technical solution provided by the present invention is: a method for preparing a metal layer on the surface of a power semiconductor chip, comprising the following steps:

[0007] Step 1: Pretreatment of chip substrate: Select the power semiconductor chip substrate to be prepared with metal layer, and perform surface cleaning, plasma etching and interface modification treatment in sequence;

[0008] Step 2, Transition Metal Layer Preparation: A titanium-tantalum alloy transition layer is deposited on the pretreated chip substrate surface using magnetron sputtering. The mass ratio of titanium to tantalum is 7:3-8:2, and the sputtering vacuum degree is 5×10⁻⁻⁻⁴. 4 -1×10⁻³Pa, sputtering power of 300-400W, sputtering temperature of 150-200℃, and deposition thickness of 50-100nm;

[0009] Step 3, Preparation of the main metal layer: A silver-copper-tin alloy main metal layer is deposited on the surface of the transition metal layer using a cyanide-free electroplating process. The mass ratio of silver, copper, and tin is 85:10:5-90:5:5. The electroplating solution uses a cyanide-free sulfurous acid system, the electroplating temperature is 40-50℃, the current density is 0.5-1A / dm², and the deposition thickness is 1-3μm.

[0010] Step 4: Preparation of the antioxidant protective layer: A gold-palladium alloy antioxidant protective layer is deposited on the surface of the host metal layer using electron beam evaporation. The mass ratio of gold to palladium is 9:1-9.5:0.5, and the evaporation vacuum degree is 1×10⁻ 4 -5×10⁻ 4 Pa, with a deposition thickness of 20-50 nm;

[0011] Step 5, Co-annealing: The chip with the deposited metal layer is placed in an annealing furnace for segmented co-annealing, which goes through three stages in sequence: heating and holding, high temperature holding, and cooling. A mixture of nitrogen and hydrogen protective gas is introduced during the annealing process.

[0012] Step 6, Post-processing and Inspection: The annealed chip is surface polished, and then its performance is tested. The finished product is obtained after passing the test.

[0013] Further, in step 1, the surface cleaning adopts a step-by-step process of alkaline degreasing, acidic rust removal, deionized water rinsing, and vacuum drying; the plasma etching uses a mixed gas of argon and oxygen, with an etching power of 150-250W and an etching time of 30-60s; the interface modification treatment uses low-temperature plasma implantation technology to implant titanium ions into the substrate surface, with an implantation energy of 50-100eV and an implantation dose of 1×10¹. 5 -5×10¹ 5 ions / cm²;

[0014] Further, in step 1, the alkaline degreasing uses a sodium hydroxide solution with a mass concentration of 5%-10%, a temperature of 50-60℃, and a soaking time of 10-15 minutes; the acidic rust removal uses a dilute hydrochloric acid solution with a mass concentration of 8%-12%, a temperature of 25-30℃, and a soaking time of 5-8 minutes; the vacuum drying temperature is 80-100℃, the drying time is 20-30 minutes, and the vacuum degree is 1×10⁻²-5×10⁻² Pa.

[0015] Furthermore, in step 3, the cyanide-free electroplating solution contains silver ions at a concentration of 5-10 g / L, copper ions at a concentration of 1-2 g / L, and tin ions at a concentration of 0.5-1 g / L. Sodium citrate is added as a complexing agent, polyethylene glycol as a grain refiner, and 0.1-0.2 g / L of polypropylene glycol can also be added as a brightener.

[0016] Further, in step 5, the specific parameters of the synergistic annealing treatment are as follows: in the first stage, the temperature is increased to 200-250℃ at a heating rate of 5-10℃ / min and held for 30-40min; in the second stage, the temperature is increased to 400-450℃ at a heating rate of 3-5℃ / min and held for 60-90min; in the third stage, the temperature is decreased to room temperature at a cooling rate of 8-12℃ / min; the vacuum degree in the annealing furnace is 1×10⁻³-5×10⁻³Pa, the volume ratio of nitrogen to hydrogen in the mixed protective gas is 9:1, and the flow rate is 10-20sccm.

[0017] Furthermore, in step 6, the surface polishing precision is controlled within 0.1-0.5 μm; the performance testing includes metal layer thickness testing, adhesion testing, electrical conductivity testing, thermal conductivity testing, and high-temperature stability testing, wherein the adhesion is tested using the cross-cut test to ensure no detachment, and the resistivity is ≤1.5×10⁻ 8 Ω·m, thermal conductivity ≥300W / (m·K), no peeling or oxidation after 1000h high temperature insulation at 200℃.

[0018] Furthermore, the power semiconductor chip substrate is a SiC substrate or a GaN substrate.

[0019] The advantages of this invention compared to the prior art are:

[0020] This invention forms a micro-rough surface through plasma etching, combined with low-temperature titanium ion implantation modification and a titanium-tantalum alloy transition layer. This effectively alleviates the difference in thermal expansion coefficients between the metal layer and the chip substrate, improves the bonding strength between the metal layer and the substrate, avoids peeling and detachment problems under high-temperature conditions, and enhances chip reliability.

[0021] The main metal layer of this invention adopts a silver-copper-tin alloy system, combined with a synergistic annealing process, which optimizes the metal grain structure and reduces lattice defects. Compared with traditional single metal layers, the electrical and thermal conductivity is improved, which can meet the application requirements of high voltage and high current power chips.

[0022] The main metal layer of this invention adopts a cyanide-free electroplating process, which completely eliminates cyanide, avoids environmental pollution, and conforms to the trend of green manufacturing; the surface gold-palladium alloy protective layer can not only prevent oxidation, but also improve the compatibility of packaging interconnection and adapt to a variety of packaging processes.

[0023] This invention, through an innovative process route of "interface modification-layered alloy preparation-synergistic annealing" combined with a unique alloy ratio, forms a completely new metal layer preparation scheme, which solves the core pain points of existing technologies and has significant innovation and practicality. Detailed Implementation

[0024] Various exemplary embodiments of the present invention are described in detail below. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present invention.

[0025] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0026] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0027] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0028] The following is a detailed description of a method for preparing a surface metal layer of a power semiconductor chip according to the present invention.

[0029] A method for preparing a metal layer on the surface of a power semiconductor chip includes the following steps:

[0030] Step 1: Chip Substrate Pretreatment: Select the power semiconductor chip substrate (SiC or GaN substrate) to be prepared with the metal layer, and perform surface cleaning, plasma etching, and interface modification treatments sequentially. Surface cleaning adopts a step-by-step process of "alkaline degreasing - acidic rust removal - deionized water rinsing - vacuum drying" to remove oil, oxide layer, and impurities from the substrate surface. Plasma etching uses a mixture of argon and oxygen gas, with an etching power of 150-250W and an etching time of 30-60s, to form a micro-rough structure on the substrate surface and increase the contact area with the metal layer. Interface modification treatment uses low-temperature plasma implantation technology to implant titanium ions into the substrate surface at an implantation energy of 50-100eV and an implantation dose of 1×10¹. 5 -5×10¹ 5 The process involves adding ions / cm² to form a thin titanium-doped transition layer, enhancing interfacial adhesion. Alkaline degreasing uses a 5%-10% sodium hydroxide solution at 50-60℃ for 10-15 minutes. Acidic rust removal uses an 8%-12% dilute hydrochloric acid solution at 25-30℃ for 5-8 minutes. Vacuum drying is performed at 80-100℃ for 20-30 minutes, with a vacuum degree of 1×10⁻²-5×10⁻² Pa.

[0031] Step 2, Transition Metal Layer Preparation: A transition metal layer is deposited on the pretreated chip substrate surface using magnetron sputtering. The transition metal layer is a titanium-tantalum alloy layer with a titanium to tantalum mass ratio of 7:3-8:2. A titanium-tantalum alloy target with the corresponding ratio is used for sputtering. During sputtering, the vacuum level is controlled at 5×10⁻⁻⁻⁴. 4 -1×10⁻³Pa, sputtering power of 300-400W, sputtering temperature of 150-200℃, argon flow rate of 20-30sccm, deposition thickness of 50-100nm; the transition metal layer is used to alleviate the difference in thermal expansion coefficients between the metal layer and the substrate, while further improving the interfacial bonding strength and preventing subsequent metal layer peeling.

[0032] Step 3: Preparation of the main metal layer: A modified cyanide-free electroplating process is used to deposit the main metal layer on the surface of the transition metal layer. The main metal layer is a silver-copper-tin alloy layer, with a mass ratio of silver, copper, and tin of 85:10:5-90:5:5. The electroplating solution uses a cyanide-free sulfurous acid system, containing silver ions at a concentration of 5-10 g / L, copper ions at a concentration of 1-2 g / L, and tin ions at a concentration of 0.5-1 g / L. Sodium citrate is added as a complexing agent, and polyethylene glycol is added as a grain refiner. The electroplating temperature is 40-50℃, and the current density is... The electroplating concentration is 0.5-1 A / dm², the electroplating time is 30-60 min, and the deposition thickness is 1-3 μm. The main metal layer undertakes the main functions of current transmission and heat dissipation. The cyanide-free system avoids cyanide pollution and meets environmental protection requirements. 0.1-0.2 g / L of brightener, which is polypropylene glycol, is added to the cyanide-free electroplating solution to improve the surface smoothness and gloss of the main metal layer. During the electroplating process, a stirring device is used to stir at a uniform speed of 50-100 r / min to ensure the uniform concentration of the electroplating solution.

[0033] Step 4: Preparation of the antioxidant protective layer: An antioxidant protective layer is deposited on the surface of the main metal layer using electron beam evaporation. The antioxidant protective layer is a gold-palladium alloy layer, with a gold to palladium mass ratio of 9:1-9.5:0.5. The evaporation vacuum degree is controlled at 1×10⁻ 4 -5×10⁻ 4 Pa, electron beam power of 200-300W, evaporation temperature of 250-300℃, deposition thickness of 20-50nm; the anti-oxidation protective layer can effectively prevent oxidation of the main metal layer, while improving the packaging interconnect compatibility of the metal layer.

[0034] Step 5, Synergistic Annealing: The chip with deposited metal layers is placed in an annealing furnace for segmented synergistic annealing. The specific steps are as follows: First stage: Heating to 200-250℃ at a rate of 5-10℃ / min and holding for 30-40min to remove residual stress within the metal layers; Second stage: Heating to 400-450℃ at a rate of 3-5℃ / min and holding for 60-90min to promote diffusion and fusion between the metal layers, optimize the grain structure, and improve... The electrical and thermal conductivity of the metal layer is improved; in the third stage, the temperature is reduced to room temperature at a rate of 8-12℃ / min to avoid thermal stress caused by excessively rapid cooling, which could lead to cracking of the metal layer; a mixed protective gas of nitrogen and hydrogen is introduced during the annealing process, with a nitrogen to hydrogen volume ratio of 9:1, to prevent oxidation of the metal layer; the vacuum degree in the annealing furnace for synergistic annealing is controlled at 1×10⁻³-5×10⁻³Pa, and the flow rate of the mixed protective gas is 10-20sccm to ensure that the metal layer is not oxidized during the annealing process.

[0035] Step 6, Post-treatment and Detection: The annealed chip is subjected to surface polishing to remove surface burrs and defects, and the polishing accuracy is controlled within 0.1 - 0.5 μm. Subsequently, performance detection is carried out, including metal layer thickness detection, bonding force detection, electrical conductivity detection, thermal conductivity detection, and high-temperature stability detection. After passing the detection, the finished power semiconductor chip is obtained. The bonding force detection uses the cross-cut method, the cross-cut spacing is 1 mm, and after cross-cutting, tape is pasted. No metal layer peeling is qualified; the electrical conductivity detection uses the four-probe method, and the resistivity of the metal layer ≤ 1.5×10⁻ 8 Ω·m; the thermal conductivity detection uses the laser flash method, and the thermal conductivity of the metal layer ≥ 300 W / (m·K); the high-temperature stability detection is to place the chip in a high-temperature environment of 200 °C and keep it warm for 1000 h. No peeling or oxidation of the metal layer is qualified.

[0036] The specific implementation process of a method for preparing a surface metal layer of a power semiconductor chip according to the present invention is as follows:

[0037] Example 1

[0038] A method for preparing a surface metal layer of a power semiconductor chip includes the following steps:

[0039] Step 1, Chip Substrate Pretreatment: Select a SiC power semiconductor chip substrate, and perform surface cleaning, plasma etching, and interface modification treatment in sequence; Alkaline degreasing uses a sodium hydroxide solution with a mass concentration of 5%, a temperature of 50 °C, and an immersion time of 15 min; Acidic derusting uses a dilute hydrochloric acid solution with a mass concentration of 8%, a temperature of 25 °C, and an immersion time of 8 min; Rinse with deionized water 3 times, each time for 5 min; Vacuum drying temperature is 80 °C, drying time is 30 min, and vacuum degree is 5×10⁻² Pa; Plasma etching uses a mixed gas of argon and oxygen (volume ratio 9:1), etching power is 150 W, and etching time is 60 s; Interface modification treatment uses low-temperature plasma to inject titanium ions, injection energy is 50 eV, and injection dose is 1×10¹ 5 ions / cm² to form a titanium-doped transition layer.

[0040] Step 2, Preparation of Transition Metal Layer: Use the magnetron sputtering process to deposit a titanium-tantalum alloy transition layer, the mass ratio of titanium to tantalum is 7:3, and the sputtering target is a titanium-tantalum alloy target with the corresponding ratio; The vacuum degree is controlled within 5×10⁻ 4 Pa, sputtering power is 300 W, sputtering temperature is 150 °C, argon flow rate is 20 sccm, and deposition thickness is 50 nm.

[0041] Step 3: Preparation of the main metal layer: A silver-copper-tin alloy main metal layer was deposited using a cyanide-free electroplating process, with a silver, copper, and tin mass ratio of 85:10:5. The electroplating solution was a cyanide-free sulfurous acid system containing 5 g / L silver ions, 1 g / L copper ions, and 0.5 g / L tin ions. Sodium citrate (20 g / L) was added as a complexing agent, polyethylene glycol (1 g / L) as a grain refiner, and polypropylene glycol (0.1 g / L) as a brightener. The electroplating temperature was 40℃, the current density was 0.5 A / dm², the electroplating time was 60 min, and the deposition thickness was 1 μm. The mixture was stirred at a constant speed of 50 r / min during the electroplating process.

[0042] Step 4: Preparation of the antioxidant protective layer: A gold-palladium alloy antioxidant protective layer was deposited using electron beam evaporation, with a gold to palladium mass ratio of 9:1 and an evaporation vacuum degree of 1×10⁻⁻⁻⁴. 4 Pa, electron beam power of 200W, evaporation temperature of 250℃, deposition thickness of 20nm.

[0043] Step 5, Co-annealing: Place the chip in an annealing furnace, control the vacuum at 1×10⁻³Pa, and introduce a mixed protective gas of nitrogen and hydrogen (volume ratio 9:1) at a flow rate of 10 sccm; in the first stage, heat to 200℃ at a heating rate of 5℃ / min and hold for 40 min; in the second stage, heat to 400℃ at a heating rate of 3℃ / min and hold for 90 min; in the third stage, cool to room temperature at a cooling rate of 8℃ / min.

[0044] Step 6, Post-processing and Inspection: The chip surface is polished to a precision of 0.5μm; Performance test results: The total metal layer thickness is 1.12μm, no peeling was observed in the cross-cut adhesion test, and the resistivity is 1.4×10⁻ 8 The Ω·m value has a thermal conductivity of 305 W / (m·K). After being kept at 200℃ for 1000 hours, there was no peeling or oxidation, and the test was qualified.

[0045] Example 2

[0046] A method for preparing a metal layer on the surface of a power semiconductor chip includes the following steps:

[0047] Step 1: Chip Substrate Pretreatment: A GaN power semiconductor chip substrate was selected and subjected to surface cleaning, plasma etching, and interface modification treatments sequentially. Alkaline degreasing was performed using an 8% sodium hydroxide solution at 55°C for 12 minutes. Acidic rust removal was performed using a 10% dilute hydrochloric acid solution at 28°C for 6 minutes. The substrate was rinsed three times with deionized water for 5 minutes each time. Vacuum drying was carried out at 90°C for 25 minutes at a vacuum level of 3×10⁻² Pa. Plasma etching was performed using a mixture of argon and oxygen (8:2 volume ratio) at a power of 200W for 45 seconds. Interface modification was achieved by low-temperature plasma implantation of titanium ions at an energy of 80 eV and a dose of 3×10¹⁰. 5 ions / cm², forming a titanium-doped transition layer.

[0048] Step 2, Preparation of the transition metal layer: A titanium-tantalum alloy transition layer was deposited using magnetron sputtering, with a titanium to tantalum mass ratio of 7.5:2.5. The sputtering target was a titanium-tantalum alloy target with the corresponding ratio. The vacuum level was controlled at 8×10⁻⁻⁻⁶. 4 Pa, sputtering power of 350W, sputtering temperature of 180℃, argon flow rate of 25sccm, and deposition thickness of 80nm.

[0049] Step 3: Preparation of the main metal layer: A silver-copper-tin alloy main metal layer was deposited using a cyanide-free electroplating process, with a silver, copper, and tin mass ratio of 88:7:5. The electroplating solution was a cyanide-free sulfurous acid system containing 8 g / L silver ions, 1.5 g / L copper ions, and 0.8 g / L tin ions. Sodium citrate (25 g / L) was added as a complexing agent, polyethylene glycol (1.5 g / L) as a grain refiner, and polypropylene glycol (0.15 g / L) as a brightener. The electroplating temperature was 45℃, the current density was 0.8 A / dm², the electroplating time was 45 min, and the deposition thickness was 2 μm. The mixture was stirred at a constant speed of 80 r / min during the electroplating process.

[0050] Step 4: Preparation of the antioxidant protective layer: A gold-palladium alloy antioxidant protective layer was deposited using electron beam evaporation, with a gold to palladium mass ratio of 9.2:0.8 and an evaporation vacuum of 3×10⁻⁻⁻⁶. 4 Pa, electron beam power of 250W, evaporation temperature of 280℃, deposition thickness of 35nm.

[0051] Step 5, Co-annealing: Place the chip in an annealing furnace, control the vacuum at 3×10⁻³Pa, and introduce a mixed protective gas of nitrogen and hydrogen (volume ratio 9:1) at a flow rate of 15 sccm; in the first stage, heat to 220℃ at a heating rate of 8℃ / min and hold for 35 min; in the second stage, heat to 420℃ at a heating rate of 4℃ / min and hold for 75 min; in the third stage, cool to room temperature at a cooling rate of 10℃ / min.

[0052] Step 6, Post-processing and Inspection: The chip surface is polished to a precision of 0.3 μm; Performance test results: The total metal layer thickness is 2.115 μm, no detachment was observed during the cross-cut adhesion test, and the resistivity is 1.2 × 10⁻⁻⁻⁶. 8 The Ω·m value has a thermal conductivity of 320 W / (m·K). After being kept at 200℃ for 1000 hours, there was no peeling or oxidation, and the test was passed.

[0053] Example 3

[0054] A method for preparing a metal layer on the surface of a power semiconductor chip includes the following steps:

[0055] Step 1: Chip Substrate Pretreatment: Select a SiC power semiconductor chip substrate and perform surface cleaning, plasma etching, and interface modification treatments sequentially. Alkaline degreasing uses a 10% sodium hydroxide solution at 60℃ for 10 minutes. Acidic rust removal uses a 12% dilute hydrochloric acid solution at 30℃ for 5 minutes. Rinse three times with deionized water for 5 minutes each time. Vacuum drying is performed at 100℃ for 20 minutes at a vacuum level of 1×10⁻² Pa. Plasma etching uses a mixture of argon and oxygen (volume ratio 7:3) at a power of 250W for 30 seconds. Interface modification is achieved by low-temperature plasma implantation of titanium ions at an energy of 100 eV and a dose of 5×10¹⁰. 5 ions / cm², forming a titanium-doped transition layer.

[0056] Step 2, Preparation of transition metal layer: A titanium-tantalum alloy transition layer is deposited by magnetron sputtering with a titanium to tantalum mass ratio of 8:2 and a titanium-tantalum alloy target of the corresponding ratio. The vacuum degree is controlled at 1×10⁻³Pa, the sputtering power is 400W, the sputtering temperature is 200℃, the argon flow rate is 30sccm, and the deposition thickness is 100nm.

[0057] Step 3: Preparation of the main metal layer: A silver-copper-tin alloy main metal layer was deposited using a cyanide-free electroplating process, with a silver, copper, and tin mass ratio of 90:5:5. The electroplating solution was a cyanide-free sulfurous acid system containing 10 g / L silver ions, 2 g / L copper ions, and 1 g / L tin ions. Sodium citrate (30 g / L) was added as a complexing agent, polyethylene glycol (2 g / L) as a grain refiner, and polypropylene glycol (0.2 g / L) as a brightener. The electroplating temperature was 50℃, the current density was 1 A / dm², the electroplating time was 30 min, and the deposition thickness was 3 μm. The mixture was stirred at a constant speed of 100 r / min during the electroplating process.

[0058] Step 4: Preparation of the antioxidant protective layer: A gold-palladium alloy antioxidant protective layer was deposited using electron beam evaporation, with a gold to palladium mass ratio of 9.5:0.5 and an evaporation vacuum of 5×10⁻⁻⁻⁶. 4 Pa, electron beam power of 300W, evaporation temperature of 300℃, deposition thickness of 50nm.

[0059] Step 5, Co-annealing: Place the chip in an annealing furnace, control the vacuum at 5×10⁻³Pa, and introduce a mixed protective gas of nitrogen and hydrogen (volume ratio 9:1) at a flow rate of 20 sccm; in the first stage, heat to 250℃ at a heating rate of 10℃ / min and hold for 30 min; in the second stage, heat to 450℃ at a heating rate of 5℃ / min and hold for 60 min; in the third stage, cool to room temperature at a cooling rate of 12℃ / min.

[0060] Step 6, Post-processing and Inspection: The chip surface is polished to a precision of 0.1 μm; Performance test results: The total metal layer thickness is 3.15 μm, no peeling was observed in the cross-cut adhesion test, and the resistivity is 1.1 × 10⁻⁻⁻⁶. 8 The Ω·m value has a thermal conductivity of 335 W / (m·K). After being kept at 200℃ for 1000 hours, there was no peeling or oxidation, and the test was passed.

[0061] The present invention and its embodiments have been described above. This description is not restrictive. If a person skilled in the art is inspired by this description and designs a similar structure and embodiment without departing from the spirit of the present invention, such design should fall within the protection scope of the present invention.

Claims

1. A method for preparing a metal layer on the surface of a power semiconductor chip, characterized in that, Includes the following steps: Step 1: Pretreatment of chip substrate: Select the power semiconductor chip substrate to be prepared with metal layer, and perform surface cleaning, plasma etching and interface modification treatment in sequence; Step 2, Transition Metal Layer Preparation: A titanium-tantalum alloy transition layer is deposited on the pretreated chip substrate surface using magnetron sputtering. The mass ratio of titanium to tantalum is 7:3-8:2, and the sputtering vacuum is 5×10⁻⁶. -4 -1×10 -3 Pa, sputtering power of 300-400W, sputtering temperature of 150-200℃, and deposition thickness of 50-100nm; Step 3: Preparation of the main metal layer: A silver-copper-tin alloy main metal layer is deposited on the surface of the transition metal layer using a cyanide-free electroplating process. The mass ratio of silver, copper, and tin is 85:10:5-90:5:

5. The electroplating solution uses a cyanide-free sulfurous acid system, the electroplating temperature is 40-50℃, and the current density is 0.5-1 A / dm³. 2 The deposition thickness is 1-3 μm; Step 4: Preparation of the antioxidant protective layer: A gold-palladium alloy antioxidant protective layer is deposited on the surface of the host metal layer using electron beam evaporation. The mass ratio of gold to palladium is 9:1-9.5:0.5, and the evaporation vacuum degree is 1×10⁻⁶. -4 -5×10 -4 Pa, with a deposition thickness of 20-50 nm; Step 5, Co-annealing: The chip with the deposited metal layer is placed in an annealing furnace for segmented co-annealing, which goes through three stages in sequence: heating and holding, high temperature holding, and cooling. A mixture of nitrogen and hydrogen protective gas is introduced during the annealing process. Step 6, Post-processing and Inspection: The annealed chip is surface polished, and then its performance is tested. The finished product is obtained after passing the test.

2. The method for preparing a surface metal layer of a power semiconductor chip according to claim 1, characterized in that: In step 1, the surface cleaning adopts a step-by-step process of alkaline degreasing, acidic rust removal, deionized water rinsing, and vacuum drying; the plasma etching adopts a mixed gas of argon and oxygen, with an etching power of 150-250W and an etching time of 30-60s. The interface modification treatment employs low-temperature plasma implantation technology to implant titanium ions into the substrate surface at an implantation energy of 50-100 eV and an implantation dose of 1 × 10⁻⁶ eV. 15 -5×10 15 ions / cm 2 。 3. The method for preparing a surface metal layer of a power semiconductor chip according to claim 2, characterized in that: In step 1, the alkaline degreasing uses a 5%-10% sodium hydroxide solution at a temperature of 50-60℃ for 10-15 minutes; the acidic rust removal uses an 8%-12% dilute hydrochloric acid solution at a temperature of 25-30℃ for 5-8 minutes; and the vacuum drying temperature is 80-100℃ for 20-30 minutes, with a vacuum degree of 1×10⁻⁶. -2 -5×10 -2 Pa.

4. The method for preparing a surface metal layer of a power semiconductor chip according to claim 3, characterized in that: In step 3, the cyanide-free electroplating solution contains silver ions at a concentration of 5-10 g / L, copper ions at a concentration of 1-2 g / L, and tin ions at a concentration of 0.5-1 g / L. Sodium citrate is added as a complexing agent, polyethylene glycol as a grain refiner, and 0.1-0.2 g / L of polypropylene glycol can also be added as a brightener.

5. The method for preparing a surface metal layer of a power semiconductor chip according to claim 4, characterized in that: In step 5, the specific parameters of the synergistic annealing treatment are as follows: In the first stage, the temperature is increased to 200-250℃ at a heating rate of 5-10℃ / min and held for 30-40 min; in the second stage, the temperature is increased to 400-450℃ at a heating rate of 3-5℃ / min and held for 60-90 min; in the third stage, the temperature is decreased to room temperature at a cooling rate of 8-12℃ / min; the vacuum degree inside the annealing furnace is 1×10⁻⁶. -3 -5×10 -3 Pa, the volume ratio of nitrogen to hydrogen in the mixed protective gas is 9:1, and the flow rate is 10-20 sccm.

6. The method for preparing a surface metal layer of a power semiconductor chip according to claim 5, characterized in that: In step 6, the surface polishing precision is controlled within 0.1-0.5 μm; the performance testing includes metal layer thickness testing, adhesion testing, electrical conductivity testing, thermal conductivity testing, and high-temperature stability testing, wherein the adhesion is tested using the cross-cut test with no detachment, and the resistivity is ≤1.5×10⁻⁶. -8 Ω·m, thermal conductivity ≥300W / (m·K), no peeling or oxidation after 1000h high temperature insulation at 200℃.

7. The method for preparing a surface metal layer of a power semiconductor chip according to claim 1, characterized in that: The power semiconductor chip substrate is a SiC substrate or a GaN substrate.