Method of forming a silicon-on-insulator substrate

Abstract

The present disclosure relates to methods of forming silicon-on-insulator substrates. A method of forming an SOI substrate includes performing a hydrogen thermal treatment on a pretreated sacrificial wafer at an elevated temperature. A stop layer and a semiconductor layer can be sequentially formed on a first surface of the sacrificial wafer on which the hydrogen (H2) thermal treatment was performed. The stop layer and the semiconductor layer can be formed by an epitaxial growth process using a hybrid precursor including monosilane (MS) and dichlorosilane (DCS) sources.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0170621, filed on November 26, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure generally relate to a method of forming a silicon-on-insulator (SOI) substrate, and more specifically, to a method of forming an SOI substrate capable of reducing leakage current in the channel. Background Technology

[0004] A unit storage cell of a storage device may include at least one unit transistor and at least one storage element. For example, a unit storage cell of dynamic random access memory (DRAM) may use a capacitor as a storage element.

[0005] As the density requirements of memory devices increase, several technical challenges have emerged, such as achieving sufficient capacitance in DRAM due to the reduction in the area of ​​a single memory cell. Therefore, vertical memory cells were proposed.

[0006] Silicon-on-insulator (SOI) substrates can be used for transistor structures in vertical memory cells. An SOI substrate may include a layer of semiconductor material (e.g., silicon) separated from the wafer by an insulating layer, and the semiconductor material layer of the SOI substrate can act as a channel when forming the cell transistor.

[0007] However, the channels (e.g., semiconductor layers) in SOI substrates used in vertical memory cells may be in a floating state, and therefore may suffer from high leakage current characteristics. Therefore, this technology requires further improvement to achieve wider practical applications. Summary of the Invention

[0008] Embodiments of this disclosure provide a method for forming an SOI substrate with a semiconductor layer having improved leakage current characteristics.

[0009] According to embodiments of this disclosure, a method for forming an SOI substrate is provided. The method includes performing a hydrogen (H2) heat treatment on a pretreated sacrificial wafer at a high temperature. A stop layer and a semiconductor layer can be sequentially formed on a first surface of the sacrificial wafer after the hydrogen heat treatment. The stop layer and semiconductor layer can be formed by an epitaxial growth process using a mixed precursor comprising a monosilane (MS) source and a dichlorosilane (DCS) source.

[0010] According to embodiments of this disclosure, a method for forming an SOI substrate is provided. The method includes: performing hydrogen thermal treatment on a pre-treated sacrificial wafer at a high temperature; forming a stop layer on the sacrificial wafer after the hydrogen thermal treatment; forming a semiconductor layer on the stop layer, forming a barrier oxide layer on the semiconductor layer; and forming a first bonding insulating layer on the barrier oxide layer to form a first structure. The stop layer and the semiconductor layer are formed by an epitaxial growth method.

[0011] According to various embodiments, the pretreatment process may include a cleaning process and a drying process for the sacrificial wafer before forming the stop layer and the semiconductor layer on the sacrificial wafer. Therefore, crystal defects caused by oxide impurities in the stop layer and semiconductor layer formed during subsequent epitaxial processes can be prevented.

[0012] Furthermore, in the hydrogen (H2) heat treatment that forms the stop layer and semiconductor layer on the sacrificial wafer, residues (e.g., residual oxygen) on the sacrificial wafer can be completely removed, and Si migration can occur on the sacrificial wafer from which residues can be completely removed, thereby improving the roughness of the sacrificial wafer.

[0013] Furthermore, by using a monosilane (MS) source and a dichlorosilane (DCS) source as precursors to form a stop layer (e.g., a SiGe layer) and a semiconductor layer (e.g., a Si layer), SiGe / Si grain growth can be prevented by the chloride (Cl) ions, which have etching properties, generated during the decomposition of the DCS source. Additionally, the leakage current characteristics of the memory device can be improved by reducing crystal defects through improved roughness at the boundary between the SiGe and Si layers and by reducing Si dangling bonds. Attached Figure Description

[0014] The above and other aspects, features, and advantages of the subject matter of this disclosure will be more readily understood from the following detailed description, taken in conjunction with the accompanying drawings, wherein:

[0015] Figures 1 to 7 This is a cross-sectional view illustrating a method for forming an SOI substrate according to an embodiment of the present disclosure. Detailed Implementation

[0016] The advantages and features of the embodiments of this disclosure, as well as methods of implementing them, will become apparent when the embodiments are described in detail with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed herein, and embodiments may be embodied in many different forms. The embodiments are provided to complete this disclosure and to enable those skilled in the art to fully understand the technical concept and scope of the embodiments as defined by the claims. For clarity, the dimensions and relative sizes of layers and regions in the figures may be enlarged. Throughout the specification, the same reference numerals may refer to the same components.

[0017] Figures 1 to 7 This is a cross-sectional view illustrating a method for forming an SOI substrate according to an embodiment of the present disclosure.

[0018] refer to Figure 1 The device may provide a sacrificial wafer 110 and a reference wafer 120. For example, the sacrificial wafer 110 and the reference wafer 120 may include at least one material selected from silicon (Si), germanium (Ge), silicon carbide (SiC), group IV-IV, group III-V or group II-VI semiconductor compounds and piezoelectric materials (e.g., LiNbO3, LiTaO3, etc.).

[0019] In various embodiments, the sacrificial wafer 110 may undergo a pretreatment process. The pretreatment process for the sacrificial wafer 110 may include a cleaning process to remove native oxides and organic materials from the sacrificial wafer 110. The pretreatment process for the sacrificial wafer 110 may also include a drying process to prevent oxide regrowth from the sacrificial wafer 110. For example, the sacrificial wafer 110 may include a polished surface. Pretreatment may be performed on the polished surface of the sacrificial wafer 110.

[0020] In some embodiments, the cleaning process for the sacrificial wafer 110 can be performed using hydrofluoric acid (HF) diluted in water. This process is referred to as the diluted HF (DHF) cleaning process. For example, the DHF cleaning process for the sacrificial wafer 110 can be performed using hydrofluoric acid (HF) diluted in deionized water (DI water, DIW) to a ratio of 100:1 to 200:1. Furthermore, the drying process for the sacrificial wafer 110 can be performed using nitrogen (N2).

[0021] As described above, by sacrificing the preprocessing process of wafer 110, it is possible to prevent damage due to the stop layer 111 (see above). Figure 2 ) and semiconductor layer 112 (see Figure 2 Crystal defects caused by oxide impurities in the crystal are formed through subsequent epitaxial processes.

[0022] Now for reference Figure 2 A stop layer 111 and a semiconductor layer 112 can be formed on a first surface (e.g., the top surface) of the sacrificial wafer 110. For example, the first surface of the sacrificial wafer 110 can be a surface that has undergone pretreatment. Furthermore, the sacrificial wafer 110 may include a second surface opposite to the first surface. In some embodiments, the stop layer 111 and the semiconductor layer 112 can be formed by epitaxial growth using in-situ techniques.

[0023] In some embodiments, the pre-processed sacrificial wafer 110 can be subjected to hydrogen (H2) heat treatment at a high temperature before forming the stop layer 111. For example, the hydrogen heat treatment of the sacrificial wafer 110 can be performed at a high temperature of 900°C to 1,200°C. In this way, as the high-temperature (i.e., 900°C to 1,200°C) H2 heat treatment of the sacrificial wafer 110 is performed, silicon (Si) migration can be generated on the surface of the sacrificial wafer 110, thereby improving the surface roughness of the sacrificial wafer 110. In addition, since oxide impurities on the surface of the sacrificial wafer 110 are removed by hydrogen heat treatment (or H2 baking), crystal defects can be reduced, which in turn improves the leakage current characteristics of the memory device.

[0024] The stop layer 111 prevents the loss of the semiconductor layer 112 when the sacrificial wafer 110 is removed in subsequent processes. The stop layer 111 can be formed using a material with a different etch selectivity than the sacrificial wafer 110 and the semiconductor layer 112. Alternatively, the stop layer 111 can be formed using a material with fewer physical differences from the semiconductor layer 112. In various embodiments, the stop layer 111 can be a single-crystal silicon-germanium (SiGe) layer.

[0025] In some embodiments, the stop layer 111 can be formed by an epitaxial growth process. The epitaxial growth process can be performed using a mixed precursor having a monosilane (MS:SiH4) source and a dichlorosilane (DCS:SiH2Cl2) source as the source gas, and a reaction gas at 600°C to 800°C. For example, the reaction gas may include germanium tetrahydrodehydride (GeH4). The partial pressure ratio of the monosilane (MS) source to the dichlorosilane (DCS) source gas can be 3:1.

[0026] Since the chloride (Cl) ions generated during the DCS source decomposition of the source gas can have etching properties, the roughness of the stop layer 111 (i.e., SiGe) can be improved, and the Si dangling bonds in the stop layer 111 can be reduced. As a result, crystal defects caused by the roughness of the stop layer 111 and the Si dangling bonds in the stop layer 111 can be reduced, and the leakage current characteristics of the memory device can be improved.

[0027] For example, when a stop layer 111 (e.g., a SiGe layer) is formed via an epitaxial growth process, island-like growth may occur due to compressive stress caused by the lattice mismatch between the Si material of the sacrificial wafer 110 and the SiGe layer of the stop layer 111. The roughness characteristics of the SiGe layer may deteriorate due to the occurrence of island-like growth. As a result, the sharpness characteristics between the Si layer (i.e., semiconductor layer 112) and the SiGe layer (i.e., stop layer 111) may deteriorate during the epitaxial growth process used to form the semiconductor layer 112. Furthermore, the formation of island-like growth may increase Si dangling bonds, which could degrade the electrical properties of the memory device.

[0028] In various embodiments, by employing a mixed precursor of MS and DCS sources as the Si source gas, after the Si epitaxial reaction, protruding Si adsorbed on the sacrificial wafer 110 can be removed by Cl ions decomposed from the DCS source, where silicon ions are adsorbed on the sacrificial wafer 110. As a result, island growth can be reduced during the epitaxial growth process used to form the stop layer 111 and the semiconductor layer 112. The roughness characteristics of the SiGe layer (i.e., stop layer 111) and the sharpness characteristics of the bonding interface between the stop layer 111 and the semiconductor layer 112 can be improved, and Si dangling bonds can be reduced. Since the surface roughness and sharpness characteristics of the SiGe layer are improved, the surface roughness characteristics of the semiconductor layer 112 can be improved when the stop layer 111 is removed in a subsequent process, thereby eliminating the need for chemical mechanical polishing (CMP) processes and finishing processes for the semiconductor layer 112.

[0029] In various embodiments, the stop layer 111 may have a germanium (Ge) concentration of 10% to 30%. The thickness of the stop layer 111 can range from [missing information]. to But it is not limited to this.

[0030] In some embodiments, after the stop layer 111 is formed, a purging process can be performed using hydrogen. During the purging process, residual gases in the chamber can be removed, and defects on the surface of the stop layer 111, such as Si dangling bonds, can be removed by hydrogen (H2) passivation.

[0031] Refer again Figure 2 Semiconductor layer 112 can be formed on stop layer 111. For example, semiconductor layer 112 can be a single crystal silicon (Si) layer.

[0032] In some embodiments, the semiconductor layer 112 can also be formed by an epitaxial growth process at 600°C to 800°C using a mixed precursor comprising a compound of MS and DCS. For example, the voltage ratio of MS to DCS can be 3:1. As described above, chloride (Cl) ions generated during the decomposition of the DCS source of the source gas used to form the semiconductor layer 112 can contribute to etching characteristics, Si grain growth, Si roughness, and can reduce crystal defects caused by Si grain growth and Si roughness, and can improve the leakage current characteristics of the memory device.

[0033] As described above, in various embodiments, when the semiconductor layer 112 is formed from a compound including a DCS source and an MS source, protrusions on the surface of the semiconductor layer 112 can be removed by Cl decomposed from the DCS source. As a result, island growth and Si dangling bonds in the semiconductor layer 112 can be reduced, thereby improving the surface roughness characteristics of the semiconductor layer 112.

[0034] refer to Figure 3 A barrier oxide layer 113 can be formed on the semiconductor layer 112, and a first bonding insulating layer 114 can be formed on the barrier oxide layer 113.

[0035] In some embodiments, the barrier oxide layer 113 may include a silicon oxide (SiO2) layer or a silicon oxynitride (SiON) layer, but the embodiments are not particularly limited thereto.

[0036] Next, a reference wafer 120 may be provided. A second bonding insulating layer 124 may be formed on the reference wafer 120. In various embodiments, the first bonding insulating layer 114 and the second bonding insulating layer 124 may be formed simultaneously in the same chamber or simultaneously in different chambers. However, embodiments are not particularly limited to this approach.

[0037] In some embodiments, the first bonding insulating layer 114 and the second bonding insulating layer 124 may include silicon carbonitride (SiCN) layers, but the embodiments are not particularly limited thereto.

[0038] When the first bonding insulating layer 114 and the second bonding insulating layer 124 have been formed, a first structure A including a sacrificial wafer 110 and a stop layer 111, a semiconductor layer 112, a barrier oxide layer 113 and the first bonding insulating layer 114, and a second structure B including a reference wafer 120 and the second bonding insulating layer 124 can be prepared.

[0039] refer to Figure 4 The first structure A and the second structure B can be bonded together, allowing the first bonding insulating layer 114 and the second bonding insulating layer 124 to contact. In various embodiments, the bonding of the first structure A and the second structure B may include a melt bonding process performed at the interface between the first bonding insulating layer 114 and the second bonding insulating layer 124. The melt bonding process may be performed, for example, at room temperature. After the melt bonding process, an annealing process may be performed to strengthen the bonding at the interface between the first bonding insulating layer 114 and the second bonding insulating layer 124. For example, the annealing process may be performed using nitrogen (N2) at a temperature of 400°C to 650°C.

[0040] like Figure 4 As shown, after flipping the first structure A, the flipped first structure A can be bonded to the second structure B, and the second surface of the sacrificial wafer 110 of the first structure A can be exposed.

[0041] refer to Figure 5 The exposed sacrificial wafer 110 can be trimmed to remove selected portions of the edge of the sacrificial wafer 110 (hereinafter referred to as trimming process).

[0042] refer to Figure 6 The exposed sacrificial wafer 110 can be ground to a predetermined thickness (or height). In some embodiments, the remaining sacrificial wafer 110R may include a thickness of about 3 μm, but the embodiments are not particularly limited thereto. When the sacrificial wafer 110 is ground, cracking and fragmentation of the sacrificial wafer 110 can be reduced through the trimming process of the sacrificial wafer 110.

[0043] refer to Figure 7 The remaining sacrificial wafer 110R and stop layer 111 can be removed sequentially to form SOI substrate 100.

[0044] In various embodiments, at least one of wet cleaning processes and dry cleaning processes can be used to remove the remaining sacrificial wafer 110R. For example, the remaining sacrificial wafer 110R can be removed by sequentially performing a DHF (diluted HF) pretreatment cleaning process and a wet alkaline (diluted NH4OH, TMAH:(CH3)4N(OH) or KOH) posttreatment cleaning process, followed by a drying process in an IPA (isopropanol) dryer.

[0045] Furthermore, in some embodiments, at least one of a wet cleaning process and a dry cleaning process can be used to remove the stop layer 111. For example, a wet alkaline cleaning process (diluted NH4OH, TMAH:(CH3)4N(OH), KOH, etc.) and a dry cleaning process using fluorinated compounds can be used to remove the stop layer 111.

[0046] SOI substrate 100 may include a second bonding insulating layer 124, a first bonding insulating layer 114, a barrier oxide layer 113, and a semiconductor layer 112 sequentially stacked on reference wafer 120.

[0047] The surface of the semiconductor layer 112 can be exposed by removing the stop layer 111. A cleaning process can also be performed to improve the roughness of the exposed surface of the semiconductor layer 112.

[0048] Although embodiments of the present disclosure have been described in detail with reference to certain examples, the present disclosure is not limited to the embodiments described above. Modifications to the embodiments can be made by those skilled in the art, and any modifications should be considered to fall within the scope of the present disclosure. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A method for forming an SOI substrate, SOI referring to silicon-on-insulator, the method comprising: The pre-treated sacrificial wafers were subjected to hydrogen heat treatment at high temperatures; A stop layer is formed on the sacrificial wafer that has undergone the hydrogen heat treatment; as well as A semiconductor layer is formed on the stop layer. The stop layer and the semiconductor layer are formed by an epitaxial growth process using a hybrid precursor, which includes an MS source and a DCS source, where MS is monosilane and DCS is dichlorosilane.

2. The method according to claim 1, wherein, The pretreated sacrificial wafer is formed through the following steps: A cleaning process is performed to remove native oxides and organic materials from the polished wafer; as well as A drying process is performed to prevent oxide regrowth on the cleaned wafer.

3. The method according to claim 2, wherein, The cleaning process is performed using a cleaning solution comprising hydrofluoric acid HF diluted in deionized water to a ratio of 100:1 to 200:

1.

4. The method according to claim 2, wherein, The drying process is performed under nitrogen (N2) atmosphere.

5. The method according to claim 1, wherein, The molar ratio of the monosilane source and the dichlorosilane source in the mixed precursor is 3:

1.

6. The method according to claim 1, wherein, The stop layer comprises single-crystal silicon germanium (SiGe), and The stop layer is formed by providing germanium tetrahydrogenate (GeH4) as a reactant gas.

7. The method according to claim 6, wherein, The stop layer is formed to have a germanium (Ge) concentration of 10% to 30%, and The thickness of the stop layer includes to 8. The method according to claim 1, further comprising: A purging process is performed using hydrogen gas before the semiconductor layer is formed on the stop layer.

9. The method according to claim 1, further comprising: A barrier oxide layer is formed on the semiconductor layer; as well as A first bonded insulating layer is formed on the barrier oxide layer to form a first structure.

10. The method of claim 9, further comprising: A second bonding insulating layer is formed on a reference wafer to form a second structure.

11. The method of claim 10, further comprising: The first structure and the second structure are bonded together such that the first bonding insulating layer of the first structure and the second bonding insulating layer of the second structure face each other to form the SOI substrate.

12. The method according to claim 11, wherein, Bonding the first structure to the second structure includes: At room temperature, fusion bonding is performed at the interface between the first bonded insulating layer and the second bonded insulating layer; and The SOI substrate is annealed to enhance the bonding at the interface between the first bonding insulating layer and the second bonding insulating layer.

13. The method of claim 11, further comprising: The edge portion of the sacrificial wafer in the first structure is removed using a wafer trimming process; as well as The sacrificial wafer is ground to form a residual sacrificial wafer layer with a set thickness on the stop layer.

14. The method of claim 13, further comprising: The remaining sacrificial wafer layer is removed using a wet cleaning process to expose the stop layer; as well as The exposed stop layer is removed using a dry cleaning process to expose the semiconductor layer.

15. The method of claim 14, further comprising: The surface of the exposed semiconductor layer is cleaned using a wet cleaning process.

16. A method for forming an SOI substrate, SOI referring to silicon-on-insulator, the method comprising: The pre-treated sacrificial wafers were subjected to hydrogen heat treatment at high temperatures; A stop layer is formed on the sacrificial wafer after the hydrogen heat treatment; A semiconductor layer is formed on the stop layer; A barrier oxide layer is formed on the semiconductor layer; as well as A first bonded insulating layer is formed on the barrier oxide layer to form a first structure. The stop layer and the semiconductor layer are formed by an epitaxial growth method.

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