A pixel structure for an anti-radiation 4T CMOS image sensor and a working method thereof

Abstract

This invention provides a pixel structure and its operating method for a radiation-hardened 4T CMOS image sensor. The pixel structure includes a transmission transistor, a reset transistor, a source follower, a row select transistor, an STI bias gate, a photodiode, a floating node, a shallow trench isolation region, and a P-type substrate. The photodiode is surrounded by a P-type substrate, which is enclosed by the shallow trench isolation region. A portion of the shallow trench isolation region is covered by an STI bias gate. The lower right corner of the photodiode is connected to one side of the transmission transistor, and the other side of the transmission transistor is connected to the floating node. The reset transistor, row select transistor, and source follower are sequentially connected after the floating node. The negative bias V of the STIX designed in this invention... STI negative bias V with TX TX The shutdown voltage effectively improves the radiation resistance of the device by suppressing the generation of interface state trap charges at the STI-pixel interface and the generation of dark current in the TX-PD overlap region under the TID effect.

Description

Technical Field

[0001] This invention relates to the field of radiation-resistant CMOS image sensor technology, and in particular to a pixel structure and its working method for a radiation-resistant 4T CMOS image sensor. Background Technology

[0002] CMOS image sensors offer advantages such as small size, high integration, low power consumption, and fast response speed, meeting the needs of security surveillance systems, mobile phone photography, machine vision, autonomous driving in automobiles, and medical electronics. Simultaneously, CMOS image sensors are also widely used in space-based applications such as space-based visual monitoring systems, star sensors, and Earth observation.

[0003] However, the protons, electrons, and gamma rays in the harsh space radiation environment can produce total ionizing dose (TID) and displacement effects in on-orbit CMOS image sensors, causing permanent damage to the image sensors, resulting in decreased sensor imaging performance, shortened lifespan, and posing a serious threat to the on-orbit operation of spacecraft.

[0004] Currently, there are many new pixel structure designs for CMOS image sensors based on the traditional 4T structure. However, most of these designs focus on high dynamic range, high-speed image acquisition, low power consumption, large full-well capacity, and low noise, with few addressing radiation hardening techniques, such as: Patent CN112614862B describes a novel pixel structure for a CMOS image sensor. It designs the photodiode as a hollow ring structure, increasing the area of ​​the photosensitive region of the photodiode without affecting the charge transfer speed of the transfer transistor. While maintaining the same maximum distance of charge from the floating diffusion node, it increases the area of ​​the photosensitive region of the photodiode, improving the full-well capacity and achieving better image quality. This patent does not involve radiation hardening. Patent CN103873787B, High Dynamic Range Image Sensor Pixel, on a 5T structure of 4T pixels plus High Dynamic Range (HDR) control transistor, limits the gate area of ​​the HDR transistor, eliminates parasitic capacitance, saves pixel area, improves fill factor, and enhances quantum efficiency, but does not involve the field of radiation hardening.

[0005] To extend the on-orbit lifespan of CMOS image sensors, radiation-hardened designs are implemented for the pixel structure. Existing solutions mainly include: Patent CN103152531B describes an active pixel structure for a radiation-hardened CMOS image sensor. This patent introduces a compensation signal circuit within the pixel unit. When the pixel is affected by the total ionizing dose (TID) effect, the significantly increased dark current is eliminated by enhancing the compensation signal. However, this method leads to increased static power consumption, and each pixel unit requires an additional transistor and independent control signal, significantly reducing the fill factor.

[0006] Patent CN104157659B discloses a crosstalk isolation and radiation-hardened pixel structure for a radiation detector and its fabrication method. This patent utilizes silicon-on-insulator (SOI) technology and an air-gap structure to prevent the diffusion of the bottom potential into the bulk region of the top-layer metal-oxide-semiconductor field-effect transistor (MOSFET), effectively shielding radiation-induced charges generated by the total ionization dose (TID) effect in the insulating medium, while suppressing the formation of interface state trap charges. However, the excessively large air-gap layer increases the fabrication difficulty, causing this design to remain only at the theoretical level at present. Furthermore, the reserved air gap actually requires a sufficiently high gate control voltage, thereby increasing the device's power consumption.

[0007] Traditional 4T CMOS image sensor pixel structure, such as Figure 1 , Figure 2 As shown, the structure includes a photodiode (PD) and four MOS transistors: a transmission transistor (TX), a reset transistor (RST), a source follower (SF), a row select transistor (SEL), a photodiode (PD), a floating node (FD), a shallow trench isolation region (STI), and a P-type substrate. Summary of the Invention

[0008] The purpose of this invention is to provide a pixel structure and its working method for a radiation-resistant 4T CMOS image sensor. Without changing the pixel structure manufacturing process or increasing the difficulty of chip manufacturing, this invention solves the problem of increased pixel dark current caused by the TID effect in the harsh space radiation environment, and extends the on-orbit service life by controlling the changes in pixel timing and pixel structure during the process.

[0009] To solve the above-mentioned technical problems, the technical solution of the present invention is: to provide a pixel structure for a radiation-resistant 4T CMOS image sensor, including a transmission transistor, a reset transistor, a source follower, a row select transistor, an STI bias gate, a photodiode, a floating node, a shallow trench isolation region, and a P-type substrate; The photodiode is surrounded by a P-type substrate, which is enclosed by the shallow trench isolation region. Part of the shallow trench isolation region is covered with an STI bias gate. The lower right corner of the photodiode is connected to one side of the transmission tube, and the other side of the transmission tube is connected to the floating node. The floating node is connected in sequence to the reset tube, the row select tube, and the source follower. The photon signal enters the photodiode, generating photoelectrons in the N-type depletion layer, and is initially stored in the photodiode. By turning on the reset transistor, the floating node potential is pulled up to Vdd. After the transmission transistor is turned on, due to the high floating node potential, the photoelectrons are transmitted from the photodiode to the source follower through the transmission transistor. After the row select transistor is turned on, the voltage signal is converted into a current signal output through the source follower, ultimately realizing the conversion of optical signal to electrical signal. The STI bias gate applies a negative voltage bias to the STI region, which plays a role in radiation hardening.

[0010] Another technical solution of the present invention provides a method for operating the pixel structure of the above-mentioned radiation-resistant 4T CMOS image sensor, comprising the following steps: Step S1: After the device is powered on at time t0, and before time t1, the STI bias gate is negatively biased by V. STI To suppress the increase in dark current at the STI interface defects caused by the TID effect; apply a negative bias V to the transmission transistor. TX To suppress the increase in TX-PD overlap current caused by the TID effect; apply a positive bias V to the horizontal select transistor. SEL The pixel output gating is turned on. Output is achieved; the reset transistor is positively biased V. RST Make the floating node potential V FD The electrons that were originally present in the floating node are pulled up to Vdd. In step S2, during the time interval t1~t2, the reset transistor is removed from the positive bias, and the floating node potential is no longer locked at Vdd. The input sampling signal SH1 is used to sample the pixel output voltage at this time, which is recorded as the reset voltage.

[0011] In step S3, during the time interval t2~t3, a positive bias V is applied to the transmission tube. TX The light signal originally collected in the photodiode region generates electrons, which are then transmitted to the floating node region through the open transmission tube. The floating node potential V FD As the signal charge gradually decreases, the floating node potential V decreases after the signal charge has been completely transferred to the floating node region. FD No longer changing; In step S4, during the time interval t3~t4, after the signal stabilizes, apply a negative bias V. TX After the transmission transistor is turned off, the sampling signal SH2 is input, and the output voltage of the pixel at this time is read and recorded as . ; Step S5: Subtract the two output voltages of the pixel to obtain the signal voltage. This achieves true correlated double sampling in the circuit, eliminating pixel KBTC noise and fixed-pattern noise.

[0012] in It is the gain of the source follower SF transistor.

[0013] Furthermore, in step S1, a negative bias V is applied to the STI bias gate. STI Subsequently, holes move directionally toward the surface polysilicon gate STIX; during the movement, holes form positively charged radiation-induced oxide trap charges, moving away from the shallow trench isolation region and the SiO2 / Si interface of the pixel.

[0014] Furthermore, The value range is 0.8 to 0.9.

[0015] The beneficial effects of the pixel structure and its working method for a radiation-resistant 4T CMOS image sensor provided by this invention are as follows: 1. The negative bias V of the STIX designed in this invention STI negative bias V with TX TX The shutdown voltage effectively improves the radiation resistance of the device by suppressing the generation of interface state trap charges at the STI-pixel interface and the generation of dark current in the TX-PD overlap region under the TID effect. 2. The radiation-resistant pixel of the present invention relies on the existing CMOS process and mainly adjusts the voltage on the internal polysilicon gate as an effective radiation-resistant control strategy. The method is highly executable, has low migration and application costs, and has broad application prospects. 3. The imaging process of the present invention only requires the addition of one or two negative voltage power supplies. While improving the anti-radiation performance, it does not need to sacrifice the advantages of the traditional 4T CMOS image sensor pixel structure, such as high fill factor, low power consumption, and large full-well capacity. Attached Figure Description

[0016] The invention will be further described below with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the pixel structure of a traditional 4T CMOS image sensor in the background technology; Figure 2 The background section describes the pixel layout of a traditional 4T CMOS image sensor. Figure 3 A pixel layout for a pixel structure used in a radiation-resistant 4T CMOS image sensor; Figure 4 This is a timing diagram of a pixel operation method for a radiation-resistant 4T CMOS image sensor; Figure 5 The pixel dark current before and after irradiation varies with the negative bias voltage V of the transmission gate. TG-L The change curve. Detailed Implementation

[0017] The pixel structure and its operation method for a radiation-resistant 4T CMOS image sensor proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0018] This invention provides a pixel structure for a radiation-resistant 4T CMOS image sensor, as shown below. Figure 3 As shown, the circuit includes a transmission transistor (TX), a reset transistor (RST), a source follower (SF), a row select transistor (SEL), a bias gate (STIX) for a shallow trench isolation region (STI), a photodiode (PD), a floating node (FD), a shallow trench isolation region (STI), and a P-type substrate. The photodiode (PD) is surrounded by a P-type substrate, which is enclosed by a shallow trench isolation region (STI). A portion of the shallow trench isolation region (STI) is covered by the STI bias gate (STIX). The lower right corner of the photodiode (PD) is connected to one side of the transmission transistor (TX), and the other side of the transmission transistor (TX) is connected to the floating node (FD). Following the floating node (FD) are the reset transistor (RST), the row select transistor (SEL), and the source follower (SF).

[0019] The photon signal enters the photodiode (PD) and generates photoelectrons in the N-type depletion layer, which are initially stored in the PD. By turning on the RST transistor, the floating node (FD) potential is pulled up to Vdd. After the transmission transistor (TX) is turned on, due to the high potential of the floating node (FD), the photoelectrons are transmitted from the photodiode (PD) through the transmission transistor (TX) to the source follower (SF). After the row select transistor (SEL) is turned on, the voltage signal is converted into a current signal output through the source follower (SF), ultimately realizing the conversion from optical signal to electrical signal. The STI bias gate (STIX) applies a negative voltage bias to the STI region, providing radiation hardening.

[0020] The pixel operation method for a radiation-resistant 4T CMOS image sensor provided by this invention is as follows: After the device is powered on at time t0 and before time t1, STIX is negatively biased by V. STI This suppresses the increase in dark current caused by STI interface defects due to the TID effect. A negative bias is applied to the TX transistor. TX This suppresses the increase in TX-PD overlap current caused by the TID effect. A positive bias V is applied to the SEL transistor. SEL The pixel output gate is turned on, allowing Vpixel-out to be output. A positive bias V is applied to the RST transistor. RST This makes the floating node FD potential VFD The electrons that were originally present in the floating node FD are pulled up to Vdd. During the time interval t1~t2, the RST transistor is first removed from the positive bias, and the potential of the floating node FD is no longer locked at Vdd. Then, a sampling signal SH1 is applied to sample the pixel output voltage at this time, which is recorded as the reset voltage V. reset ; During the time interval t2~t3, the TX transistor is positively biased by V. TX The optical signal originally collected in the PD region generates electrons, which are then transmitted to the FD region through the opened TX transistor, and the floating node FD potential V is set. FD As the signal charge gradually decreases, once the signal charge has completely transferred to the FD region, the floating node FD potential V... FD No longer changing; During the time interval t3~t4, after the signal stabilizes, apply a negative bias V. TX After the TX transistor is turned off, another sampling signal SH2 is applied, and the output voltage of the pixel at this time is read and recorded as Vsignal; Subtracting the two pixel output voltages yields the signal voltage Vpixel-out, achieving true correlated double sampling (CDS) and eliminating pixel KBTC noise and fixed-pattern noise (FPN). This process can be represented by the following equation: (Formula 1) In the formula, Gpixel is the gain of the source follower SF transistor, which is usually between 0.8 and 0.9.

[0021] Pixel dark current refers to the current spontaneously generated by the pixel under unexposed conditions due to the presence of various defects (interface defects and bulk defects), which is then absorbed by the depletion region. It mainly originates from the intrinsic reverse bias current of the bulk PN junction, the current generated by STI interface defects, the current generated by PPD surface defects, and the current generated in the TX-PD overlap region. Under the TID effect, the dark current generated by STI interface defects and the dark current in the TX-PD overlap region together lead to an increase in pixel dark current.

[0022] For dark current defects at the STI interface, as pixel size decreases, the STI area shrinks accordingly, making it increasingly easy to form voids when filling its trenches. To ensure dense filling, high-energy high-density plasma deposition (HDP) of SiO2 is generally used. This subjectes the SiO2-Si interface to more severe bombardment than traditional processes, making it more prone to broken dangling bonds and interface defects. Under the TID effect, a large number of electron-hole pairs are generated in the STI and gate oxide SiO2 due to the ionization deposition of incident ions. Under the applied bias electric field, electrons move towards the polysilicon gate, and holes move towards the N-type buried trench. Since the electron mobility in SiO2 is much higher than that of holes, electrons are typically swept out of SiO2 by the electric field within 1 ps, while holes gradually move towards the SiO2 / Si interface under the influence of the electric field and thermal motion. During their movement, some holes are captured by oxygen vacancy traps in the SiO2 layer and become positively charged radiation-induced oxide trap charges. Other holes move to the Si-SiO2 interface and form interface states, which act as mediating energy levels in the SHR recombination process and increase the dark current of STI interface defects.

[0023] The dark current in the TX-PD overlap region originates during charge transport when the high-concentration surface P-region (P+) overlaps with the TX transport gate. This allows P+ to enter under the gate, and the excessively high P+ concentration causes pinch-off in the N-region under the gate, leading to a high electric field E where the voltage from the FD to the N-region drops primarily across this narrow area. Under this field, some photogenerated carriers reach velocity saturation, becoming hot carriers. These hot carriers continuously bombard the Si-SiO2 interface, creating numerous fast interface states and increasing the level of interface defects and dark current. This dark current, caused by these interface states, then ionizes due to collisions with other doped atoms under the high electric field, resulting in more hot electrons accumulating in the TX channel. If the TX channel potential distribution favors hot electron inflow into the PD, the dark current level will rise sharply. After total dose irradiation, the TX channel gate oxide interface will form more dangling bonds under the action of ionizing radiation. The defect density available for generating the above fast interface states will increase compared to the unirradiated state, thus forming another important source of radiation-generated dark current.

[0024] Therefore, the current generated by STI interface defects and the current generated in the TX-PD overlap area are the main reasons for the increase in pixel dark current under the TID effect.

[0025] For step 1, a negative bias V is applied to STIX. STIUnder the applied electric field, holes migrate directionally toward the surface polysilicon gate (STIX). During this migration, positively charged radiation-induced oxide trap charges are formed, moving away from the SiO2 / Si interface between the STIX and the pixel. Compared to the pixel structure of a traditional 4T CMOS image sensor, the interface state trap charges generated at the SiO2 / Si interface between the STIX and the pixel are significantly reduced. Therefore, a negative bias V is applied to the STIX. STI This allows for the suppression of dark currents generated by STI interface defects caused by irradiation; In step 1, STIX is given a negative bias V. STI A larger bias is not necessarily better; the specific value should be determined after the process is debugged. In step 1 and step 4, the TX shutdown voltage is a negative bias V. TX When a negative bias voltage is applied to the TG, the surface potential is negative, and the surface exhibits a majority-carrier hole accumulation state. The accumulated holes fill part of the interface trap charge, which can effectively reduce the generation of dark current at the TG. Its suppression mechanism for surface current is similar to that of p+ layer heavy doping, thereby suppressing the dark current generated in the TX-PD overlap region caused by irradiation; the overall pixel size is 2.5μm × 2.5μm, where: 1. Transfer transistor (TX): The gate width of the TX transistor is 0.25μm and the length is 1μm. After the TX transistor is turned on, photogenerated electrons are transferred from the PD region to the SF transistor through the TX transistor. 2. Reset transistor (RST): The gate width of the RST transistor is 0.5μm and the length is 0.25μm. After the RST transistor is turned on, the node potential of the FD region is pulled up to Vdd. 3. Source Follower (SF): The SF transistor has a gate width of 0.5μm and a length of 0.6μm. It amplifies the voltage signal and converts it into a current signal output. 4. Horizontal Select Transistor (SEL): The gate width of the SEL is 0.5μm and the length is 0.25μm. When the SEL is turned on, the pixel output voltage signal can be read out. 5. STI bias gate (STIX): This polysilicon gate is 0.2μm wide and is distributed above the STI region. It is used to apply a negative bias voltage to suppress the dark current growth caused by the TID effect. 6. Photodiode (PD area): The PD area is a right trapezoid with the lower right corner of a rectangle measuring 1.6μm × 1.6μm and the right corner of the rectangle having a right angle of 0.6μm removed. The internal photoelectric effect occurs, converting the optical signal into an electrical signal. 7. Floating Node (FD Region): The FD region is a rectangle with dimensions of 0.25μm × 0.3μm, which collects signal charge and facilitates readout using the dual sampling method.

[0026] The photon signal enters the PD region and generates photogenerated electrons in the N-type depletion layer, which are then initially stored in the PD region. The FD region can be raised to Vdd by turning on the RST transistor. The voltage signal is then converted into a current signal output via a source follower, ultimately achieving the conversion from optical to electrical signals. STIX applies a negative voltage bias to the STI region, providing radiation hardening.

[0027] In this embodiment of the invention, only one bias voltage is used, in which case STIX is given a negative bias V. STI TX shutdown voltage is negative bias V TX All are V TG-L The pixel operation method for a radiation-resistant 4T CMOS image sensor provided by this invention is as follows: 1. After the device is powered on at time t0 and before time t1, STIX is negatively biased by V. TG-L This suppresses the increase in dark current caused by STI interface defects due to the TID effect. A negative bias is applied to the TX transistor. TG-L This suppresses the increase in TX-PD overlap current caused by the TID effect. A positive bias V is applied to the SEL transistor. SEL The pixel output gate is turned on, allowing Vpixel-out to be output. A positive bias V is applied to the RST transistor. RST This makes the floating node FD potential V FD The electrons that were originally present in the floating node FD are pulled up to Vdd. 2. During the time interval t1~t2, the RST transistor is first removed from the positive bias, and the potential of the floating node FD is no longer locked at Vdd. Then, a sampling signal SH1 is applied to sample the pixel output voltage at this time, which is recorded as the reset voltage V. reset ; 3. During the time interval t2~t3, a positive bias V is applied to the TX transistor. TX The optical signal originally collected in the PD region generates electrons, which are then transmitted to the FD region through the opened TX transistor, and the floating node FD potential V is set. FD As the signal charge gradually decreases, once the signal charge has completely transferred to the FD region, the floating node FD potential V... FD No longer changing; 4. During the time interval t3~t4, after the signal stabilizes, apply a negative bias V. TG-L After the TX transistor is turned off, another sampling signal SH2 is applied, and the output voltage of the pixel at this time is read and recorded as Vsignal; 5. By subtracting the two output voltages of the pixel, the signal voltage Vpixel-out can be obtained, realizing true correlated double sampling (CDS) in the circuit and eliminating pixel KBTC noise and fixed pattern noise (FPN). This process can be represented by Equation 1, where Gpixel is the gain of the source follower SF transistor, which is 0.88; 6. After time t5, the device is powered off, and the pixel stops working.

[0028] By changing the negative bias voltage V TG-L Size, changes in pixel dark current before and after irradiation, such as Figure 5 As shown, it can be seen that when V TG-L When V is set to a negative bias, the increase in pixel dark current caused by the post-radiation TID effect is significantly suppressed. TG-L Radiation resistance is maximized at ≤-0.6V.

[0029] The above description is only the best specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the protection scope of the present invention.

[0030] The contents not described in detail in this specification are prior art known to those skilled in the art. It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.

Claims

1. A pixel structure for a radiation-resistant 4T CMOS image sensor, characterized in that, Includes transmission transistors, reset transistors, source followers, row select transistors, STI bias gates, photodiodes, floating nodes, shallow trench isolation regions, and P-type substrates; The photodiode is surrounded by a P-type substrate, which is enclosed by the shallow trench isolation region. Part of the shallow trench isolation region is covered with an STI bias gate. The lower right corner of the photodiode is connected to one side of the transmission tube, and the other side of the transmission tube is connected to the floating node. The floating node is connected in sequence to the reset tube, the row select tube, and the source follower. The photon signal enters the photodiode, generating photoelectrons in the N-type depletion layer, and is initially stored in the photodiode. By turning on the reset transistor, the floating node potential is pulled up to Vdd. After the transmission transistor is turned on, due to the high floating node potential, the photoelectrons are transmitted from the photodiode to the source follower through the transmission transistor. After the row select transistor is turned on, the voltage signal is converted into a current signal output through the source follower, ultimately realizing the conversion of optical signal to electrical signal. The STI bias gate applies a negative voltage bias to the STI region, which plays a role in radiation hardening.

2. A method for operating the pixel structure of a radiation-resistant 4T CMOS image sensor as described in claim 1, characterized in that, Includes the following steps: Step S1: After the device is powered on at time t0, and before time t1, the STI bias gate is negatively biased by V. STI To suppress the increase in dark current at the STI interface defects caused by the TID effect; apply a negative bias V to the transmission transistor. TX To suppress the increase in TX-PD overlap current caused by the TID effect; apply a positive bias V to the horizontal select transistor. SEL The pixel output gating is turned on. Output is achieved; the reset transistor is positively biased V. RST Make the floating node potential V FD The electrons that were originally present in the floating node are pulled up to Vdd. In step S2, during the time interval t1~t2, the reset transistor is removed from the positive bias, and the floating node potential is no longer locked at Vdd. The input sampling signal SH1 is used to sample the pixel output voltage at this time, which is recorded as the reset voltage. ; In step S3, during the time interval t2~t3, a positive bias V is applied to the transmission tube. TX The light signal originally collected in the photodiode region generates electrons, which are then transmitted to the floating node region through the open transmission tube. The floating node potential V FD As the signal charge gradually decreases, the floating node potential V decreases after the signal charge has been completely transferred to the floating node region. FD No longer changing; In step S4, during the time interval t3~t4, after the signal stabilizes, apply a negative bias V. TX After the transmission transistor is turned off, the sampling signal SH2 is input, and the output voltage of the pixel at this time is read and recorded as . Step S5: Subtract the two output voltages of the pixel to obtain the signal voltage. This achieves true correlated double sampling in the circuit, eliminating pixel KBTC noise and fixed-pattern noise. in It is the gain of the source follower SF transistor.

3. The method for operating the pixel structure of a radiation-resistant 4T CMOS image sensor as described in claim 2, characterized in that, In step S1, a negative bias V is applied to the STI bias gate. STI Then, the holes move directionally toward the surface polysilicon gate STIX; As holes move, they form positively charged radiation-induced oxide trap charges, moving away from the shallow trench isolation region and the SiO2 / Si interface of the pixel.

4. The method for operating the pixel structure of a radiation-resistant 4T CMOS image sensor as described in claim 2, characterized in that, The value range is 0.8 to 0.9.

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