Electronic device and method of manufacturing the same

Abstract

This invention discloses an electronic device and its manufacturing method. The electronic device includes a substrate, a shielding layer, an insulating layer, a circuit layer, and electronic components. The substrate includes a first, second, and third portion, wherein the first portion is lower than the second portion, and the third portion connects the second portion and the first portion to form a recess. The shielding layer is disposed on the first, second, and third portions. The insulating layer is disposed on the shielding layer. The circuit layer is disposed on the insulating layer. The electronic components are disposed in the recess and electrically connected to the circuit layer. The shielding layer disposed on the third portion laterally surrounds the electronic components.

Description

Technical Field

[0001] This invention relates to an electronic device and a method for manufacturing the same. Background Technology

[0002] As the demand for diverse functions in electronic devices increases, the circuits and components in electronic devices become increasingly dense, leading to mutual interference of electrical signals and resulting in poor reliability. Summary of the Invention

[0003] Embodiments of the present invention provide an electronic device and a method for manufacturing the same, which helps to improve the problem of mutual interference of electrical signals.

[0004] An electronic device according to an embodiment of the present invention includes a substrate, a shielding layer, an insulating layer, a circuit layer, and at least one electronic component. The substrate includes a first portion, a second portion, and a third portion, wherein the first portion is lower than the second portion, and the third portion connects the second portion and the first portion to form a recess. The shielding layer is disposed on the first portion, the second portion, and the third portion. The insulating layer is disposed on the shielding layer. The circuit layer is disposed on the insulating layer. The at least one electronic component is disposed in the recess and electrically connected to the circuit layer. The shielding layer disposed on the third portion laterally surrounds the at least one electronic component.

[0005] An embodiment of the present invention provides a method for manufacturing an electronic device, comprising: forming a planar multilayer structure, the planar multilayer structure including a substrate and a shielding layer, an insulating layer and a circuit layer sequentially stacked on the substrate; performing a molding process on the planar multilayer structure to transform the planar multilayer structure into a non-planar multilayer structure with grooves; and bonding at least one electronic component to the circuit layer in the groove to be formed or already formed.

[0006] To make the present invention more apparent and understandable, specific embodiments are described below, along with detailed descriptions in conjunction with the accompanying drawings. Attached Figure Description

[0007] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0008] Figure 1 This is a partial top view schematic diagram of an electronic device according to the first embodiment of the present invention;

[0009] Figure 2 It corresponds Figure 1 A schematic diagram of the cross section along the central section line I-I';

[0010] Figure 3A as well as Figure 3B They are Figure 2 Two enlarged schematic diagrams of the middle region R;

[0011] Figure 4 This is a partial cross-sectional schematic diagram of an electronic device according to a second embodiment of the present invention;

[0012] Figure 5 This is a partial cross-sectional schematic diagram of an electronic device according to a third embodiment of the present invention;

[0013] Figure 6 This is a partial top view of an electronic device according to the fourth embodiment of the present invention;

[0014] Figure 7 It corresponds Figure 6 Schematic diagram of the cross section along the center section line II-II';

[0015] Figures 8 to 15 These are partial cross-sectional schematic diagrams of various electronic devices according to the fifth to twelfth embodiments of the present invention;

[0016] Figure 16 This is a partial perspective view of an electronic device according to the thirteenth embodiment of the present invention;

[0017] Figures 17A to 17C as well as Figures 18A to 18C These are schematic flowcharts illustrating two methods for manufacturing electronic devices according to some embodiments of the present invention. Detailed Implementation

[0018] The directional terms used in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0019] In the accompanying drawings, each figure illustrates general features of the methods, structures, and / or materials used in specific exemplary embodiments. However, these figures should not be construed as defining or limiting the scope or nature covered by these exemplary embodiments. For example, for clarity, the relative dimensions, thicknesses, and locations of various films, regions, and / or structures may be reduced or enlarged.

[0020] In the implementation, the same or similar elements will be designated by the same or similar reference numerals, and their descriptions will be omitted. Furthermore, features in different exemplary embodiments may be combined with each other without conflict, and simple equivalent changes and modifications made in accordance with this specification or claims are still within the scope of this patent.

[0021] The terms "first," "second," etc., used in this specification or claims are only used to name different elements or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements, nor to limit the manufacturing or placement order of the elements. Furthermore, the placement of one element / film layer on (or above) another element / film layer may include situations where there are or are not additional elements / film layers between the two elements / film layers; in other words, the element / film layer may be directly or indirectly placed on (or above) the other element / film layer. On the other hand, the placement of one element / film layer directly on (or above) another element / film layer indicates that the two elements / film layers are in contact with each other, and there are no additional elements / film layers between the two elements / film layers.

[0022] Figure 1 This is a partial top view of an electronic device according to a first embodiment of the present invention. Figure 2 It corresponds Figure 1 A schematic diagram of the cross section along the central section line I-I'. Figure 3A as well as Figure 3B They are Figure 2 Two enlarged schematic diagrams of the middle region R. Figure 4 This is a partial cross-sectional schematic diagram of an electronic device according to a second embodiment of the present invention. Figure 5 This is a partial cross-sectional schematic diagram of an electronic device according to a third embodiment of the present invention. Figure 6 This is a partial top view of an electronic device according to a fourth embodiment of the present invention. Figure 7 It corresponds Figure 6 A schematic diagram of the cross-section along the midline II-II'. Figures 8 to 15 These are partial cross-sectional schematic diagrams of various electronic devices according to the fifth to twelfth embodiments of the present invention. Figure 16 This is a partial perspective view of an electronic device according to the thirteenth embodiment of the present invention. Figures 17A to 17C as well as Figures 18A to 18C These are schematic flowcharts illustrating two methods for manufacturing electronic devices according to some embodiments of the present invention.

[0023] Please refer to the following first. Figure 1 as well as Figure 2 The electronic device 1 may include a substrate 10, a shielding layer 11, an insulating layer 12, a circuit layer 13, and at least one electronic component 14, but is not limited thereto. The electronic device 1 may include other components or films depending on different requirements.

[0024] In detail, the substrate 10 is used to support the shielding layer 11, the insulating layer 12, the circuit layer 13, and at least one electronic component 14. In some embodiments, the thickness T10 of the substrate 10 (e.g., the maximum thickness in the thickness direction D3) may be greater than or equal to 0.1 mm and less than or equal to 5 mm, and the Young's modulus of the substrate 10 may be greater than or equal to 0.5 GPa and less than or equal to 20 GPa, to facilitate stretching, compression, or shaping. For example, the material of the substrate 10 may include polyethylene terephthalate (PET), polyethylene terephthalate (PETG), polycarbonate (PC), polyimide (PI), polymethyl methacrylate (PMMA; or acrylic), polyethersulfone (PES), polysiloxane (PDMS), acrylonitrile-butadiene-styrene copolymer (ABS), or combinations thereof, but is not limited thereto.

[0025] like Figure 2 As shown, the substrate 10 may include a first portion 101, a second portion 102, and a third portion 103, wherein the first portion 101 is lower than the second portion 102, and the third portion 103 connects the second portion 102 to the first portion 101 to form a groove G. In some embodiments, as will be discussed later... Figures 17A to 17C or Figures 18A to 18C The described method involves shaping a planar substrate into a non-planar substrate (with grooves G) through a molding process (e.g., thermoforming), such that the bottom surface SB101 of the first portion 101 (e.g., the surface of the first portion 101 away from the shielding layer 11) is lower than the bottom surface SB102 of the second portion 102 (e.g., the surface of the second portion 102 away from the shielding layer 11), and the top surface ST101 of the first portion 101 (e.g., the surface of the first portion 101 facing the shielding layer 11) is lower than the top surface ST102 of the second portion 102 (e.g., the surface of the second portion 102 facing the shielding layer 11), wherein the bottom surface SB103 of the third portion 103 (e.g., the surface of the third portion 103 away from the shielding layer 11) connects the bottom surface SB101 of the first portion 101 to the bottom surface SB102 of the second portion 102, and the top surface ST103 of the third portion 103 connects the top surface ST101 of the first portion 101 to the top surface ST102 of the second portion 102.

[0026] A shielding layer 11 is disposed on the first portion 101, the second portion 102, and the third portion 103. In some embodiments, the shielding layer 11 is conformally disposed on the first portion 101, the second portion 102, and the third portion 103, such that, in a cross-sectional view, as shown... Figure 2 As shown, the shielding layer 11 may have a similar morphology to the substrate 10. For example, the shielding layer 11 may also have a groove conforming to the groove G (not shown separately for the sake of simplicity in the figure).

[0027] The shielding layer 11 is used, for example, to shield electromagnetic waves (MW). In some embodiments, the stretchability of the shielding layer 11 is greater than or equal to 20% to facilitate stretching, compression, or shaping. In some embodiments, although not shown, the shielding layer 11 may have a patterned structure to facilitate stretching, compression, or shaping. The patterned structure may include a mesh structure, such as a vertical mesh (including multiple thin lines extending along direction D1 and multiple thin lines extending along direction D2), a 45-degree mesh (including multiple thin lines extending along direction D4 and multiple thin lines extending along direction D5), a zigzag mesh, a solid diamond mesh, a checkerboard mesh, a dotted mesh, a random dotted mesh, a tile mesh, a mesh fabric mesh, a fine mesh, a diagonal brick mesh, a horizontal brick mesh, a knitted mesh, or other forms of mesh, but not limited thereto.

[0028] In some embodiments, the resistivity of the shielding layer 11 may be greater than or equal to 10. -8 Ω·m and less than or equal to 10 -6 The thickness T11 of the shielding layer 11 (e.g., the maximum thickness in the thickness direction D3) may be greater than or equal to 10 μm to improve the electromagnetic wave shielding effect and / or provide electrostatic discharge (ESD) protection. For example, the shielding layer 11 may include metal particles (e.g., gold, silver, platinum, copper, aluminum, nickel, etc.), metal oxides (e.g., iron(II,III) oxide as a magnetic filler), carbon materials (e.g., carbon black, carbon fibers, graphene, carbon nanotubes), or MXene-like materials (e.g., an alternating stacked structure of multiple metal carbide layers and multiple carbon layers), but is not limited thereto.

[0029] An insulating layer 12 is disposed on a shielding layer 11. In some embodiments, the insulating layer 12 is conformally disposed on the shielding layer 11, for example, so that in a cross-sectional view, as shown... Figure 2 As shown, the insulating layer 12 may also have a similar morphology to the substrate 10. For example, the insulating layer 12 may also have a groove conforming to the groove G (not shown separately for the sake of simplicity in the figure).

[0030] The insulating layer 12 can be used to electrically insulate the shielding layer 11 from the circuit layer 13. In some embodiments, the insulating layer 12 may be made of a material that is easy to stretch, compress, or shape, and the insulating layer 12 may have a high dielectric constant, for example, a dielectric constant greater than or equal to 3.9, but is not limited thereto. For example, the material of the insulating layer 12 may include dielectric materials such as acrylic, epoxy, phenol, polyester, polyurethane, silicone, and polyimide, but is not limited thereto.

[0031] A circuit layer 13 is disposed on an insulating layer 12. In some embodiments, the circuit layer 13 is conformally disposed on the insulating layer 12, for example. The circuit layer 13 can be used to electrically connect the at least one electronic component 14 to other components (not shown). Figure 1 and Figure 2 ) or external circuit (not shown in Figure 1 and Figure 2 For example, the material of circuit layer 13 may include gold, silver, copper, aluminum, platinum, nickel, tin, carbon, alloys of the above, or combinations thereof, but is not limited thereto.

[0032] like Figure 1 As shown, the circuit layer 13 may include multiple wires 131 and multiple pads 132, wherein each wire 131 may extend into the groove G along direction D1, the opposite direction of direction D1, direction D2, or the opposite direction of direction D2 and connect to a corresponding pad 132. Figure 1 As shown, each pad 132 may be located at the end of a corresponding wire 131 adjacent to the end of the at least one electronic component 14, but is not limited thereto.

[0033] The at least one electronic component 14 is disposed in the recess G and electrically connected to the circuit layer 13. For example, a plurality of pins 140 of the electronic component 14 may be electrically connected to a plurality of pads 132 of the circuit layer 13, respectively. The manner in which the pins 140 are electrically connected to the corresponding pads 132 is not limited. For example, the pins 140 may be electrically connected to the corresponding pads 132 by wire bonding, flip-chip bonding, or other methods.

[0034] like Figure 2 As shown, the shielding layer 11 disposed on the third portion 103 laterally surrounds the at least one electronic component 14 disposed in the groove G, thus providing an electromagnetic wave shielding effect, such as shielding the electromagnetic waves MW generated by the at least one electronic component 14 from interference to other electromagnetic wave sensitive elements / electromagnetic wave generating elements (not shown), and / or shielding the electromagnetic waves generated by other electromagnetic wave sensitive elements / electromagnetic wave generating elements (not shown) from interference to the at least one electronic component 14. In some embodiments, such as Figure 2 As shown, the shielding layer 11 may be grounded. In some embodiments, the at least one electronic component 14 may include at least one electromagnetic wave sensitive element, such as a radio frequency (RF) element, an intermediate frequency (IF) element, a high frequency element, a power supply, a touch sensor, a low frequency element, a piezoelectric element, a light-emitting diode (LED), an active element, a passive element, a buzzer, other electromagnetic wave generating elements, or a combination thereof. Figure 1 as well as Figure 2Only one electronic component 14 is shown schematically, but it should be understood that the electronic device 1 may include multiple electronic components 14 as required, and the multiple electronic components 14 may be of the same or different types.

[0035] By forming a groove G and using a shielding layer 11 (also known as a three-dimensional shielding structure) disposed on the side wall of the groove G to shield electromagnetic waves, it is possible to avoid increasing the size and / or weight of the electronic device 1, reduce the influence of the material shielding rate on the electromagnetic wave shielding effect, and / or provide the ability of 3D curved circuit to shield electromagnetic waves and / or electrostatic discharge.

[0036] The larger the lateral shielding area of ​​shielding layer 11, the better the electromagnetic wave shielding effect. Figure 2 In this architecture, the greater the depth DP of the groove G, the larger the lateral shielding area of ​​the shielding layer 11. In some embodiments, the depth DP of the groove G may be greater than or equal to twice the thickness T14 of the electronic component 14 (e.g., the maximum thickness in the thickness direction D3), for example, greater than or equal to five times the thickness T14 of the electronic component 14, or greater than or equal to ten times the thickness T14 of the electronic component 14, in order to improve the electromagnetic wave shielding effect.

[0037] exist Figure 2 In this architecture, the shielding layer 11 has a groove conformally to the groove G. The opening of the groove in the shielding layer 11 is proportional to the opening AG of the groove G. The narrower the opening AG, the less electromagnetic wave MW is leaked. In some embodiments, the included angle θ between the third portion 103 and the first portion 101 of the substrate 10 may be greater than or equal to 90 degrees and less than or equal to 110 degrees, for example, greater than or equal to 90 degrees and less than or equal to 100 degrees, or greater than or equal to 90 degrees and less than or equal to 95 degrees, to obtain a groove G with a narrower opening AG.

[0038] In some embodiments, such as Figure 3A As shown, the angle C between the third part 103 and the first part 101 can be a chamfer with a length L greater than or equal to 1 mm; or, as shown... Figure 3B As shown, the corner C between the third part 103 and the first part 101 can be a rounded corner with a radius RD greater than or equal to 1 mm to facilitate demolding.

[0039] In some embodiments, such as Figure 1 As shown, the width WG of the groove G is greater than or equal to 1.5 times the length L14 of the at least one electronic component 14 to facilitate the bonding of the at least one electronic component 14 to the circuit layer 13, for example, to reserve space for surface mount processes. The length L14 of the electronic component 14 refers to the length of the longer side of the electronic component 14 in the top view. Figure 1For example, the length L14 of electronic component 14 is the length of the side of electronic component 14 extending along direction D1. The width WG of groove G refers to the side length of the longer side of electronic component 14 corresponding to groove G in the top view.

[0040] A method for manufacturing an electronic device 1 may include: forming a planar multilayer structure 2, the planar multilayer structure 2 including a substrate 10 and a shielding layer 11, an insulating layer 12, and a circuit layer 13 sequentially stacked on the substrate 10; performing a molding process on the planar multilayer structure 2 to transform the planar multilayer structure 2 into a non-planar multilayer structure 3 having a groove G; and bonding at least one electronic component 14 to the circuit layer 13 in the groove G to be formed or already formed, such as... Figures 17A to 17C or Figures 18A to 18C As shown.

[0041] Figure 17A as well as Figure 18A A planar multilayer structure 2 including a substrate 10, a shielding layer 11, an insulating layer 12, and a circuit layer 13 is shown. In some embodiments, the shielding layer 11, the insulating layer 12, and the circuit layer 13 may be formed on the substrate 10 by a screen printing process, but are not limited thereto.

[0042] In some embodiments, such as Figure 17B as well as Figure 17C As shown, electronic components 14 can be first bonded to the planar multilayer structure 2, and then grooves G can be formed through a molding process, wherein... Figure 17B At this location, electronic component 14 is bonded to circuit layer 13 in the groove G to be formed, so that after the molding process, as Figure 17C As shown, electronic component 14 is located in groove G. The molding process may include, but is not limited to, vacuum high-pressure thermoforming or vacuum thermoforming. Figures 17A to 17C In the embodiment shown, the electronic component 14 is bonded to the planar multilayer structure 2 before the molding process forms the groove G. Therefore, the fabrication of the electronic device 1 is initially completed when the non-planar multilayer structure 3 with the groove G is formed.

[0043] Alternatively, in Figures 18A to 18C In the illustrated embodiment, a molding process is first performed to form a non-planar multilayer structure 3 with grooves G, and then electronic components 14 are bonded to the circuit layer 13 in the formed grooves G. That is, electronic components 14 are not bonded to the planar multilayer structure 2, but are directly bonded to the non-planar multilayer structure 3 with grooves G, and the step of forming the non-planar multilayer structure 3 with grooves G (as shown in the example) Figure 18B As shown) After the initial completion of the fabrication of electronic device 1 (as shown) Figure 18C (as shown) before.

[0044] The electronic device of any embodiment of the present invention may employ, as follows: Figures 17A to 17C and / or Figures 18A to 18C The process steps shown are for manufacturing, and will not be repeated below.

[0045] Please refer to Figure 4 Electronic device 1A and Figure 2 The main difference in electronic device 1 is that electronic device 1A further includes a heat dissipation layer 15, wherein the heat dissipation layer 15 is disposed on the circuit layer 13, and the circuit layer 13 is located between the heat dissipation layer 15 and the shielding layer 11. In some embodiments, the heat dissipation layer 15 is conformally disposed on the circuit layer 13, for example. Figure 17A as well as Figure 18A The planar multilayer structure 2 shown may further include a heat dissipation layer 15. The heat dissipation layer 15, together with the substrate 10, shielding layer 11, insulating layer 12 and circuit layer 13, is formed by a molding process to form a non-planar multilayer structure 3 with a groove G, and the at least one electronic component 14 may be bonded to the circuit layer 13 in the groove G to be formed or already formed.

[0046] In some embodiments, the thermal conductivity of the heat dissipation layer 15 may be greater than or equal to 6 W / (m·K) to improve heat dissipation. In some embodiments, the elongation of the heat dissipation layer 15 may be greater than or equal to 20% to facilitate stretching, compression, or shaping. For example, the base material of the heat dissipation layer 15 may include thermoplastic polyurethane (TPU), thermoplastic polyester elastomer (TPEE), styrene-based elastomer (TPS), or nylon 12 elastomer (PAE), and the heat dissipation layer 15 may additionally contain boron nitride (BN), aluminum nitride (AlN), alumina (Al2O3), boron nitride carbon nanotubes (BNNT), or a mixture of at least one of the above materials in different proportions, but is not limited to a single material or a combination thereof.

[0047] In some embodiments, such as Figure 4 As shown, the heat dissipation layer 15 may contact the pins 140 or heat sink (not shown) of the at least one electronic component 14 to diffuse heat outward by enclosing the heat source, thereby improving the heat dissipation effect. In some embodiments, in a top view (not shown), the area of ​​the heat dissipation layer 15 may be greater than or equal to four times the area of ​​the at least one electronic component 14 disposed in the groove G to improve the heat dissipation effect by diffusing heat outward. In some embodiments, the thickness T15 of the heat dissipation layer 15 (e.g., the maximum thickness in the thickness direction D3) may be greater than or equal to three / five times (three-fifths of a time) of the thickness T14 of the at least one electronic component 14, for example, greater than or equal to twice the thickness T14 of the at least one electronic component 14, to dissipate heat by increasing the contact area between the heat dissipation layer 15 and the air to form thermal convection.

[0048] By forming a groove G and utilizing a heat dissipation layer 15 disposed on the sidewall of the groove G, heat can be diffused outward, reducing the temperature difference between the heat source (such as electronic component 14) and its surroundings. This helps to improve the problem of reduced operating efficiency of electronic component 14 due to heat concentration. If the electronic device 1A is further encapsulated with a packaging material (e.g., plastic), and the heat concentration is mitigated through a three-dimensional heat dissipation structure design, the problem of localized damage to the packaging material caused by heat concentration can be improved, thereby enhancing the reliability and lifespan of the product.

[0049] Please refer to Figure 5 Electronic device 1B and Figure 4 The main difference between electronic device 1A and electronic device 1B is that electronic device 1B further includes a decorative layer 16, wherein the decorative layer 16 is disposed between the substrate 10 and the shielding layer 11. In some embodiments, the decorative layer 16 is conformally disposed on the substrate 10, for example. Figure 17A as well as Figure 18A The planar multilayer structure 2 shown may further include a decorative layer 16. The decorative layer 16, together with the substrate 10, shielding layer 11, insulating layer 12, circuit layer 13 and heat dissipation layer 15, is formed by a molding process to form a non-planar multilayer structure 3 with a groove G, and the at least one electronic component 14 may be bonded to the circuit layer 13 in the groove G to be formed or already formed.

[0050] In some embodiments, the decorative layer 16 may provide not only a decorative effect (e.g., reducing the visibility of the circuit layer 13) but also an electromagnetic wave shielding effect. For example, the material of the decorative layer 16 may include carbon black or other non-conductive materials that can shield electromagnetic waves.

[0051] Please refer to Figure 6 as well as Figure 7 Electronic device 1C and Figure 5 The main difference of the electronic device 1B is that the electronic device 1C also includes a shielding layer 17, a shielding via 18 and an insulating layer 19, wherein the shielding layer 17 is disposed on the circuit layer 13, the shielding via 18 penetrates the circuit layer 13 and the insulating layer 12 to electrically connect the shielding layer 11 and the shielding layer 17, and the shielding via 18 is electrically insulated from other film layers through the insulating layer 19.

[0052] In detail, in the architecture of the electronic device 1C including a heat dissipation layer 15, a shielding layer 17 may be disposed on the heat dissipation layer 15 and electrically insulated from the circuit layer 13 through the heat dissipation layer 15. In some embodiments, the shielding layer 17 and the shielding via 18 may be formed together, but are not limited thereto. For example, a via TH penetrating the heat dissipation layer 15, the circuit layer 13, and the insulating layer 12 may be formed first, and then an insulating layer 19 may be formed on the sidewall of the via TH. Next, the shielding layer 17 is formed on the heat dissipation layer 15, and the shielding via 18 is formed in the space of the via TH not occupied by the insulating layer 19. In some embodiments, such as Figure 7 As shown, the shielding layer 17 may expose electronic components and the heat dissipation layer 15 overlapping the groove G, but the invention is not limited thereto. In other embodiments, such as Figure 9 As shown, the shielding layer 17 can cover the electronic component 14 and the heat dissipation layer 15 overlapping the groove G.

[0053] Details of shielding layer 17 (e.g., patterned structure, resistivity, thickness T17, and / or material, etc.) can be found in the description of shielding layer 11 and will not be repeated here. Details of insulating layer 19 (e.g., dielectric constant, and / or material, etc.) can be found in the description of insulating layer 12 and will not be repeated here.

[0054] Figure 17A as well as Figure 18A The planar multilayer structure 2 shown may further include a shielding layer 17, a shielding via 18, and an insulating layer 19. The shielding layer 17, the shielding via 18, and the insulating layer 19, together with the substrate 10, the decorative layer 16, the shielding layer 11, the insulating layer 12, the circuit layer 13, and the heat dissipation layer 15, are formed by a molding process to create a non-planar multilayer structure 3 with a groove G, and the at least one electronic component 14 can be bonded to the circuit layer 13 in the groove G to be formed or already formed.

[0055] By setting the shielding through-hole 18, the lateral shielding effect of electromagnetic waves can be improved. Figure 6 Four L-shaped shielding vias 18 are schematically shown, but it should be understood that the design parameters of the shielding vias 18 (such as number, top view shape, and / or location) can be changed according to actual needs, and are not fixed. Figure 6 The examples shown are for illustrative purposes only. For instance, the shielding via 18 may be coarser or finer; the number of shielding vias 18 may be greater or less; and / or the shielding via 18 may be located on one side, adjacent sides, opposite sides, three sides, or four sides of the recess G. For instance, although not shown, the shielding via 18 may be located between two adjacent recesses G, or between electronic component 14 and other electronic components.

[0056] Please refer to Figure 8 Electronic device 1D and Figure 7The main differences of the electronic device 1C are explained below. In the electronic device 1D, the heat dissipation layer 15 is replaced by an insulating layer 20. The design parameters of the insulating layer 20 can be referred to the design parameters of the insulating layer 19, and will not be repeated here. In some embodiments, the insulating layer 20 and the insulating layer 19 may be formed together, but are not limited thereto. For example, a via TH' penetrating the circuit layer 13 and the insulating layer 12 may be formed first, and then the insulating layer 20 and the insulating layer 19 may be formed on the circuit layer 13 and the sidewall of the via TH', respectively, wherein the insulating layer 20 and the insulating layer 19 may be formed by the same process step. Next, a shielding layer 17 is formed on the insulating layer 20 and a shielding via 18 is formed in the space of the via TH' not occupied by the insulating layer 19.

[0057] Figure 17A as well as Figure 18A The planar multilayer structure 2 shown may further include an insulating layer 20. The insulating layer 20, together with the substrate 10, decorative layer 16, shielding layer 11, insulating layer 12, circuit layer 13, shielding layer 17, shielding via 18, and insulating layer 19, is formed by a molding process to form a non-planar multilayer structure 3 with a groove G, and the at least one electronic component 14 can be bonded to the circuit layer 13 in the groove G to be formed or already formed.

[0058] Figure 8 The diagram schematically shows a shielding through-hole 18 located on one side of the groove G. However, it should be understood that the design parameters of the shielding through-hole 18 (such as the number, top view shape, and / or location) can be changed according to actual needs, and are not limited to this. Figure 8 The display is limited.

[0059] Please refer to Figure 9 Electronic device 1E and Figure 7 The main differences of the electronic device 1C are described below. The electronic device 1E also includes an encapsulation layer 21, which is disposed on the shielding layer 17. The material of the encapsulation layer 21 may include plastic or other molding materials, and is not limited thereto. Although Figure 9 Is Figure 7 The encapsulation layer 21 is further provided under the architecture, but it should be understood that electronic devices in other embodiments of the present invention may further include the encapsulation layer 21.

[0060] In some embodiments, the shielding layer 17 may overlap the at least one electronic component 14. In this architecture, after forming the heat dissipation layer 15, the electronic component 14 may be bonded to the circuit layer 13, followed by the formation of the insulating layer 19, the shielding layer 17, and the shielding via 18 (the shielding layer 17 and the shielding via 18 may be formed together). A molding process is then performed to form a non-planar multilayer structure 3 with grooves G. Finally, an encapsulation layer 21 is formed by an injection molding process.

[0061] By covering electronic component 14 with shielding layer 17, interference from electromagnetic waves (not shown) generated by electronic component 14 to adjacent electronic components (not shown) can be reduced. Electronic devices in other embodiments of the present invention may also employ this design of covering electronic component 14 with shielding layer 17, which will not be repeated below.

[0062] In some embodiments, the shielding layer 17 may cover the sidewalls of the decorative layer 16 (if present), the shielding layer 11, the insulating layer 12, the circuit layer 13, and the heat dissipation layer 15 (if present) to reduce interference from adjacent electronic components (not shown) to the electronic component 14 in the recess G. This design may also be used in electronic devices according to other embodiments of the present invention, which will not be repeated below.

[0063] Please refer to Figure 10 Electronic device 1F and Figure 9 The main difference in the electronic device 1E is that the portion of the encapsulation layer 21F that overlaps with the groove G is thinner than the rest of the encapsulation layer 21F. For example, the encapsulation layer 21F can be formed with varying thicknesses in different areas using a common mold. By designing the encapsulation layer 21F with varying thicknesses in different areas, heat dissipation can be improved by utilizing thermal convection.

[0064] Please refer to Figure 11 1G electronic devices and Figure 10 The main difference between the electronic device 1F and the shielding layer 17 and encapsulation layer 21G is that the at least one electronic component 14 is exposed. Figure 11 For example, the shielding layer 17 and the encapsulation layer 21G may not overlap with the groove G, allowing the heat dissipation layer 15 to directly contact the air, which helps to further improve the heat dissipation effect. In addition, the design that the electronic component 14 is not covered by the shielding layer 17 and the encapsulation layer 21G facilitates the rework or replacement of the electronic component 14.

[0065] Please refer to Figure 12 Electronic device 1H and Figure 10The main difference between the electronic device 1F and the electronic device 1H is that the electronic device 1H also includes a planarization layer 22, which is disposed between the at least one electronic component 14 and the shielding layer 17H. For example, after forming the shielding via 18, a groove G can be formed first by a molding process (where the electronic component 14 can be bonded to the circuit layer 13 before or after the molding process), and then the planarization layer 22, the shielding layer 17H, and the encapsulation layer 21H can be formed sequentially. In some embodiments, the material of the planarization layer 22 may include dielectric materials such as acrylic, epoxy, phenol, polyester, polyurethane, silicone, and polyimide, and the planarization layer 22 can be formed by potting, bonding, vapor deposition, sputtering, or a combination thereof, but is not limited thereto. Furthermore, in Figure 12 In this process, the shielding layer 17H can be formed by techniques such as attachment, evaporation, sputtering, or non-conductive vacuum metallization (NCVM) or a combination thereof, and the shielding layer 17H can be a metal film, metal cover, metal foil, metal woven mesh, conductive foam or conductive cloth, etc., but is not limited thereto.

[0066] although Figure 12 Is Figure 10 The architecture further includes a planarization layer 22 and changes to the design parameters (e.g., process, material, shape, etc.) of the shielding layer 17H and the encapsulation layer 21H. However, it should be understood that electronic devices in other embodiments of the present invention may also be modified in the same way.

[0067] Please refer to Figure 13 Electronic device 1I and Figure 12 The main difference in electronic device 1H is that the planarization layer 22 extends further between the heat dissipation layer 15 and the encapsulation layer 21H. In addition, electronic device 1I omits the shielding via 18 and the insulating layer 19.

[0068] although Figure 13 Is Figure 12 The design parameters of the flat layer 22 can be further modified under the architecture (e.g., layout area, etc.), but it should be understood that electronic devices in other embodiments of the present invention can also be modified in the same way.

[0069] Please refer to Figure 14 Electronic device 1J and Figure 13The main difference between the electronic device 1I and the electronic device 1J is that the electronic device 1J also includes electronic component 23 and electronic component 24. Electronic component 23 and electronic component 24 are disposed on circuit layer 13 and electrically connected to circuit layer 13. In some embodiments, electronic components 23 and 24 may be disposed in the non-radio frequency circuit region (NRF), and electronic component 14 may be disposed in the radio frequency circuit region (RF). The NRF and RF are separated by a shielding via 18, and the shielding via 18 and insulating layer 19 are disposed in a via TH” penetrating the planarization layer 22, the heat dissipation layer 15, the circuit layer 13, and the insulating layer 12. The electromagnetic waves MW generated by electronic component 14 in the RF circuit region are shielded or absorbed by the shielding layer 11 disposed on the sidewall of the recess G, the shielding layer 17H disposed on the planarization layer 22, and the shielding via 18 disposed between the NRF and RF circuit regions, thereby reducing the interference of electromagnetic waves MW on electronic components 23 and 24 in the NRF. For example, electronic component 23 and electronic component 24 may be a light-emitting diode (LED) and a resistor for regulating the current supplied to the LED, but are not limited thereto. In other embodiments, electronic component 23 and electronic component 24 may be other types of electronic components.

[0070] Please refer to Figure 15 Electronic devices 1K and Figure 14 The main differences of the electronic device 1J are explained below. In the electronic device 1K, electronic components 23 and 24 are respectively disposed on different circuit layers. For example, the electronic device 1K may also include an insulating layer 25, a circuit layer 26, and a heat dissipation layer 27, wherein the insulating layer 25, the circuit layer 26, and the heat dissipation layer 27 are stacked sequentially on the heat dissipation layer 15. Details of the insulating layer 25, the circuit layer 26, and the heat dissipation layer 27 can be referred to the descriptions of the insulating layer 12, the circuit layer 13, and the heat dissipation layer 15, respectively, and will not be repeated here. Electronic components 23 and 24 may be disposed on the circuit layers 13 and 26, respectively, and electronic components 23 and 24 may contact the heat dissipation layers 15 and 27, respectively. The planarization layer 22 may cover the heat dissipation layers 15 and 27.

[0071] although Figure 15 Is Figure 14 The arrangement of electronic components 23 and 24 can be further modified under the existing architecture, but it should be understood that electronic devices in other embodiments of the present invention can also be modified in the same way.

[0072] In addition, although Figure 15The example illustrates a device 1K comprising two circuit layers (including circuit layers 13 and 26), three insulating layers (including insulating layers 12, 19, and 25), two heat dissipation layers (including heat dissipation layers 15 and 27), three electronic components (including electronic component 14, electronic component 23, and electronic component 24), and a recess G. However, it should be understood that the electronic device 1K may include more circuit layers, more insulating layers, more heat dissipation layers, more electronic components, and more recesses G as needed. Figure 16 For example, the electronic device 1L may include multiple recesses G, and each recess G defines a radio frequency (RF) circuit area. Multiple electronic components may be disposed in each recess G. For instance, a first electronic component 14a and a second electronic component 14b may be disposed in the same recess G, and the distance DT (e.g., minimum distance) between the first electronic component 14a and the second electronic component 14b is, for example, greater than or equal to 10 mm. This is to reduce the increase in surface temperature when the heat source increases and / or improve the problem of localized damage to the packaging material (e.g., packaging layer 21H) caused by heat concentration, thereby improving the reliability and lifespan of the product.

[0073] In summary, in the embodiments of the present invention, the use of a three-dimensional shielding structure design to shield electromagnetic waves can improve the problem of mutual interference between electrical signals, avoid increasing the size and / or weight of electronic devices, reduce the impact of material shielding efficiency on the electromagnetic wave shielding effect, and / or provide the ability of 3D curved circuits to shield electromagnetic waves and / or electrostatic discharge. Optionally, a three-dimensional heat dissipation structure design can also mitigate heat concentration, improve the problem of localized damage to the packaging material caused by heat concentration, and thus improve the reliability and service life of the product.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electronic device, characterized in that, include: A substrate includes a first portion, a second portion, and a third portion, wherein the first portion is lower than the second portion, and the third portion connects the second portion to the first portion to form a groove; A shielding layer is disposed on the first part, the second part, and the third part; An insulating layer is disposed on the shielding layer; A circuit layer is disposed on the insulating layer; as well as At least one electronic component is disposed in the recess and electrically connected to the circuit layer, wherein the shielding layer disposed on the third portion laterally surrounds the at least one electronic component.

2. The electronic device according to claim 1, characterized in that, The depth of the groove is greater than or equal to twice the thickness of the electronic component.

3. The electronic device according to claim 1, characterized in that, The angle between the third part and the first part is greater than or equal to 90 degrees and less than or equal to 110 degrees.

4. The electronic device according to claim 1, characterized in that, The angle between the third part and the first part is a chamfer with a length greater than or equal to 1 mm or a rounded corner with a radius greater than or equal to 1 mm.

5. The electronic device according to claim 1, characterized in that, The thickness of the substrate is greater than or equal to 0.1 mm and less than or equal to 5 mm, and the Young's modulus of the substrate is greater than or equal to 0.5 GPa and less than or equal to 20 GPa.

6. The electronic device according to claim 1, characterized in that, The elongation of the shielding layer is greater than or equal to 20%, and the resistivity of the shielding layer is greater than or equal to 10. -8 Ω·m and less than or equal to 10 -6 Ω·m.

7. The electronic device according to claim 1, characterized in that, The at least one electronic component includes at least one electromagnetic wave sensitive element.

8. The electronic device according to claim 1, characterized in that, The at least one electronic component includes a first electronic component and a second electronic component, and the distance between the first electronic component and the second electronic component is greater than or equal to 10 mm.

9. The electronic device according to claim 1, characterized in that, Also includes: A heat dissipation layer is disposed on the circuit layer, wherein the circuit layer is located between the heat dissipation layer and the shielding layer.

10. The electronic device according to claim 9, characterized in that, The thermal conductivity of the heat dissipation layer is greater than or equal to 6 W / (m·K).

11. The electronic device according to claim 9, characterized in that, in: The heat dissipation layer contacts the pins or heat sink of the at least one electronic component. In the top view, the area of ​​the heat dissipation layer is greater than or equal to four times the area of ​​the at least one electronic component disposed in the groove, and The thickness of the heat dissipation layer is greater than or equal to 3 / 5 times the thickness of the at least one electronic component.

12. The electronic device according to claim 1, characterized in that, Also includes: Another shielding layer is disposed on the circuit layer; as well as A shielding via penetrates the circuit layer and the insulating layer to electrically connect the shielding layer to the other shielding layer.

13. The electronic device according to claim 12, characterized in that, Also includes: An encapsulation layer is disposed on the other shielding layer.

14. The electronic device according to claim 13, characterized in that, The other shielding layer overlaps with the encapsulation layer on the at least one electronic component, and the portion of the encapsulation layer that overlaps with the groove is thinner than the other portions of the encapsulation layer.

15. The electronic device according to claim 13, characterized in that, The other shielding layer and the encapsulation layer expose the at least one electronic component.

16. The electronic device according to claim 12, characterized in that, The other shielding layer completely covers the at least one electronic component, and the electronic device further includes: A planarization layer is disposed between the at least one electronic component and the other shielding layer.

17. The electronic device according to claim 1, characterized in that, The width of the groove is greater than or equal to 1.5 times the length of the at least one electronic component.

18. A method for manufacturing an electronic device, characterized in that, include: A planar multilayer structure is formed, the planar multilayer structure including a substrate and a shielding layer, an insulating layer and a circuit layer sequentially stacked on the substrate; The planar multilayer structure is subjected to a molding process to transform it into a non-planar multilayer structure with grooves. as well as At least one electronic component is attached to the circuit layer in the groove to be formed or already formed.

19. The method for manufacturing an electronic device according to claim 18, characterized in that, The method of forming the shielding layer, the insulating layer and the circuit layer on the substrate includes a screen printing process.

20. The method for manufacturing an electronic device according to claim 18, characterized in that, The molding process includes vacuum high-pressure thermoforming or vacuum thermoforming.

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