A chip screening method, device, equipment, medium and program product

Abstract

This invention relates to the field of chip technology and discloses a chip screening method, apparatus, device, medium, and program product. The method includes: during the chip testing phase, acquiring process corner data corresponding to each initial chip; acquiring the target ambient temperature range and the target thermal design current upper limit; and, through a pre-established target correlation model between ambient temperature, process corner, and the target thermal design current upper limit, acquiring the process corner limitation range based on the target ambient temperature range and the target thermal design current upper limit; and, based on the process corner limitation range and the process corner data, screening out target chips from each initial chip. This method enables chip screening based on the thermal design current upper limit, reduces performance fluctuations between chips, and ensures the operating efficiency of the chip cluster.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a chip screening method, apparatus, device, medium, and program product. Background Technology

[0002] As large-scale multi-GPU collaborative training and inference scenarios become increasingly prevalent in data centers, ensuring performance consistency among graphics processing unit (GPU) chips is crucial for improving overall application efficiency and data throughput.

[0003] In the hardware design, power management, and performance optimization of GPUs, the data transfer unit, as a core data transmission component, directly impacts the overall GPU performance due to its operational stability. To avoid performance fluctuations and hardware damage caused by overheating, excessive power consumption, or unstable power supply, the industry typically sets a long-term safe current limit for the data transfer unit, also known as the thermal design current limit. When the operating current of the data transfer unit approaches this thermal design current limit, the GPU's logic control unit actively activates a current limiting mechanism. This reduces current consumption by lowering the frequency and voltage of the data transfer unit or memory, ensuring the long-term safety and stability of the hardware. However, this current limiting behavior directly leads to a decrease in the GPU's bandwidth performance, preventing it from fully realizing its design potential and consequently affecting the performance consistency between GPU chips.

[0004] Against this industry backdrop, how to conduct efficient GPU performance quality control analysis based on the thermal design current safety limits of data transport units before GPUs leave the factory, and minimize performance fluctuations between GPU chips, has become a key technical challenge to ensure the overall operating efficiency of GPU clusters. Summary of the Invention

[0005] This invention provides a chip screening method, apparatus, device, medium, and program product, which can achieve chip screening based on the upper limit of thermal design current, reduce performance fluctuations between chips, and ensure the operating efficiency of chip clusters.

[0006] According to one aspect of the present invention, a chip screening method is provided, comprising: During the chip testing phase, process corner data corresponding to each initial chip is acquired; Obtain the target ambient temperature range and the target thermal design current upper limit, and obtain the process angle limit range based on the target ambient temperature range and the target thermal design current upper limit by using a pre-established target correlation model between ambient temperature, process angle and thermal design current upper limit; Based on the process angle limit range and the process angle data, the target chip is selected from each initial chip.

[0007] According to another aspect of the present invention, a chip screening apparatus is provided, comprising: The data acquisition module is used to acquire the process corner data corresponding to each initial chip during the chip testing phase. The range acquisition module is used to acquire the target ambient temperature range and the target thermal design current upper limit value, and to acquire the process angle limit range based on the target ambient temperature range and the target thermal design current upper limit value through a pre-established target correlation model between ambient temperature, process angle and thermal design current upper limit value. The chip screening module is used to screen target chips from the initial chips according to the process corner limit range and the process corner data.

[0008] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the chip screening method according to any embodiment of the present invention.

[0009] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing a computer program configured to cause a processor to execute and implement the chip screening method according to any embodiment of the present invention.

[0010] According to another aspect of the present invention, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the chip screening method described in any embodiment of the present invention.

[0011] The technical solution of this invention, in the chip testing phase, acquires the process corner data corresponding to each initial chip; acquires the target ambient temperature range and the target thermal design current upper limit value; and, through a pre-established target correlation model between ambient temperature, process corner, and thermal design current upper limit value, acquires the process corner limitation range based on the target ambient temperature range and the target thermal design current upper limit value; and, based on the process corner limitation range and process corner data, selects target chips from each initial chip; by using the pre-established target correlation model between ambient temperature, process corner, and thermal design current upper limit value, the ambient temperature range and thermal design current upper limit value are converted into a process corner limitation range, and chip selection in the chip testing phase is achieved based on the process corner limitation range. This enables chip selection based on the thermal design current upper limit, reduces performance fluctuations between chips, and ensures the operating efficiency of the chip cluster.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a flowchart of a chip screening method provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the chip structure provided in Embodiment 1 of the present invention; Figure 3 This is a flowchart of a chip screening method provided according to Embodiment 2 of the present invention; Figure 4 This is a schematic diagram of a chip screening device according to Embodiment 3 of the present invention; Figure 5 This is a schematic diagram of the structure of an electronic device that implements the chip screening method of this invention. Detailed Implementation

[0015] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0016] It should be noted that the terms "first," "second," "target," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0017] Example 1 Figure 1 This is a flowchart of a chip screening method provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where chip screening is implemented before GPU chips leave the factory, taking into account the thermal design current limit of the data transport unit. This method can be executed by a chip screening device, which can be implemented in hardware and / or software. Typically, this chip screening device can be configured in electronic devices, such as computer equipment, servers, etc. Figure 1 As shown, the method includes: S110. During the chip testing phase, acquire the process corner data corresponding to each initial chip.

[0018] In this embodiment, the chip structure can be as follows: Figure 2 As shown, the chip includes a computing unit, a power control microcontroller unit (MCU), a clock source, a power management unit, a memory unit, a data transmission unit, and a current detection unit. The computing unit is the core of the chip and also the unit with the highest current / power consumption. Its operating frequency directly determines its current output, so changing its operating frequency can control the chip's current to some extent. The MCU inside the computing unit can control the interface to read data from the current detection unit (i.e., the chip's current information) at a certain periodic frequency. It can also configure the clock source through registers to output a clock signal of a specific frequency.

[0019] The clock source generates a clock signal within a certain frequency range to supply the computing unit, storage unit, and data transmission unit. Both the data transmission unit and the computing unit support dynamic frequency adjustment, with their operating frequencies determined by the clock output from the clock source. The storage unit can be adjusted according to the operating frequency of the data transmission unit. A current detection unit is connected in series at the chip's input terminal to acquire the chip's current information in real time.

[0020] The chip testing phase can be the automatic test equipment (ATE) testing phase for GPU chips. In this embodiment, ATE testing can be used to obtain the process corner data corresponding to each initial chip. The process corner data can include typical-typical (TT), fast-fast (FF), slow-slow (SS), fast-slow (FS), and slow-fast (SF) process corners, etc. Various types of process corners can also be represented using the oscillation frequency of a ring oscillator (RO).

[0021] Process angle is a key parameter used in semiconductor manufacturing to characterize chip performance deviations. Essentially, it refers to the extreme or typical states of transistor electrical characteristics (such as threshold voltage and drive current) caused by process fluctuations such as photolithography, etching, and doping during the mass production process.

[0022] S120. Obtain the target ambient temperature range and the target thermal design current upper limit value, and obtain the process angle limit range based on the target ambient temperature range and the target thermal design current upper limit value through a pre-established target correlation model between ambient temperature, process angle and thermal design current upper limit value.

[0023] Specifically, firstly, an environmental monitoring system can be used to collect the operating ambient temperature of the chip in the actual application scenario of the data center, thereby obtaining the target ambient temperature range. Simultaneously, the pre-set target thermal design current upper limit value for the data transfer unit can be obtained. Next, the target ambient temperature range and the target thermal design current upper limit value can be substituted into a pre-established target correlation model between ambient temperature, process corner, and thermal design current upper limit value to calculate the process corner limitation range. Alternatively, based on the target ambient temperature range and the target thermal design current upper limit value, a matching search can be performed within the pre-established target correlation model between ambient temperature, process corner, and thermal design current upper limit value to obtain the process corner limitation range.

[0024] In this embodiment, correlation data between ambient temperature, process corner, dynamic current of data transfer unit, and chip leakage current can be collected in advance, and curve fitting can be performed on the collected correlation data to establish a target correlation model between ambient temperature, process corner, and upper limit of thermal design current. Alternatively, a correspondence between ambient temperature, process corner, and upper limit of thermal design current can be established in advance as a target correlation model.

[0025] S130. Based on the process angle limitation range and the process angle data, select the target chip from each initial chip.

[0026] Specifically, the process corner data for each initial chip is compared with the process corner limit range. Initial chips with process corner data exceeding the limit range are identified as performance deviation products and directly intercepted. Initial chips with process corner data within the limit range are identified as target chips, whose leakage current and dynamic current sum meet the thermal design current limit constraint, avoiding bandwidth degradation caused by triggering the thermal design current limit in actual applications, thus ensuring performance consistency between chips. This screening mechanism enables accurate interception of substandard chips in the early stages of production, significantly reducing subsequent production and application costs.

[0027] The selection of target chips from the initial chips based on the process angle limitation range and the process angle data may include: If the process corner data corresponding to the current initial chip is detected to be within the process corner limit range, then the current initial chip is determined as the target chip.

[0028] Specifically, if the process corner data corresponding to an initial chip is within the process corner limit range, it means that its performance meets the performance requirements, and thus it can be identified as a target chip. For example, if the process corner limit range is TT, FF, and SS process corners, if the process corner corresponding to the initial chip is any one of the three, it can be identified as a target chip; if it is not any one of the three, it can be intercepted.

[0029] It's important to note that to reduce inter-card performance fluctuations and prevent the performance of multi-card clusters from being affected by underperforming cards, it's crucial to identify chips with performance deviations early in the chip manufacturing process. Early detection can significantly reduce production costs. Process corner information can be obtained during the die testing phase of ATE CP (Chip Probing). Through theoretical analysis and data fitting with a certain sample size, the relationship between process corners and performance bottlenecks can be established. Based on the requirements for inter-card performance consistency, a performance screening mechanism can be established during the die screening stage based on process corner information. This can eliminate chips that do not meet the requirements to a certain extent, avoiding the problem of performance deviations only being discovered during actual chip testing. The performance testing and identification process can be further advanced, reducing testing and manufacturing costs across multiple production stages.

[0030] The technical solution of this invention, in the chip testing phase, acquires the process corner data corresponding to each initial chip; acquires the target ambient temperature range and the target thermal design current upper limit value; and, through a pre-established target correlation model between ambient temperature, process corner, and thermal design current upper limit value, acquires the process corner limitation range based on the target ambient temperature range and the target thermal design current upper limit value; and, based on the process corner limitation range and process corner data, selects target chips from each initial chip; by using the pre-established target correlation model between ambient temperature, process corner, and thermal design current upper limit value, the ambient temperature range and thermal design current upper limit value are converted into a process corner limitation range, and chip selection in the chip testing phase is achieved based on the process corner limitation range. This enables chip selection based on the thermal design current upper limit, reduces performance fluctuations between chips, and ensures the operating efficiency of the chip cluster.

[0031] Example 2 Figure 3The flowchart of a chip screening method provided in the second embodiment of the present invention. This embodiment further refines the above technical solution, and the technical solution in this embodiment can be combined with one or more of the above embodiments. As Figure 3 shown, the method includes: S210. In the chip testing stage, obtain the process corner data corresponding to each initial chip.

[0032] S220. Obtain the target environmental temperature range and the upper limit value of the target thermal design current, establish a first correlation model between the dynamic current, operating frequency and process corner of the data transfer unit in the chip, and establish a second correlation model between the dynamic current, chip leakage current and the upper limit of the thermal design current.

[0033] In this embodiment, when establishing the target correlation model, curve fitting methods can be used, for example, linear fitting method, polynomial fitting method, etc., to pre-establish the first correlation model between the dynamic current I_dynamic, operating frequency F and process corner RO of the data transfer unit. At the same time, the sum of the dynamic current I_dynamic and the chip leakage current I_leakage needs to be less than the upper limit of the thermal design current TDC_limit. Based on this, a second correlation model between the dynamic current, chip leakage current and the upper limit of the thermal design current can be established, that is, I_leakage + I_dynamic < TDC_limit. I_leakage is a function model with environmental temperature and process corner as variables, which can be set in advance.

[0034] Among them, establishing the first correlation model between the dynamic current, operating frequency and process corner of the data transfer unit in the chip may include: Collect the correlation data between the dynamic current, operating frequency and process corner, and use the polynomial fitting method to establish the first correlation model between the dynamic current, operating frequency and process corner according to the correlation data between the dynamic current, operating frequency and process corner.

[0035] It should be noted that as the core component of data transmission in the chip, the dynamic current I_dynamic of the data transfer unit directly affects the data transmission bandwidth and the redundancy of the thermal design current. Through theoretical analysis and experimental verification, the dynamic current I_dynamic of the data transfer unit is directly proportional to the data path operating frequency F, operating voltage Vset, load capacitance C and data transfer bandwidth A as follows: I_dynamic (C Vset F A).

[0036] The load capacitance C is determined by the hardware design of the data transfer unit and is a fixed parameter. The data transfer bandwidth A represents the maximum amount of data transferred between different storage levels, modules, or devices per unit time. It is a core indicator for measuring the transmission efficiency of the data transfer unit, directly determining the data transfer rate and thus affecting the parallel computing efficiency of the GPU cluster. Especially in data-intensive tasks, data transfer bandwidth often becomes a critical bottleneck for system performance. Therefore, the data transfer bandwidth A can, to a certain extent, directly characterize the actual application performance of the GPU chip.

[0037] When the data transfer bandwidth A reaches the upper limit of the software design's expected optimization, based on the linear relationship between the process angle RO and the operating voltage Vset, the first correlation model between the dynamic current I_dynamic, the operating frequency F, and the process angle RO can be derived, namely, I_dynamic = fmax(F, RO). Here, fmax() is a function characterizing the positive correlation between I_dynamic and the operating frequency F and the process angle RO. Its specific expression can be determined by collecting a large amount of correlation data between dynamic current, operating frequency, and process angle, and then using a polynomial fitting method to fit the collected data. This expression needs to ensure that the model accurately reflects the variation of dynamic current with process angle and operating frequency.

[0038] The advantage of the above settings is that they can ensure the accuracy of the correlation model between dynamic current, operating frequency and process angle, so that the correlation model conforms to the actual change law.

[0039] S230. Based on the first correlation model and the second correlation model, establish a target correlation model between ambient temperature, process angle and upper limit of thermal design current.

[0040] Next, the first and second correlation models can be combined to jointly establish a target correlation model between ambient temperature, process angle, and upper limit of thermal design current.

[0041] The target correlation model established based on the first correlation model and the second correlation model, relating ambient temperature, process angle, and upper limit of thermal design current, may include: A third correlation model is established between the operating voltage and the process corner, and based on the third correlation model, a fourth correlation model is established between the process corner, ambient temperature and chip leakage current. Based on the first correlation model, the second correlation model, and the fourth correlation model, a target correlation model is established between ambient temperature, process angle, and upper limit of thermal design current.

[0042] In the actual application scenario of the chip, when the computing unit is at a specific operating frequency, there is a significant linear correlation between the process corner RO and the operating voltage Vset. Based on this, a third correlation model between the operating voltage and the process corner can be established, and its mathematical expression is Vset = K0 RO + B0. Here, K0 represents the slope of the fitting curve, and B0 represents the offset value of the fitting curve. It should be noted that in order to ensure the safety of the chip's operating voltage, B0 needs to be set with a sufficient safety threshold.

[0043] In this embodiment, the curve fitting method can be used to fit the correlation data among the operating voltage, ambient temperature, and chip leakage current to establish a correlation model among the operating voltage, ambient temperature, and chip leakage current. Then, by combining this correlation model with the third correlation model, a fourth correlation model among the process corner RO, ambient temperature TEMP, and chip leakage current I_leakage can be obtained. The fourth correlation model can be expressed as I_leakage = f(RO, TEMP). Finally, by combining I_leakage = f(RO, TEMP), I_dynamic = fmax(F, RO), and I_leakage + I_dynamic < TDC_limit, the target correlation model among the ambient temperature, process corner, and upper limit of the thermal design current can be obtained, that is, f(RO, Temp) + fmax(F, RO) < TDC_limit. Among them, based on the analysis of the data defined by the actual product, the operating frequency F can be a preset fixed value. Thus, after obtaining the target ambient temperature range and the target upper limit value of the thermal design current, by substituting the above target correlation model, the process corner limit range can be calculated.

[0044] The advantage of the above setting is that it can ensure the accuracy of the target correlation model and improve the accuracy of the process corner limit range.

[0045] Among them, according to the third correlation model, establishing the fourth correlation model among the process corner, ambient temperature, and chip leakage current may include: Establishing a fifth correlation model among the operating voltage, process corner, and chip leakage current, and establishing an initial correlation model among the process corner, ambient temperature, and chip leakage current; According to the third correlation model, the fifth correlation model, and the initial correlation model, establishing the fourth correlation model among the process corner, ambient temperature, and chip leakage current.

[0046] In this embodiment, the correlation data among the operating voltage, process corner, and chip leakage current can be collected and fitted to establish a fifth correlation model among the operating voltage, process corner, and chip leakage current, and its mathematical expression is log10(I_leakage) = K2 Vset+f2(RO). Where K2 represents the slope of the fitted curve, and f2() represents the offset function of the fitted curve. Its specific form is determined by fitting measured data to ensure that the model can accurately reflect the leakage current variation under different process angles and different operating voltages.

[0047] Simultaneously, it can collect correlation data between process corner, ambient temperature, and chip leakage current, and perform fitting processing on the collected data to establish an initial correlation model between process corner, ambient temperature, and chip leakage current. The mathematical expression is log10(I_leakage)=K1 TEMP+f1(RO). Where K1 represents the slope of the fitted curve, and f1() represents the offset function of the fitted curve. Its specific form is also determined by polynomial fitting of the measured data. During the fitting process, it is necessary to ensure that the model has good adaptability to leakage current data under different process angles and different temperature conditions.

[0048] It should be noted that the initial correlation model primarily considers the linear relationship between ambient temperature and chip leakage current, with the process angle only involving the offset term. Therefore, this embodiment further incorporates a third correlation model, Vset=K0, based on the initial correlation model. RO+B0, and the fifth correlation model log10(I_leakage)=K2 Vset+f2(RO) is used to derive the fourth correlation model between process corner, ambient temperature, and chip leakage current, namely I_leakage=f(RO,TEMP). This embodiment does not specify the specific form of the f() function.

[0049] The advantage of the above settings is that they can ensure the accuracy of the correlation model between process corner, ambient temperature and chip leakage current, and improve the accuracy of the target correlation model.

[0050] S240. By using a pre-established target correlation model between ambient temperature, process angle and upper limit of thermal design current, obtain the process angle limit range based on the target ambient temperature range and the target upper limit of thermal design current.

[0051] S250. Based on the process angle limitation range and the process angle data, select the target chip from each initial chip.

[0052] In this embodiment, by fitting actual data and performing theoretical calculations, the inherent correlation between process corners in semiconductor manufacturing and the actual application performance of GPU cards is identified, providing a core theoretical basis for predicting GPU performance. During the chip testing phase, a performance screening mechanism is established based on process corner information to preemptively filter out chips with excessive performance deviations, achieving early control of GPU performance and significantly reducing production costs. By accurately identifying GPU chips whose performance is substandard due to thermal design current limitations, the system avoids such GPU chips slowing down the entire cluster's application efficiency after being connected to the cluster, ensuring the consistency of dynamic load performance of the GPU cluster.

[0053] The technical solution of this invention establishes a first correlation model between the dynamic current, operating frequency and process angle of the data transport unit in the chip, and a second correlation model between the dynamic current, chip leakage current and thermal design current limit. Based on the first and second correlation models, a target correlation model between ambient temperature, process angle and thermal design current limit is established. By adopting a multi-level correlation model establishment method, the accuracy of the target correlation model can be improved, thereby improving the accuracy of chip selection.

[0054] Example 3 Figure 4 This is a schematic diagram of a chip screening device provided in Embodiment 3 of the present invention. Figure 4 As shown, the device includes: a data acquisition module 310, a range acquisition module 320, and a chip screening module 330; wherein, The data acquisition module 310 is used to acquire the process corner data corresponding to each initial chip during the chip testing phase. The range acquisition module 320 is used to acquire the target ambient temperature range and the target thermal design current upper limit value, and to acquire the process angle limit range based on the target ambient temperature range and the target thermal design current upper limit value through a pre-established target correlation model between ambient temperature, process angle and thermal design current upper limit value. The chip screening module 330 is used to screen target chips from the initial chips according to the process corner limit range and the process corner data.

[0055] The technical solution of this invention, in the chip testing phase, acquires the process corner data corresponding to each initial chip; acquires the target ambient temperature range and the target thermal design current upper limit value; and, through a pre-established target correlation model between ambient temperature, process corner, and thermal design current upper limit value, acquires the process corner limitation range based on the target ambient temperature range and the target thermal design current upper limit value; and, based on the process corner limitation range and process corner data, selects target chips from each initial chip; by using the pre-established target correlation model between ambient temperature, process corner, and thermal design current upper limit value, the ambient temperature range and thermal design current upper limit value are converted into a process corner limitation range, and chip selection in the chip testing phase is achieved based on the process corner limitation range. This enables chip selection based on the thermal design current upper limit, reduces performance fluctuations between chips, and ensures the operating efficiency of the chip cluster.

[0056] Optionally, the chip screening device also includes: The first model building module is used to build a first correlation model between the dynamic current, operating frequency and process corner of the data transport unit in the chip, and to build a second correlation model between the dynamic current, chip leakage current and thermal design current upper limit. The second model building module is used to establish a target correlation model between ambient temperature, process angle and upper limit of thermal design current based on the first correlation model and the second correlation model.

[0057] Optional, the second model building module includes: The first model building unit is used to build a third correlation model between the operating voltage and the process corner, and based on the third correlation model, to build a fourth correlation model between the process corner, ambient temperature and chip leakage current. The second model building unit is used to establish a target correlation model between ambient temperature, process angle and upper limit of thermal design current based on the first correlation model, the second correlation model and the fourth correlation model.

[0058] Optionally, the first model building unit is specifically used to build a fifth correlation model between operating voltage, process corner and chip leakage current, and to build an initial correlation model between process corner, ambient temperature and chip leakage current. Based on the third correlation model, the fifth correlation model, and the initial correlation model, a fourth correlation model is established between process corner, ambient temperature, and chip leakage current.

[0059] Optionally, the first model building module is specifically used to collect correlation data between dynamic current, operating frequency and process angle, and to establish a first correlation model between dynamic current, operating frequency and process angle using a polynomial fitting method based on the correlation data between dynamic current, operating frequency and process angle.

[0060] Optionally, the chip screening module 330 is specifically used to determine the current initial chip as the target chip if the process corner data corresponding to the current initial chip is detected to be within the process corner limit range.

[0061] The chip screening device provided in the embodiments of the present invention can execute the chip screening method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0062] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0063] Example 4 Figure 5 A schematic diagram of an electronic device 40 that can be used to implement embodiments of the present invention is shown. The electronic device 40 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device 40 can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0064] like Figure 5 As shown, the electronic device 40 includes at least one processor 41 and a memory, such as a read-only memory (ROM) 42 or a random access memory (RAM) 43, communicatively connected to the at least one processor 41. The memory stores computer programs executable by the at least one processor. The processor 41 can perform various appropriate actions and processes based on the computer program stored in the read-only memory 42 or loaded from the storage unit 48 into the random access memory 43. The RAM 43 can also store various programs and data required for the operation of the electronic device 40. The processor 41, ROM 42, and RAM 43 are interconnected via a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0065] Multiple components in electronic device 40 are connected to I / O interface 45, including: input unit 46, such as keyboard, mouse, etc.; output unit 47, such as various types of monitors, speakers, etc.; storage unit 48, such as disk, optical disk, etc.; and communication unit 49, such as network card, modem, wireless transceiver, etc. Communication unit 49 allows electronic device 40 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0066] Processor 41 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 41 include, but are not limited to, central processing units, graphics processing units, various special-purpose artificial intelligence computing chips, various processors running machine learning model algorithms, digital signal processors, and any suitable processor, controller, microcontroller, etc. Processor 41 performs the various methods and processes described above, such as chip screening methods.

[0067] In some embodiments, the chip screening method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 48. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 40 via ROM 42 and / or communication unit 49. When the computer program is loaded into RAM 43 and executed by processor 41, one or more steps of the chip screening method described above may be performed. Alternatively, in other embodiments, processor 41 may be configured to perform the chip screening method by any other suitable means (e.g., by means of firmware).

[0068] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays, application-specific integrated circuits (ASICs), application-specific standard products (ASICs), system-on-a-chip (SoCs), complex programmable logic devices, computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0069] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0070] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory, read-only memory, erasable programmable read-only memory, optical fibers, portable compact disk read-only memory, optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0071] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device 40, which includes: a display device (e.g., a cathode ray tube or liquid crystal display) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device 40. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0072] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0073] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact via a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server.

[0074] This embodiment may also include a computer program product, which includes a computer program that, when executed by a processor, implements the chip screening method provided in any embodiment of the present invention.

[0075] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0076] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A chip screening method, characterized in that, include: During the chip testing phase, process corner data corresponding to each initial chip is acquired; Obtain the target ambient temperature range and the target thermal design current upper limit, and obtain the process angle limit range based on the target ambient temperature range and the target thermal design current upper limit by using a pre-established target correlation model between ambient temperature, process angle and thermal design current upper limit; Based on the process angle limit range and the process angle data, the target chip is selected from each initial chip.

2. The method according to claim 1, characterized in that, Before obtaining the process angle limitation range based on the target ambient temperature range and the target thermal design current limit value using a pre-established target correlation model between ambient temperature, process angle, and upper limit of thermal design current, the process angle limitation range is further included: A first correlation model is established between the dynamic current, operating frequency and process corner of the data transport unit in the chip, and a second correlation model is established between the dynamic current, chip leakage current and upper limit of thermal design current. Based on the first correlation model and the second correlation model, a target correlation model is established between ambient temperature, process angle and upper limit of thermal design current.

3. The method according to claim 2, characterized in that, Based on the first correlation model and the second correlation model, a target correlation model is established between ambient temperature, process angle, and upper limit of thermal design current, including: A third correlation model is established between the operating voltage and the process corner, and based on the third correlation model, a fourth correlation model is established between the process corner, ambient temperature and chip leakage current. Based on the first correlation model, the second correlation model, and the fourth correlation model, a target correlation model is established between ambient temperature, process angle, and upper limit of thermal design current.

4. The method according to claim 3, characterized in that, Based on the third correlation model, a fourth correlation model is established between process corner, ambient temperature, and chip leakage current, including: A fifth correlation model is established between operating voltage, process corner, and chip leakage current, and an initial correlation model is established between process corner, ambient temperature, and chip leakage current. Based on the third correlation model, the fifth correlation model, and the initial correlation model, a fourth correlation model is established between process corner, ambient temperature, and chip leakage current.

5. The method according to claim 2, characterized in that, Establish a first correlation model between the dynamic current, operating frequency, and process corner of the data transport unit in the chip, including: Data on the correlation between dynamic current, operating frequency, and process angle are collected. Based on this correlation data, a first correlation model is established using a polynomial fitting method.

6. The method according to claim 1, characterized in that, Based on the process corner limit range and the process corner data, target chips are selected from the initial chips, including: If the process corner data corresponding to the current initial chip is detected to be within the process corner limit range, then the current initial chip is determined as the target chip.

7. A chip screening device, characterized in that, include: The data acquisition module is used to acquire the process corner data corresponding to each initial chip during the chip testing phase. The range acquisition module is used to acquire the target ambient temperature range and the target thermal design current upper limit value, and to acquire the process angle limit range based on the target ambient temperature range and the target thermal design current upper limit value through a pre-established target correlation model between ambient temperature, process angle and thermal design current upper limit value. The chip screening module is used to screen target chips from the initial chips according to the process corner limit range and the process corner data.

8. An electronic device, characterized in that, The electronic device includes: At least one processor, and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the chip screening method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the chip screening method according to any one of claims 1-6.

10. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the chip screening method according to any one of claims 1-6.

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