Memory system

Abstract

In a memory system (100, 100a), a memory controller issues a command including an extension flag field (F3) and a bank address field (F2) as a precharge command to a semiconductor memory device, the extension flag field (F3) specifying: which one of one, all, and two banks belonging to mutually different bank groups is precharged; and a second relative processing timing for the first bank in the case of two banks. In the case of two banks, the semiconductor memory device precharges the first bank determined by the bank address field, and precharges the second bank of a bank address obtained by inverting the inversion target bits in the bank address field at the relative processing timing.

Description

Technical Field

[0001] This disclosure relates to memory systems. Background Technology

[0002] As semiconductor memory devices, DDR4 and LPDDR5, which have multiple memory bank groups, are sometimes used. In such semiconductor memory devices, when activation commands are issued consecutively to two memory banks belonging to different memory bank groups, the interval that must be set between the issuance of the two activation commands can be shortened (Non-Patent Document 1, Non-Patent Document 2). Therefore, activation commands and read / write commands can be issued continuously without creating idle cycles in the command bus.

[0003] Existing technical documents Non-patent literature Non-Patent Document 1: JEDEC STANDARD DDR4 SDRAM JESD79-4B, JUNE 2017 Non-Patent Document 2: JEDEC STANDARD Low Power Double Data Rate 5 (LPDDR5) JESD209-5B June 2021 Summary of the Invention

[0004] However, when activation and read / write commands are issued consecutively, the idle time of the command bus used to issue refresh or precharge commands is reduced. If the issuance of activation and read / write commands is delayed to issue refresh or precharge commands, the data access performance of the semiconductor memory device will be reduced. Therefore, a technique is desired that can efficiently utilize the command bus while ensuring the timing of refresh or precharge command issuance.

[0005] As one aspect of this disclosure, a memory system is provided, comprising: a semiconductor memory device having a plurality of memory banks; and a memory controller that issues commands to the semiconductor memory device based on an access request from an arithmetic device accessing the semiconductor memory device. In this memory system, the memory controller issues a command to the semiconductor memory device, including an extended flag field and a memory bank address field, as a precharge command, wherein the extended flag field is a bit string specifying: precharging one memory bank, precharging all memory banks, and precharging two memory banks belonging to different memory bank groups; and a second relative processing timing for the first memory bank in the case of precharging two memory banks, wherein the memory bank address field is a bit string determining the memory bank address to be precharged. When the semiconductor memory device specifies that two memory banks should be precharged via the precharge command, it performs precharge on the first memory bank determined by the memory bank address field, and performs precharge on the second memory bank determined by the following memory bank address at the corresponding processing timing specified by the extended flag field, wherein the memory bank address is obtained by inverting a predetermined bit, i.e., the inverted object bit, in the bit string of the memory bank group determined in the memory bank address field.

[0006] According to this memory system, when precharging two memory banks is specified via a precharge command, both the first and second memory banks can be precharged with a single precharge command. Therefore, the issuance of the precharge command can be suppressed, creating idle time on the command bus. Thus, the command bus can be used effectively while ensuring the timing of the precharge command issuance.

[0007] As another aspect of this disclosure, a memory system is provided, comprising: a semiconductor memory device having a plurality of memory banks; and a memory controller that issues commands to the semiconductor memory device based on an access request from an arithmetic device accessing the semiconductor memory device. In this memory system, the memory controller issues a command to the semiconductor memory device as a refresh command, including an extended flag field and a memory bank address field, wherein the extended flag field is a bit string specifying either refreshing all memory banks or refreshing two memory banks belonging to mutually different memory bank groups; and a second relative processing timing for the first memory bank in the case of refreshing two memory banks, and the memory bank address field is a bit string determining the memory bank to be refreshed. When the semiconductor memory device specifies that two memory banks should be refreshed via the refresh command, the first memory bank, determined by the memory bank address field, is selected as the target for refresh, and the second memory bank, determined by the memory bank address, is selected as the target for refresh at the corresponding processing time specified by the extended flag field. The memory bank address is obtained by inverting a predetermined bit, i.e., the inverted object bit, in the bit string of the determined memory bank group in the memory bank address field.

[0008] According to this memory system, when a refresh command specifies that two memory banks should be refreshed, both the first and second memory banks can be refreshed with a single refresh command. Therefore, the issuance of refresh commands can be suppressed, creating idle time on the command bus. Thus, the command bus can be used effectively while ensuring the timely issuance of refresh commands. Attached Figure Description

[0009] Figure 1 This is a block diagram showing the general configuration of a memory system as an embodiment of the present disclosure.

[0010] Figure 2 This is a flowchart showing the sequence of pre-charge processing.

[0011] Figure 3 This is an explanatory diagram showing the data format of the precharge command in this embodiment.

[0012] Figure 4 This is an explanatory diagram showing the contents of the extended flags field in the precharge command.

[0013] Figure 5 This is a flowchart showing the order of refresh processing.

[0014] Figure 6 This is an explanatory diagram showing the data format of the refresh command in this embodiment.

[0015] Figure 7 This is an illustration showing the contents of the extended flags field in the refresh command.

[0016] Figure 8 This is a timing diagram illustrating an example of the operation of the memory system in this embodiment and comparative examples.

[0017] Figure 9 This is a timing diagram illustrating another example of the operation of the memory system in this embodiment.

[0018] Figure 10 This is a block diagram showing the general configuration of the memory system in the second embodiment.

[0019] Figure 11 This is an explanatory diagram illustrating an example of the settings in the extended flag field, the first register, and the second register in the second embodiment. Detailed Implementation

[0020] A. First implementation method: A1. System Composition: like Figure 1 As shown, the memory system 100 of the first embodiment includes a memory controller 110 and a semiconductor memory device 120. The memory system 100 performs read and write operations on the semiconductor memory device 120 via the memory controller 110 based on access requests issued from the computing device 200. The computing device 200 is, for example, equivalent to a CPU or a GPU (Graphics Processing Unit).

[0021] The memory controller 110 is connected to the arithmetic unit 200 via bus 10 and receives access requests for the semiconductor memory device 120 from the arithmetic unit 200. Furthermore, the memory controller 110 is connected to the semiconductor memory device 120 via command bus 20 and issues commands, represented by bit strings, to the semiconductor memory device 120 in response to access requests. The memory controller 110 issues these commands according to a clock signal that serves as the reference for the operation of the memory system 100. In addition, the memory controller 110 performs translation from the logical address of the data accessed by commands such as read, write, and activate to the physical address of the storage area on the semiconductor memory device 120 where the data is stored.

[0022] Specifically, when the access request is a write access request requesting the writing of data to the semiconductor memory device 120, the memory controller 110 issues a write command to the semiconductor memory device 120 instructing it to write data to the address specified by the access request (hereinafter also referred to as the "access target address"). Conversely, when the access request is a read access request requesting the reading of data from the semiconductor memory device 120, the memory controller 110 issues a read command to the semiconductor memory device 120 instructing it to read data from the access target address. Both the write command and the read command include a column address section that specifies the column address within the access target address.

[0023] Before issuing a write command or a read command to the semiconductor memory device 120, the memory controller 110 issues an activation command to the semiconductor memory device 120 to bring the semiconductor memory device 120 into an accessible state (hereinafter also referred to as "activation"). The activation command includes a memory bank quantity specification portion, a memory bank address portion, and a row address portion.

[0024] In this embodiment, the memory system 100 includes DRAM (Dynamic Random Access Memory) based on the so-called LPDDR5 standard, which can issue precharge commands and refresh commands upon access requests. The precharge command requests the execution of a "precharge," which involves disconnecting the FET switches between all bit lines and the capacitors of each memory cell, charging the bit lines to Vdd / 2. The refresh command requests the execution of a "refresh," which involves periodically injecting charge into the capacitors of each memory cell to replenish the charge leaking from the capacitors and maintain the stored information.

[0025] The semiconductor memory device 120 is formed by arranging memory cells, which serve as storage elements, in a matrix. Based on commands issued from the memory controller 110, it can perform various operations such as writing data to each memory cell, reading data from each memory cell, precharging, and refreshing. As described above, the semiconductor memory device 120 of this embodiment is LPDDR5, and the semiconductor memory device 120 includes memory banks BG0 to BG3. Each memory bank group BG0 to BG3 has four memory banks: memory bank group BG0 has memory banks B0 to B3, memory bank group BG1 has memory banks B4 to B7, memory bank group BG2 has memory banks B8 to B11, and memory bank group BG3 has memory banks B12 to B15.

[0026] In the semiconductor memory device 120, the memory controller 110 issues the aforementioned precharge command and refresh command to the semiconductor memory device 120. A predetermined time, referred to as tRP, is defined as the shortest period from issuing the precharge command to issuing the next precharge command. Furthermore, a refresh command is issued every predetermined period (interval), referred to as tREFi. Additionally, a minimum period from the completion of the precharge operation to the start of the refresh operation is preset. The memory controller 110 issues the precharge command and refresh command to the semiconductor memory device 120 according to these preset periods. If a precharge command is received in the semiconductor memory device 120, the precharge process described later is executed. Similarly, if a refresh command is received in the semiconductor memory device 120, the refresh process described later is executed.

[0027] A2. Pre-charge process: Figure 2 The precharge process shown is a process for performing precharge in the semiconductor memory device 120, as described above, when a precharge command is received from the memory controller 110.

[0028] The semiconductor memory device 120 determines whether the value of the extended flag field of the received precharge command is "000" or "001" (step S15). Hereinafter, "step S" will be referred to simply as "S".

[0029] like Figure 3 As shown, the precharge command in this embodiment includes a command field F1, a memory address field F2, and an extended flag field F3. The command field F1 is a field indicating the type of command, consisting of a total of 7 bits, from bits b8 to b14. Figure 3 The “0001111” shown indicates a precharge command. The memory address field F2 is the field representing the memory bank, consisting of 4 bits from b4 to b7. “0000” in the memory address field F2 indicates memory bank B0, and “1111” indicates memory bank B15.

[0030] The extended flag field F3 is a field that represents the number of memory banks to be precharged and the time difference when precharging two memory banks, as described later. It consists of bits b1 to b3. More specifically, the extended flag field F3 is a field that specifies (i) and (ii) below.

[0031] (i) Precharging one memory bank, precharging all memory banks, or precharging two memory banks belonging to different memory bank groups.

[0032] (ii) Second relative processing timing for the first memory bank in the case of precharging both memory banks.

[0033] Figure 4 The following shows a specific setting example for the extended flag field F3 in the precharge command. The settings for each value from “000” to “111” are explained below.

[0034] • "000": Indicates that the storage bank of the precharged object is only one of the storage banks specified by the storage bank address field F2. Regarding (ii) above, since it is not an object, no specific value is set.

[0035] • "001": Indicates that the storage of the precharged object is all storage. In this case, the storage address specified in the storage address field F2 becomes invalid. Similar to "000" above, regarding "001", (ii) above is also a non-object, so no specific value is set.

[0036] • "010": Indicates that the memory bank to be precharged is two memory banks. The relative processing timing in (ii) above means simultaneous, that is, precharging is performed on both memory banks at the same time.

[0037] • "011": Indicates that the memory bank for precharging is two memory banks. Additionally, it is shown that the relative processing timing in (ii) above is a timing delay of one clock cycle from the start of precharging of the first memory bank. "Cycle" refers to a period within a clock cycle.

[0038] • "100": Indicates that the storage of the precharged object is two storage banks. Additionally, the relative processing timing in (ii) above is shown as a timing delay of two cycles from the start of precharging of the first storage bank.

[0039] • "101": Indicates that the storage of the precharged object is two storage banks. Additionally, the relative processing timing in (ii) above is shown as a timing delay of three cycles from the start of precharging of the first storage bank.

[0040] • "110": Indicates that the storage of the precharged object is two storage banks. Additionally, the relative processing timing in (ii) above is shown as a timing delay of four cycles from the start of precharging of the first storage bank.

[0041] • "111": Indicates that the storage of the precharged object is two storage banks. Additionally, the relative processing timing in (ii) above is shown as a timing delay of five cycles from the start of precharging of the first storage bank.

[0042] Here, bits b1 to b3 of the extended flag field F3 have the same meaning as the lowest three bits in the precharge command in conventional LPDDR5. That is, conventionally, when the lowest three bits are "000", it means that only one memory bank specified in the memory bank address will be the target of precharge. Conversely, when the lowest three bits are "001", it means that all memory banks will be the target of precharge. Therefore, the purpose of using these lowest three bits is the same as in conventional systems, thus ensuring compatibility. Furthermore, details regarding the two memory banks that become the target of precharge when the extended flag field F3 is "010" to "111" will be described later.

[0043] like Figure 2 As shown, if the value of the extended flag field F3, which is determined to be a received precharge command, is “000” or “001” (S15: YES), the semiconductor memory device 120 determines whether the value of the extended flag field F3 is “000” (S20).

[0044] If the value of the extended flag field F3 is determined to be “000” (S20: YES), the semiconductor memory device 120 will only perform precharging on the memory bank specified by the memory bank address field F2 (S25).

[0045] If the value of the extended flag field F3 is determined to be "000" (S20: NO), in which case the value of the extended flag field F3 is "001", the semiconductor memory device 120 performs precharging on the entire memory bank as an object (S30).

[0046] In the above-mentioned S15, if the value of the extended flag field F3 of the received precharge command is not "000" or "001" (S15: NO), that is, if it is any one of "010" to "111", the semiconductor memory device 120 will perform precharge on the memory bank (hereinafter also referred to as "first memory bank") specified by the memory bank address field F2 as the object (S35).

[0047] Semiconductor memory device 120 performs a precharge (S40) targeting a second memory bank with a delay specified by the extended flag field F3. In this embodiment, the "second memory bank" refers to the memory bank determined by the memory bank address obtained by inverting a predetermined 1-bit inversion target bit in the bit string (bits b4~b7) that determines the memory bank group. In this embodiment, the "inversion target bit" is bit b7, which is the highest bit in the memory bank address field F2. Therefore, for example, when the memory bank address field F2 is "0000", the first memory bank is memory bank B0, and the second memory bank is the memory bank represented by "1000", i.e., memory bank B7. For example, when the value of the memory bank address field F2 is "0111" and the value of the extended flag field F3 is "111", as the first memory bank, the precharge of memory bank B6 is performed immediately, and then, with a delay of five clock cycles, the precharge of memory bank B15 (1111) is performed as the second memory bank.

[0048] After completing S25, S30, and S40 as described above, the precharge process ends. As mentioned above, when a precharge command is received, precharge of two memory banks can be performed according to the value specified in the extended flag field F3. Therefore, compared with the configuration that requires sending and receiving precharge commands specifying each memory bank, the issuance of precharge commands can be suppressed, and efficient utilization of the command bus 20 can be achieved.

[0049] A3. Refresh Processing: Figure 5 The refresh process shown is a process for performing a refresh in the semiconductor memory device 120, as described above, when a refresh command is received from the memory controller 110.

[0050] Semiconductor memory device 120 determines whether the value of the extended flag field of the received refresh command is “000” or “001” (S55).

[0051] like Figure 6 As shown, the refresh command in this embodiment has the same format as the precharge command described above. Specifically, the refresh command includes a command field F1, a memory address field F2, and an extended flag field F3. The command field F1 is a field indicating the type of command, consisting of a total of 7 bits, from bits b8 to b14. Figure 6 The "0001110" shown indicates a refresh command. The memory address field F2 is the same as the memory address field F2 of the precharge command mentioned above.

[0052] The extended flag field F3 is the same as the extended flag field F3 of the precharge command described above, consisting of 3 bits b1 to b3. However, the content shown is different from the extended flag field F3 of the precharge command.

[0053] The extended flag field F3 of the refresh command is a field that indicates the number of memory banks to be refreshed and the time difference when refreshing two memory banks (described later). More specifically, the extended flag field F3 specifies the following (i) and (ii): (i) refreshing all memory banks and refreshing either of two memory banks belonging to different memory bank groups. (ii) a second relative processing timing for the first memory bank when refreshing two memory banks.

[0054] Figure 7 This shows a specific setting example for the extended flag field F3 in the refresh command. The following explains the settings for each value from “000” to “111”.

[0055] • "000": This indicates that the memory bank for refreshing the object is a combination of the memory bank specified by the memory bank address field F2 (the first memory bank) and the memory bank obtained by inverting the bits of the inverted object (the second memory bank). The relative processing timing in (ii) above means simultaneous, that is, precharging is performed on both memory banks at the same time.

[0056] • "001": Indicates that the memory of the refreshed object is all memory. In this case, the memory address specified in the memory address field F2 becomes invalid.

[0057] • "010": Indicates that the refresh object has two memory banks. Additionally, the relative processing timing in (ii) above is shown as a timing delay of one cycle from the start of the refresh of the first memory bank.

[0058] • "011": Indicates that the memory of the refresh object consists of two memory banks. Additionally, the relative processing timing in (ii) above is shown as a timing delay of two cycles from the start of the refresh of the first memory bank.

[0059] • "100": Indicates that the memory of the refresh object consists of two memory banks. Additionally, the relative processing timing in (ii) above is shown as a timing delay of three cycles from the start of the refresh of the first memory bank.

[0060] • "101": Indicates that the memory of the refresh object is two memory banks. Additionally, the relative processing timing in (ii) above is shown as a timing delay of four cycles from the start of the refresh of the first memory bank.

[0061] • "110": Indicates that the memory bank of the refresh object is two memory banks. Additionally, the relative processing timing in (ii) above is shown as a timing delay of five cycles from the start of the refresh of the first memory bank.

[0062] • "111": Indicates that the memory bank of the refresh object is two memory banks. Additionally, the relative processing timing in (ii) above is shown as a timing delay of six cycles from the start of the refresh of the first memory bank.

[0063] When the extended flag field F3 is "010" to "111", the two memory banks targeted for refresh are the same as the first and second memory banks in the aforementioned precharge command. Here, bits b1 to b3 of the extended flag field F3 of the refresh command have the same meaning as the lowest three bits in the conventional LPDDR5 refresh command. That is, conventionally, when the lowest three bits are "000", it means that both the first and second memory banks specified in the memory address are refreshed simultaneously. Furthermore, when the lowest three bits are "001", it means that all memory banks are refreshed. Therefore, the purpose of using these lowest three bits is the same as in the conventional system, thus ensuring compatibility.

[0064] like Figure 5 As shown, if the value of the extended flag field F3, which is determined to be a received refresh command, is “000” or “001” (S55: YES), the semiconductor memory device 120 determines whether the value of the extended flag field F3 is “000” (S60).

[0065] If the value of the extended flag field F3 is determined to be “000” (S60: YES), the semiconductor memory device 120 performs a refresh on the first and second memory banks specified by the memory bank address field F2 (S65).

[0066] If the value of the extended flag field F3 is determined to be "000" (S60: NO), then the value of the extended flag field F3 is "001", and the semiconductor memory device 120 performs a refresh on the entire memory bank (S70).

[0067] In the above-described S55, if the value of the extended flag field F3 of the received precharge command is not "000" or "001" (S55: NO), that is, if it is any one of "010" to "111", the semiconductor memory device 120 will perform a refresh on the first memory bank specified by the memory bank address field F2 (S75).

[0068] The semiconductor memory device 120 performs a refresh (S80) targeting the second memory bank at a timed delay specified by the extended flag field F3.

[0069] After completing steps S65, S70, and S80 as described above, the refresh process ends. As mentioned above, when a refresh command is received, the refresh of two memory banks can be performed according to the value specified in the extended flag field F3. Therefore, compared with the configuration that requires sending and receiving refresh commands specifying each memory bank, the issuance of refresh commands can be suppressed, achieving efficient utilization of the command bus 20.

[0070] A4. Example of an action: use Figure 8 and Figure 9 An example of the actions performed when the pre-charge and refresh processes described above have been executed is explained. Figure 8 In the sequence diagram, the upper part represents the actions in the comparative example, and the lower part represents the actions in the first embodiment.

[0071] exist Figure 8 In the comparative example shown above, for example, to precharge and refresh memory banks B0 and B7, the memory controller 110 issues a precharge command (PRE) specifying memory bank B0 (0000) in cycle T2. Cycle T2, for example, is a time interval of tRP elapsed since the last precharge targeting memory bank B0. Furthermore, in cycle T6, the memory controller 110 issues a precharge command specifying memory bank B7 (1000). This cycle T6, for example, is also a time interval of tRP elapsed since the last precharge targeting memory bank B7. Then, the memory controller 110 intends to issue a refresh command (REF) targeting both memory banks B0 and B7. However, for example, as the shortest period from the issuance of the precharge command to the issuance of the refresh command, in the case of setting "six cycles", the refresh command for both memory banks B0 and B7 is finally issued in a period T12, which is six cycles later than the period T6 that targets memory bank B7, which issued the precharge command at a later time.

[0072] In contrast, Figure 8In the embodiment shown in the following paragraph, during cycle T2, memory bank 0 (0000) is specified in the memory bank address field F2, and a precharge command (PRE) with an extension flag of "110" is issued. In this case, precharge is immediately performed on memory bank B0. Then, in cycle T6, which is delayed four cycles from cycle T2, precharge is performed on memory bank B7 (1000). Here, in cycle T8, which is delayed six cycles from T2, where the last precharge command was issued, memory bank 0 (0000) is specified, and a refresh command (REF) with an extension flag of "101" is issued. In this case, refresh is immediately performed on memory bank B0. Then, in cycle T12, which is delayed four cycles from cycle T8, refresh is performed on memory bank B7.

[0073] As described above, based on the comparison between the comparative example and this embodiment, it can be seen that in this embodiment, while performing the same operations as in the comparative example, the issuance of the precharge command is suppressed compared to the comparative example. Furthermore, the timing of issuing the refresh command (REF) can be earlier than in the comparative example. Therefore, in this embodiment, compared to the comparative example, the command bus 20 can be effectively utilized while ensuring the timing of issuing the refresh command or precharge command.

[0074] exist Figure 9 In the illustrated action example, the extended flag field F3 of the precharge command is set to "111", and the extended flag field F3 of the refresh command is set to "110". Therefore, by issuing the precharge command in cycle T2, memory bank B0, which is the first memory bank, is precharged in cycle T2, and memory bank B7, which is the second memory bank, is precharged in cycle T7, which is five cycles later than cycle T2. Furthermore, by issuing the refresh command in cycle T8, memory bank B0, which is the first memory bank, is refreshed in cycle T8, and memory bank B7, which is the second memory bank, is refreshed in cycle T13, which is five cycles later than cycle T7. To perform the precharge and refresh of both memory banks B0 and B7, only two commands are issued during cycles T2 to T13. Therefore, with... Figure 8 Similarly, the actions of the next segment can ensure the timing of issuing refresh commands or precharge commands, while effectively utilizing the command bus 20.

[0075] In previous LPDDR5 standard systems, refresh commands required eight 1μs (microseconds) to be issued under high-temperature conditions, therefore one refresh command was issued every 125ns (nanoseconds). Furthermore, compared to issuing one refresh command, two precharge commands were required, therefore three commands were issued every 125ns (see [reference]). Figure 8(See the previous paragraph). On the other hand, in the memory system 100 of this embodiment, issuing one precharge command is sufficient instead of issuing one refresh command, thus reducing the number of commands issued by 125ns. Since the time required to issue one command is 1.25ns, a 1% reduction in commands can be achieved.

[0076] Furthermore, the row address can be changed at least every 42ns. Therefore, in conventional systems based on the LPDDR5 standard, two precharge commands are issued every 42ns. On the other hand, in the memory system 100 of this embodiment, the issuance of the precharge command can be reduced to one. Therefore, a reduction of 1.25ns can be achieved every 42ns, resulting in an approximately 3% command reduction effect.

[0077] Furthermore, both memory banks can be precharged with a single command, and from... Figure 8 The comparison between the upper and lower parts is understandable, allowing the refresh command to be issued earlier from period T12 to period T8. With a tREFi (refresh interval) of 125ns, four periods can be reduced every 125ns, or 5ns (1.25ns × 4), and a 4% command reduction effect can be achieved.

[0078] If the above command reduction effects are combined, the total utilization efficiency of the command bus 20 is expected to increase by a maximum of about 8%.

[0079] According to the memory system 100 of the first embodiment described above, when precharging of two memory banks is specified by a precharge command, both the first and second memory banks can be precharged by a single precharge command (PRE). Therefore, the issuance of the precharge command can be suppressed, creating idle time in the command bus 20. As a result, the timing of the precharge command issuance can be ensured, and the command bus 20 can be utilized efficiently.

[0080] Furthermore, when the memory controller 110 specifies precharging of a single memory bank, the bit mode of the extended flag field F3, which specifies the precharge command, becomes the least significant 3 bits set to 000. When it specifies precharging of all memory banks, the bit mode of the extended flag field F3, which specifies the precharge command, becomes the least significant 3 bits set to 001. Therefore, the least significant 3 bits can be utilized in the same way as conventional memory systems. Thus, compatibility with conventional memory systems can be ensured.

[0081] In addition, the extended flag field F3 of the precharge command consists of a 3-bit string. As a relative processing timing, it can specify a five-bit pattern that represents the delay period from the execution of precharge targeting the first memory bank. Therefore, the five delay periods can be flexibly set according to the utilization of the command bus 20.

[0082] Furthermore, according to the memory system 100, when two memory banks are specified to be refreshed via a refresh command (REF), both the first and second memory banks can be refreshed with a single refresh command. Therefore, the issuance of refresh commands can be suppressed, and free space can be created in the command bus 20. Thus, the command bus 20 can be used efficiently while ensuring the timely issuance of refresh commands.

[0083] Furthermore, when the memory controller 110 specifies a refresh command for two memory banks, the bit mode of the extended flag field F3, which is designated as the refresh command, becomes the least significant 3 bits set to 000. When the memory controller 110 specifies a refresh command for all memory banks, the bit mode of the extended flag field F3, which is designated as the refresh command, becomes the least significant 3 bits set to 001. Therefore, the least significant 3 bits can be utilized in the same way as conventional memory systems. Thus, compatibility with conventional memory systems can be ensured.

[0084] In addition, the extended flag field of the refresh command consists of a 3-bit string. As a relative processing timing, it can specify a six-bit pattern that represents the delay period from the execution of the refresh targeting the first memory bank. Therefore, the six delay periods can be flexibly set according to the utilization of the command bus.

[0085] B. Second implementation method: Figure 10 The memory system 100a of the second embodiment shown differs from the memory system 100 of the first embodiment in that it has five first registers 31, 32, 33, 34, 35 and six second registers 41, 42, 43, 44, 45, 46. Other configurations in the memory system 100a of the second embodiment are the same as those in the memory system 100 of the first embodiment; therefore, identical configurations are labeled with the same symbols, and detailed descriptions thereof are omitted.

[0086] In the five first registers 31-35, a delay period is set corresponding to the five bit patterns "011", "100", "101", "110", and "111" shown in the extended flag field F3 of the precharge command. Additionally, in the six second registers 41-46, a delay period is set corresponding to the six bit patterns "010", "011", "100", "101", "110", and "111" shown in the extended flag field F3 of the refresh command.

[0087] Specifically, such as Figure 11 As shown, in this embodiment, the five bit patterns "011", "100", "101", "110", and "111" corresponding to the extended flag field F3 of the precharge command are respectively set with the following delay times.

[0088] • "011": Delay by one cycle • "100": Delayed by three cycles • "101": Delayed by five cycles • "110": Delayed by seven cycles • "111": Delayed by eight cycles In addition, in this embodiment, the following delay times are set for each of the second registers 41 to 46, corresponding to the six bit patterns shown in the extended flag field F3 of the refresh command, namely “010”, “011”, “100”, “101”, “110”, and “111”.

[0089] • "010": Delay by one cycle • "011": Delayed by two cycles • "100": Delayed by five cycles • "101": Delayed by seven cycles • "110": Delayed by nine cycles • "111": Delayed by 12 cycles The values ​​set in each of the first registers 31-35 and each of the second registers 41-46 can be rewritten. Therefore, the user can pre-set appropriate delay time candidates for the first registers 31-35 and the second registers 41-46, and can also change them later.

[0090] In the precharge process, in S40, the set delay time is read from the register corresponding to the bit pattern specified by the extended flag field F3 in the first registers 31 to 35, and the precharge of the second memory is performed after delaying the start of the precharge of the first memory.

[0091] Similarly, in the refresh process, in S80, the set delay time is read from the register corresponding to the bit pattern specified by the extended flag field F3 in the second registers 41-46, and the refresh of the second memory is performed after delaying the refresh of the first memory from the start of the refresh execution.

[0092] The memory system 100a of the second embodiment described above achieves the same effect as the memory system 100 of the first embodiment. Furthermore, when the semiconductor memory device 120 performs pre-charging on the second memory, it reads the set delay period from the first registers 31-35 corresponding to the bit pattern specified by the extended flag field F3, and performs pre-charging of the second memory at a timing that delays the execution of pre-charging on the first memory by the delay period. Therefore, by adjusting the delay period set in the first registers 31-35, the execution timing of pre-charging on the second memory can be adjusted.

[0093] Similarly, when the semiconductor memory device 120 performs a refresh targeting the second memory bank, it reads the set delay period from the second registers 41 to 46 corresponding to the bit pattern specified by the extended flag field F3, and performs the refresh of the second memory bank at a timing that delays the execution of the refresh targeting the first memory bank. Therefore, by adjusting the delay period set for the second registers 41 to 46, the execution timing of the refresh targeting the second memory bank can be adjusted.

[0094] C. Other implementation methods: (C1) In various embodiments, the inverted object bit is the highest bit (bit b7) of the memory address field F2, but this disclosure is not limited thereto. The inverted object bit may also be a predetermined bit in the bit string of the memory bank group in the memory address section.

[0095] (C2) In each embodiment, bits b1 to b3 of the extended flag field F3 of the precharge command and refresh command have the same meaning as the least significant 3 bits in the refresh command of conventional LPDDR5, but this disclosure is not limited to this. A completely different data format from conventional precharge commands and refresh commands may also be used in the data format of the precharge command and refresh command of this disclosure. In this configuration, the extended flag field F3 is not limited to 3 bits, and may be composed of any number of bit strings. Furthermore, the extended flag field F3 may not include the least significant bit. Additionally, the command field F1 and the memory address field F2 may also be composed of bit strings with a different number of bits than those in each embodiment.

[0096] (C3) In various embodiments, this disclosure may be applied to only either the precharge command or the refresh command, while the other command may be processed using conventional data formats and conventional rules. For example, the precharge command may be specified to precharge only one memory cell or to precharge all memory cells, and the refresh command may be specified to refresh two memory cells with a time difference. Alternatively, the precharge command may be specified to precharge two memory cells with a time difference, and the refresh command may be specified to refresh both memory cells simultaneously or to refresh all memory cells simultaneously.

[0097] (C4) Each embodiment is merely an example and various modifications are possible. For example, the number of memory groups is not limited to four and can be any number. In addition, the number of memory cells contained in each memory group is not limited to four and can be any number.

[0098] This disclosure is not limited to the embodiments described above, and can be implemented in various configurations without departing from its spirit. For example, in order to solve part or all of the above-described problems, or to achieve part or all of the above-described effects, the technical features in each embodiment corresponding to the technical features described in the Summary of the Invention section can be appropriately replaced or combined. In addition, if a technical feature is not described as an essential feature in this specification, it can be appropriately deleted.

[0099] The pre-charge processing and refresh processing execution unit (hereinafter referred to as the "control unit") and its methods described in this disclosure can also be implemented by a dedicated computer, which is provided by a processor and memory programmed to perform one or more functions embodied in a computer program. Alternatively, the control unit and its methods described in this disclosure can also be implemented by a dedicated computer provided by a processor composed of one or more dedicated hardware logic circuits. Alternatively, the control unit and its methods described in this disclosure can also be implemented by one or more dedicated computers, which are configured by a combination of a processor and memory programmed to perform one or more functions and a processor composed of one or more hardware logic circuits. In addition, the computer program can also be stored as instructions executed by the computer on a computer-readable non-transferable tangible recording medium.

Claims

1. A memory system, characterized in that, include: A semiconductor memory device having multiple memory banks; And a memory controller, which issues commands based on access requests from a computing device accessing the semiconductor memory device to the semiconductor memory device. The memory controller issues a command to the semiconductor memory device, including an extended flag field and a memory bank address field, as a precharge command, wherein... The extended flag field is a bit string that specifies: Precharging one memory cell, precharging all memory cells, or precharging any one of two memory cells belonging to distinct memory cell groups; and The second relative processing timing for the first memory bank when both memory banks are pre-charged. The memory address field is a bit string that determines the memory address of the memory bank that will be the object to be precharged. The semiconductor memory device, When the precharge command specifies that precharge should be applied to both memory modules, The first memory bank, as determined by the memory bank address field, is used as the object for precharging. The second memory bank, determined by the following memory bank address, is used as the object, and precharging is performed at the relative processing time specified by the extended flag field, wherein the memory bank address is obtained by inverting a predetermined 1 bit, i.e., the inverted object bit, in the bit string of the determined memory bank group in the memory bank address field.

2. The memory system according to claim 1, characterized in that, The extended flag field includes the least significant three bits of the data format of the precharge command. The memory controller When precharging a memory bank is specified, it is specified by setting the bit pattern of the extended flag field to the least significant 3 bits being 000. When precharging of all memory is specified, it is specified in such a way that the bit pattern of the extended flag field is such that the least significant 3 bits are 001.

3. The memory system according to claim 2, characterized in that, The extended flag field consists of a 3-character string. As the relative processing timing, five bit patterns can be specified to represent the delay period from the execution of precharging to the first memory bank.

4. The memory system according to claim 3, characterized in that, It also has five registers, each corresponding to one of the five bit patterns and configured with a delay period. When the semiconductor memory device performs precharging with respect to the second memory bank, it reads the set delay period from the register corresponding to the bit pattern specified by the extended flag field, and performs precharging at a timed interval that delays the execution of precharging with respect to the first memory bank from the execution of precharging with respect to the first memory bank.

5. A memory system, characterized in that, include: A semiconductor memory device having multiple memory banks; And a memory controller, which issues commands based on access requests from a computing device accessing the semiconductor memory device to the semiconductor memory device. The memory controller issues a refresh command to the semiconductor memory device, including an extended flag field and a memory address field, wherein... The extended flag field is a bit string that specifies: Refreshing all memory banks, or refreshing either one of two memory banks belonging to distinct memory bank groups; and When refreshing two memory banks, the second relative processing timing for the first memory bank. The memory address field is a bit string that determines the memory address of the memory bank that will be refreshed. The semiconductor memory device, When the refresh command specifies that both memory banks should be refreshed, The first memory bank, determined by the memory bank address field, is used as the object for a refresh. The second memory bank, determined by the following memory bank address, is treated as an object and refreshed at the relative processing time specified by the extended flag field, wherein the memory bank address is obtained by inverting a predetermined bit, i.e., the inverted object bit, in the bit string of the determined memory bank group in the memory bank address field.

6. The memory system according to claim 5, characterized in that, The extended flag field includes the least significant three bits of the data format of the refresh command. The memory controller When specifying to refresh two memory banks, the extended flag field is specified in such a way that the least significant 3 bits are set to 000. When specifying a refresh of all memory, the extended flag field is specified in such a way that the least significant 3 bits are set to 001.

7. The memory system according to claim 6, characterized in that, The extended flag field consists of a 3-character string. As the relative processing timing, a six-bit pattern can be specified to represent the delay period from the execution of a refresh targeting the first memory bank.

8. The memory system according to claim 7, characterized in that, It also has six registers, each of which is configured with a delay period corresponding to one of the six bit patterns. When the semiconductor memory device performs a refresh targeting the second memory bank, it reads the set delay period from the register corresponding to the bit pattern specified by the extended flag field, and performs the refresh at a timed interval that delays the execution of the refresh targeting the first memory bank from the execution of the refresh.

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