A transient control method for asymmetric multiphase buck converter based on minimum time control

Abstract

This invention discloses a transient control method for an asymmetric multiphase buck converter based on minimum-time control. Addressing the coupling bottleneck between steady-state and transient performance in traditional converters, this invention introduces a joint minimum-time control strategy for the main and auxiliary phases within an asymmetric architecture comprising a large-inductance main phase and a small-inductance auxiliary phase. When a step change occurs in the load current, based on the principle of capacitor charge balance and with the core constraint that the net charge absorbed by the capacitor at the end of the transient is zero, the optimal adjustment time for single-cycle oscillation-free recovery is directly algebraically calculated, and the target on or off time of the main and auxiliary phase switches is accurately calculated accordingly. This invention effectively utilizes the high rate of change of the auxiliary phase current, drastically compressing transient regulation to be completed within one control cycle, achieving time optimization of the load jump trajectory, and significantly reducing the dynamic deviation of the output voltage.

Description

Technical Field

[0001] This invention relates to the field of digital control technology for power electronic converters, and specifically to a transient control method for an asymmetric multiphase buck converter based on minimum time control, which aims to improve the response speed of large-signal load transitions in microprocessor-powered systems. Background Technology

[0002] Microprocessor power supply systems (VRMs) have extremely stringent requirements for load transient regulation time. When the load current experiences a step fluctuation, the inductor current cannot change instantaneously. The increased or excessive load demand must be temporarily borne by the output capacitor, inevitably leading to a deep overshoot or drop in the output voltage. Existing multiphase parallel buck converters mostly employ symmetrical parameter designs, with the same steady-state and transient equivalent inductance. This results in an irreconcilable physical contradiction between steady-state ripple suppression and dynamic response speed. To alleviate this contradiction, the industry has proposed asymmetrical parameter multiphase parallel buck converter topologies, which introduce an auxiliary phase with a smaller inductance for transient compensation. However, under the asymmetrical parameter structure, if the traditional linear dual-loop control strategy is continued, the system's dynamic recovery speed is still strictly limited by the frequency domain bandwidth, failing to fully utilize the physical advantage of the extremely high current change rate of the small-inductance auxiliary phase. Currently, while the minimum time control (MTC) strategy based on the Pontryagin minimum principle can achieve the optimization objective of minimizing state transition time, existing minimum time control research is almost entirely limited to single-phase or symmetrical parameter multiphase buck converters. In asymmetrical structures, due to the significant differences in parasitic parameters and energy storage slopes of the inductors of each phase, how to establish a multi-dimensional charge balance model and achieve precise coordination of heterogeneous phase groups during transient processes has become an urgent control challenge. Summary of the Invention

[0003] The purpose of this invention is to overcome the bandwidth bottleneck of traditional dual-loop control when dealing with large step loads, and to provide a transient control method for an asymmetric multiphase buck converter based on minimum time control, achieving optimal coordinated adjustment of the main phase and auxiliary phases. To achieve the above objective, this invention adopts the following technical solution: This invention provides a transient control method for an asymmetric multiphase buck converter based on minimum time control, used in an underlying architecture comprising N main phases with large inductors and M auxiliary phases with small inductors. The system is dominated by the steady-state control unit in steady state; when a sudden change in load current occurs, it switches to the transient control unit. This transient control unit is based on the principle of output capacitor charge balance, using the zero net charge absorbed by the capacitor at the end of the transient as the core constraint, and calculates the optimal transient adjustment time for single-cycle oscillation-free recovery. ΔtThen, based on the adjustment time, the target on-time or target off-time of the large inductor main phase and the small inductor auxiliary phase are calculated to generate drive signals. After the current is rematched, the system smoothly switches back to steady-state control. The beneficial effects of this invention are: it breaks through the integral lag limitation of traditional linear loops and deeply integrates the hardware advantages of asymmetric parameter architecture with the minimum time control algorithm. By algebraically feeding forward to deduce the switching sequence of the main and auxiliary phases, the transient adjustment process is forcibly compressed into an extremely short control cycle. This scheme effectively utilizes the extremely high current ramp-up and ramp-down slope of the auxiliary phase to compensate for the capacitor charge, completely eliminates multi-cycle oscillations during dynamic response, minimizes voltage sag or overshoot amplitude, and significantly improves the transient regulation efficiency of the converter under extreme conditions. Attached Figure Description

[0004] To more clearly and intuitively demonstrate the underlying timing and circuit topology of the main-auxiliary phase combined minimum time control strategy of this invention, the accompanying drawings in this specification all use an asymmetric three-phase parallel buck converter with N=2 large inductor main phases and M=1 small inductor auxiliary phases as a typical specific embodiment for illustration and explanation. In this specific embodiment, the control logic, switching actions, and charge balance physical processes of each phase are completely consistent with the generalized multiphase mathematical model derived above. Those skilled in the art can seamlessly extend this control strategy and apply it to any asymmetric architecture converter with N main phases and M auxiliary phases without any creative effort, based on the above generalized mathematical model.

[0005] Figure 1 This is a system overall control block diagram according to an embodiment of the present invention. D m1_S The driving signal represents the upper transistor of the first phase of the main phase. D m1_Q This represents the drive signal for the lower transistor of the first phase of the main phase. D m2_S The driving signal represents the upper transistor of the second phase of the main phase. D m2_Q This represents the drive signal for the lower transistor of the second phase of the main phase. D a_S The driving signal represents the auxiliary phase upper transistor. D a_Q The driving signal representing the auxiliary phase lower transistor. I Lm1 Represents the inductor current of the first phase of the main phase. I Lm2 Represents the inductor current of the second phase of the main phase. V o Represents the output voltage. I o Represents the output current;

[0006] Figure 2 This is a circuit topology diagram of the asymmetric parameter three-phase parallel buck converter proposed in the embodiment of the present invention; Figure 3 This is the logic diagram of the minimum time control waveform for the main and auxiliary phases under the condition of sudden increase in load current in an embodiment of the present invention. Figure 4 This is a logic diagram of the minimum time control waveform for the main and auxiliary phases under the load current sudden drop condition in an embodiment of the present invention. Detailed Implementation

[0007] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be described in great detail below with reference to the accompanying drawings and specific embodiments. It should be clearly stated that the specific embodiments described herein are merely representative implementations of this invention and do not constitute any limitation on the scope of protection of this invention.

[0008] This invention proposes a transient control method for an asymmetric multiphase buck converter based on minimum time control, which utilizes the characteristics of small auxiliary phase inductance and fast dynamic current response in asymmetric parameter topologies. (See attached diagram) Figure 1 The system overall control structure block diagram and appendix shown are as follows. Figure 2 The circuit topology diagram shown illustrates the digital control architecture of this system, which includes a steady-state control unit, a transient control unit, a load transient detection circuit, a digital pulse width modulation module, and a control mode selection unit. From a control mechanism perspective, this invention executes a steady-state-transient-steady-state switching control logic. During the stable operation phase of the system load, the steady-state control unit dominates wave generation, relying on traditional dual-closed-loop algorithms or average current mode control to eliminate static errors, ensuring the output voltage remains near the reference voltage and achieving current equalization among the multi-phase main phases. Simultaneously, the load transient detection circuit monitors the dynamic fluctuations of the output current in real time. When the detection circuit detects a step change in the load current, the control mode selection unit triggers an interrupt, switching the system's drive control to the transient control unit. Based on the Pontryagin minimum principle and the output capacitor charge balance theory, the transient control unit directly plans the on and off timing of the main and auxiliary phase power switching devices through algebraic calculations. This algebraic calculation allows the transient adjustment process to be completed within one control cycle, achieving optimal time for the system to respond to load jumps. Once the inductor current within the system is rematched with the load demand, the system smoothly returns control to the steady-state control unit.

[0009] During the execution of the main-auxiliary phase joint minimum time control mechanism, the parameter calculation model inside the main control chip is strictly based on the principle of charge conservation of the output capacitor. When the microprocessor power supply system faces a large step increase in load current, due to the inherent energy storage characteristics of the inductor and the physical limitation that the inductor current cannot change abruptly, the inductor current of the main phase and the auxiliary phase cannot instantly follow the load current to achieve the same magnitude of increase. During this dynamic response, the transient current difference between the increased load current demand and the actual inductor current is temporarily compensated by the filter capacitor at the system output by releasing the stored charge. This transient discharge process of the output filter capacitor will directly lead to a rapid reduction in the amount of charge maintained at both ends of the capacitor, thereby causing a significant transient drop in the system output voltage; if no rapid control intervention is implemented, the drop in output voltage will exceed the voltage tolerance range allowed for normal operation of the subsequent microprocessor. In order to achieve the single-cycle oscillation-free recovery target in the minimum time control theory, the transient control unit of this invention sets clear boundary conditions at the algorithm level: during the transient adjustment time Δt At the end, the net deviation of the output capacitor voltage is zero. The physical essence of this condition is that the algebraic sum of the net charge absorbed and released by the output capacitor during the initial stage of load surge, when it supports load discharge, and subsequently during the stage of reverse charging by the inductor current, is zero. Based on the above capacitor charge conservation constraint, for an asymmetric buck system containing two large inductor main phases and one small inductor auxiliary phase, when the system detects a step current fluctuation of... ΔIo During sudden increases in operating conditions (the specific control timing and current waveform logic are shown in the attached figure), Figure 3 As shown), the main control chip of the transient control unit calculates the optimal conduction timing for the main phase with the large inductor and the auxiliary phase with the small inductor based on the system's large-signal model. This is achieved by introducing the steady-state duty cycle, which reflects the system's energy balance, into the algorithm model. D and input voltage V in Based on the geometric slope relationship of the inductor current during the charging and discharging phases, the main control chip derives the target on-time used to guide the operation of the main phase of the large inductor. t ON,m The calculation formula is as follows: (1) At the same time, the system synchronously derives the target on-time for controlling the conduction of the small inductor auxiliary phase. t ON,a The calculation formula is as follows: (2) To solve the above on-time formula that includes unknown time variables, the underlying solution logic of the main control system must be based on the physical constraint of the system's global charge balance. During transient settling time... ΔtWithin this system, the core charge conservation constraint equation states that the sum of the charge increments provided by all primary phases plus the sum of the charge increments provided by all auxiliary phases must equal the excess charge demand generated by a sudden load increase. The mathematical form of this physical constraint is: (3) In the formula, Q Lm,i The charge amount of the i-th phase inductor of the main phase. Q La To the amount of charge in the auxiliary phase inductor, I m0 The initial current of the main phase inductor.

[0010] The system substitutes the target conduction time expressions for the large inductor main phase and the small inductor auxiliary phase, derived above, into the charge integral equations corresponding to the inductors of each phase, and then substitutes them all into the core charge conservation constraint equations mentioned above. The main control chip solves for the optimal transient settling time for controlling the transient recovery process of the system by performing simplification operations such as algebraic power reduction and combining like terms of polynomials. Δt The generalized analytical expression of is calculated as follows: (4) After completing the algebraic feedforward calculations, the main control chip immediately transmits the data to the hardware topology via its internally configured digital pulse width modulation peripheral. N Road Master and M The auxiliary phase power switch issues a drive pulse corresponding to the target conduction time. Under the joint drive of the conduction pulse, the large inductor main phase and the small inductor auxiliary phase collaboratively inject a high-rate-of-change compensation current into the system output node. This collaborative compensation mechanism is effective during the optimal transient regulation time. Δt Internally, it effectively suppressed further drops in output voltage and quickly replenished the charge released by the output filter capacitor in the early stage of load surge, thereby accurately realizing dynamic matching and energy transfer between the internal inductor current state and the external step load current demand at the control level.

[0011] The corresponding working mechanism is that when the microprocessor power supply system encounters a sudden drop in load current during a load discharge condition (the specific control timing and current waveform logic are shown in the attached figure)... Figure 4As shown, excess inductor current maintaining heavy load operation within the main and auxiliary phases cannot be discharged instantaneously. Excess charge flows into the output capacitor at the system's end at an extremely high rate, causing voltage overshoot. To address this condition, the transient control unit of this invention reverses its execution logic. The system rapidly shuts off all upper-arm power switches while simultaneously turning on all lower-arm power switches, utilizing the maximum negative physical slope provided by the system to quickly reduce all inductor currents. During load evacuation, the system also strictly adheres to the core charge balance control principle of single-cycle, oscillation-free recovery. The main control chip again establishes a discharge constraint model based on the geometric slope descent relationship and derives the target turn-off time guiding the large inductor main phase when facing a sudden load drop. t OFF,m The calculation formula is as follows: (5) Furthermore, the target turn-off time for the auxiliary phase with small inductors is simultaneously derived. t OFF,a The calculation formula is as follows: (6) Further investigation is needed to determine the globally optimal settling time under this unloading condition. Δt At the same time, the underlying calculation logic of the main control chip is also based on the physical constraints of the system's global charge balance. During transient adjustment time... Δt Internally, the core charge conservation constraint equation is expressed as follows: the sum of the charge increments released by all main phases plus the sum of the charge increments released by all auxiliary phases must be strictly equal to the amount of excess charge that the output capacitor is forced to absorb due to a sudden load drop. The mathematical form of this physical constraint is: (7) In the formula, Q Lm,i The Prime Minister i The amount of charge in the phase inductor, Q La To the amount of charge in the auxiliary phase inductor, I m0 The initial current of the main phase inductor.

[0012] The system utilizes the geometric slope relationship of the inductor current charging and discharging process. Substituting the previously derived expressions for the main and auxiliary correlation discontinuation times into the general formula for single-phase charge integration, and then uniformly substituting them into the aforementioned core charge conservation constraint equation, the system solves the core charge conservation constraint equation by performing algebraic expansion and polynomial term merging operations, ultimately obtaining the optimal transient settling time. Δt The generalized analytical expression of is calculated as follows: (8) Based on the generalized analytical formula derived above, the main control chip can directly calculate the optimal transient adjustment time under load-discharge conditions within an extremely short instruction cycle. Δt After locking the time variable, the main control chip immediately sends drive pulses corresponding to the target turn-off time to each main and auxiliary phase power switch via the digital pulse width modulation peripheral. Under the joint drive of the turn-off pulses, the large inductor main phase and the small inductor auxiliary phase work together to utilize the maximum negative voltage excitation provided by the system topology to forcibly reduce all phase currents. With this turn-off timing feedforward control system, the asymmetric buck converter can effectively discharge the excess charge absorbed by the output capacitor in the initial stage without overshooting the output voltage, and precisely control the main and auxiliary inductor groups to complete the smooth return of the overall current to the new steady state with the maximum physical rate of change, thereby achieving dynamic matching between internal energy and external demand.

[0013] In summary, by performing algebraic inverse operations and global timing planning for load surge and drop conditions respectively, this invention successfully achieves efficient physical coordination between heterogeneous large inductor main phase and small inductor auxiliary phase. This fundamentally breaks through the physical limitations of traditional asymmetric architecture converters caused by control algorithm lag when dealing with dynamic responses, and provides an extremely optimized transient energy management scheme for microprocessor power supply systems.

Claims

1. A transient control method for an asymmetric multiphase buck converter based on minimum time control, characterized in that, The buck converter includes N The main phase of the large inductor and M The control method for the auxiliary phase of the small inductor includes: during steady-state operation, the steady-state control unit dominates the waveform generation to maintain output voltage accuracy and steady-state current sharing; when the load transient detection circuit detects a step change in load current, the system quickly switches to the transient control unit to take over control; the transient control unit calculates the optimal transient adjustment time without oscillation recovery in a single cycle based on the principle of output capacitor charge balance, with the net charge absorbed by the capacitor at the end of the transient as the core constraint. Δt According to the optimal transient adjustment time Δt The target on-time or target off-time of the large inductor main phase and the small inductor auxiliary phase during the transient response are calculated respectively, and a drive signal is generated accordingly; after the optimal transient adjustment time is reached... Δt After the inductor current is rematched with the load demand, the transient control ends and the system switches back to the steady-state control unit.

2. The transient control method for an asymmetric multiphase buck converter based on minimum time control according to claim 1, characterized in that, When a step change in load current is detected ΔI o During a sudden increase, the target conduction time of the main phase of the large inductor... t ON,m With respect to the target on-time of the small inductor auxiliary phase t ON,a The calculation formulas are as follows: ； ； In the formula, D The steady-state duty cycle of the system. V in Input voltage, L m This is the single-phase inductance value of the main phase with a large inductance.

3. The transient control method for an asymmetric multiphase buck converter based on minimum time control according to claim 2, characterized in that, for N The main phase and M For an asymmetric multiphase parallel buck converter with one auxiliary phase, the optimal transient settling time is calculated under the condition of a sudden increase in load current. Δt The generalized analytical expression is: ； In the formula, L a This represents the single-phase inductance value of the auxiliary phase with a small inductance.

4. The transient control method for an asymmetric multiphase buck converter based on minimum time control according to claim 1, characterized in that, When a step change in load current is detected ΔI o During a sudden drop, the system reduces the inductor current by turning off the upper transistor and turning on the lower transistor. The target turn-off time of the large inductor main phase... t OFF,m With respect to the target turn-off time of the small inductor auxiliary phase t OFF,a The calculation formulas are as follows: ； 。 5. The transient control method for an asymmetric multiphase buck converter based on minimum time control according to claim 4, characterized in that, for N The main phase and M For an asymmetric multiphase parallel buck converter with one auxiliary phase, the optimal transient settling time is calculated under the condition of a sudden load current drop. Δt The generalized analytical expression is: 。

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