Linear adjustable capacitance negative feedback amplifying circuit and bandwidth expanding method
By using a linearly adjustable capacitive negative feedback amplifier circuit, utilizing a parallel RC network and MOSFET gate bias voltage adjustment, combined with a cross Miller capacitor, a high-gain, wide-bandwidth, and bandwidth-adjustable amplifier circuit design under unipolar transistor technology was realized. This solves the bandwidth limitation and load effect problems in the prior art and is suitable for TFT technology.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOUTH CHINA UNIV OF TECH
- Filing Date
- 2026-02-28
- Publication Date
- 2026-06-23
AI Technical Summary
In the unipolar transistor process, existing amplifier circuits suffer from limited bandwidth, difficulty in bandwidth adjustment, severe load effects in negative feedback structures, and incompatibility between traditional bandwidth expansion methods and TFT processes, making it difficult to achieve high-gain, wide-bandwidth amplifier circuits with linearly adjustable bandwidth.
A linearly adjustable capacitive negative feedback amplifier circuit is adopted. By introducing a linearly adjustable unit and a negative capacitor compensation unit, and using the parallel RC network and the gate bias voltage of the MOSFET to adjust the zero frequency, the zero frequency can be continuously adjusted. Furthermore, by combining the cross Miller capacitor to introduce an equivalent negative capacitor structure, dual bandwidth expansion is achieved.
It achieves linearly adjustable bandwidth and decoupled control of gain and zero frequency, improving the debugging flexibility and process tolerance of the circuit, adapting to pure N-type or pure P-type TFT processes, and filling the design gap of high-performance broadband amplifiers under unipolar processes.
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Figure CN122268284A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a linearly adjustable capacitive negative feedback amplifier circuit and a bandwidth extension method. Background Technology
[0002] Thin film transistor (TFT) technology has evolved from amorphous silicon (a-Si), polycrystalline silicon (Poly-Si), organic thin film transistors (OTFTs) to metal oxide thin film transistors (MO TFTs), with continuous optimization in device performance and manufacturing costs. Among them, MO-TFTs have attracted widespread attention from researchers due to their relatively high mobility, good spatial uniformity, low processing temperature, and compatibility with flexible and transparent electronic products, becoming a future trend in the development of large-area flexible integrated circuits, especially in flexible wearable bioelectronic applications.
[0003] However, in most cases, TFT technology lacks high-performance complementary devices. Therefore, TFT circuits are typically implemented based on unipolar (pure N-type or pure P-type) transistors, a key difference between TFT circuits and traditional CMOS complementary metal-oxide-semiconductor circuits. Due to the constraints of unipolar process technology, it is impossible to directly utilize the mature PMOS-NMOS complementary structure from CMOS technology to achieve high-gain, wide-bandwidth amplifier designs.
[0004] In recent years, a series of studies on methods for extending the bandwidth of TFT amplifiers have been conducted both domestically and internationally. One method to improve the bandwidth of TFT amplifiers is to use the Cherry-Hooper amplifier structure, which typically consists of two stages of common-source amplifiers and a feedback resistor, achieving a relatively wide bandwidth. However, due to the use of a fixed resistor in the feedback network, there is a significant load effect, which degrades the overall amplifier gain performance, and the bandwidth cannot be dynamically adjusted according to application requirements. Another method is to use inductor peaking technology, but inductors are difficult to integrate in TFT processes, resulting in large area overhead and making them unsuitable for flexible integrated electronic systems. Furthermore, amplifiers using bootstrap structures as loads are commonly used to improve the gain of unipolar amplifiers, but their effect on improving bandwidth is limited.
[0005] Therefore, under the constraints of limited power consumption and unipolar process technology, how to simultaneously achieve a high-gain, wide-bandwidth, and linearly adjustable amplifier circuit is a long-standing and urgent technical challenge in this field. Summary of the Invention
[0006] The main objective of this application is to propose a linearly adjustable capacitive negative feedback amplifier circuit and a bandwidth extension method, aiming to solve at least one of the following technical problems existing in the prior art: limited bandwidth of amplifier circuits under unipolar transistor technology, difficulty in bandwidth adjustment, severe load effect of negative feedback structure, and incompatibility between traditional bandwidth extension methods and TFT technology.
[0007] To achieve the above objectives, one aspect of this application provides a linearly adjustable capacitive negative feedback amplifier circuit, including a linearly adjustable unit and a negative capacitance compensation unit. The linearly adjustable unit includes a differential input pair transistor and a capacitive negative feedback network. The differential input pair transistor is used to receive differential input signals and generate differential output signals. The capacitive negative feedback network is connected between the sources of the differential input pair transistor. The negative capacitance compensation unit is connected to the drain of the differential input pair transistors; The capacitive negative feedback network includes at least one source MOSFET (Ms) operating in the linear region and a capacitor connected in parallel with the source MOSFET. The source MOSFET and the capacitor form a parallel RC network, introducing an adjustable zero in the circuit transfer function. By adjusting the gate bias voltage of the source MOSFET, the equivalent impedance of the parallel RC network is linearly adjusted, thereby continuously adjusting the frequency position of the adjustable zero.
[0008] In some embodiments, the capacitive negative feedback network further includes a fifth MOSFET and a sixth MOSFET; The drain of the fifth MOS transistor is connected to the source of the first input transistor in the differential input pair, and the drain of the sixth MOS transistor is connected to the source of the second input transistor in the differential input pair. The source and drain of the source MOSFET are connected between the source of the fifth MOSFET and the source of the sixth MOSFET. The two terminals of the capacitor element are respectively connected to the source of the fifth MOS transistor and the source of the sixth MOS transistor, thereby forming a parallel connection with the source MOS transistor.
[0009] In some embodiments, the source MOSFET, the capacitor element, the fifth MOSFET, and the sixth MOSFET together constitute a π-type or T-type capacitive negative feedback topology; The gates of the fifth and sixth MOS transistors are connected to a first adjustable bias voltage to introduce a series feedback resistor R at the source terminal of the differential input pair transistors. The gate of the source MOS transistor is connected to a second adjustable bias voltage to introduce a source linearly adjustable resistor Rs. The zero-point frequency introduced by the parallel RC network Where Cs is the capacitance value of the capacitor element; By independently adjusting the first adjustable bias voltage and the second adjustable bias voltage, the adjustment of circuit gain and zero frequency is decoupled.
[0010] In some embodiments, the differential input pair includes a first MOS transistor and a third MOS transistor; The gate of the first MOS transistor serves as the non-inverting input terminal of the linearly adjustable unit, and its source is connected to the drain of the fifth MOS transistor, whose drain serves as the inverting output terminal of the linearly adjustable unit. The gate of the third MOS transistor serves as the inverting input of the linearly adjustable unit, and its source is connected to the drain of the sixth MOS transistor, with its drain serving as the non-inverting output of the linearly adjustable unit.
[0011] In some embodiments, the negative capacitance compensation unit includes a second MOS transistor, a fourth MOS transistor, a ninth MOS transistor, a first feedback capacitor, and a second feedback capacitor. The gate of the second MOS transistor is connected to the negative output terminal of the linearly adjustable unit, its source is connected to the drain of the ninth MOS transistor, and its gate is connected to the drain of the fourth MOS transistor through the first feedback capacitor. The gate of the fourth MOS transistor is connected to the non-inverting output terminal of the linearly adjustable unit, its source is connected to the drain of the ninth MOS transistor, and its gate is connected to the drain of the second MOS transistor through the second feedback capacitor. The gate of the ninth MOS transistor is connected to a bias voltage, and its drain is connected to ground.
[0012] In some embodiments, it also includes: The first load unit is connected between the drain of the differential input pair transistors and the power supply voltage; The second load unit is connected between the output terminal of the negative capacitor compensation unit and the power supply voltage. Both the first load unit and the second load unit adopt a capacitively coupled bootstrap structure to improve the low-frequency gain of the circuit.
[0013] In some embodiments, the first load unit includes a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, a first capacitor, and a second capacitor; The source of the tenth MOS transistor is connected to the drain of the first input transistor in the differential input pair, and its gate and source are connected through a first capacitor, while its drain is connected to the power supply voltage; the source of the twelfth MOS transistor is connected to the drain of the second input transistor in the differential input pair, and its gate and source are connected through a second capacitor, while its drain is connected to the power supply voltage. The gate and drain of the eleventh MOS transistor are both connected to the power supply voltage, and its source is connected to the gate of the tenth MOS transistor. The gate and drain of the thirteenth MOS transistor are both connected to the power supply voltage, and its source is connected to the gate of the twelfth MOS transistor.
[0014] In some embodiments, the second load unit includes a fourteenth MOSFET, a fifteenth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, a third capacitor, and a fourth capacitor; The source of the fourteenth MOS transistor is connected to the drain of the second MOS transistor, and its gate and source are connected through a third capacitor, while its drain is connected to the power supply voltage; the source of the sixteenth MOS transistor is connected to the drain of the fourth MOS transistor, and its gate and source are connected through a fourth capacitor, while its drain is connected to the power supply voltage. The gate and drain of the fifteenth MOS transistor are both connected to the power supply voltage, and its source is connected to the gate of the fourteenth MOS transistor. The gate and drain of the seventeenth MOS transistor are both connected to the power supply voltage, and its source is connected to the gate of the sixteenth MOS transistor.
[0015] In some embodiments, the linearly adjustable capacitive negative feedback amplifier circuit is implemented using one of the following processes: silicon-based process, N-type metal-oxide thin-film transistor process, amorphous silicon or polycrystalline silicon thin-film transistor process, P-type organic thin-film transistor process, CMOS complementary metal-oxide semiconductor process, and carbon nanotube process.
[0016] In some embodiments, the MOS transistor in the linearly adjustable capacitive negative feedback amplifier circuit is an N-type transistor or a P-type transistor.
[0017] To achieve the above objectives, another aspect of this application proposes a bandwidth extension method for unipolar transistor amplifier circuits, comprising the following steps: Step S1: Introduce a capacitive negative feedback network between the sources of the input pair transistors in the amplification stage, consisting of a linear region MOS transistor Rs connected in parallel and a capacitor Cs, to construct a zero in the transfer function. ; Step S2: Adjust the gate bias voltage of the linear region MOS transistor Rs to make the zero point The frequency is equal to the dominant pole of the output node of the amplifier stage. The frequency of this is used to achieve pole-zero cancellation; Step S3: Introduce a negative capacitance generating circuit consisting of common-source amplification and cross-coupled Miller capacitors at the drain node of the input pair transistors of the amplification stage to generate an equivalent negative capacitance at this node. ; Step S4: Utilize the equivalent negative capacitance Neutralizing the parasitic capacitance of the node pushes the canceled dominant pole to a higher frequency, achieving a secondary expansion of the bandwidth.
[0018] In some embodiments, the bandwidth expression of the circuit is extended as follows:
[0019] in, R is the transconductance of the input pair, and R is the equivalent resistance of the input pair source in series. For load resistance, The original load capacitance, This is the introduced equivalent negative capacitance value.
[0020] Compared with the prior art, this application has the following beneficial effects: 1) Linearly adjustable bandwidth expansion capability: By using MOSFETs operating in the linear region to replace traditional fixed resistors, the zero-point frequency is continuously adjustable, thereby achieving linear bandwidth adjustment and solving the problem of fixed bandwidth and inability to dynamically adapt in traditional capacitive negative feedback structures.
[0021] 2) Dual Bandwidth Expansion Mechanism: This mechanism organically integrates two bandwidth expansion mechanisms: "source capacitive negative feedback pole-zero cancellation" and "drain negative capacitance load cancellation," generating a synergistic effect that surpasses the bandwidth expansion performance of a simple superposition of single mechanisms. By introducing an equivalent negative capacitance structure using a cross-Miller capacitor, the impact of the output load capacitance on the bandwidth is successfully reduced, further enhancing the bandwidth expansion effect.
[0022] 3) Decoupling adjustment of gain and bandwidth: By independently setting the first adjustable bias voltage VR and the second adjustable bias voltage VRs, the decoupling control of circuit gain and zero frequency is realized, which greatly improves the debugging flexibility and process tolerance of the circuit.
[0023] 4) Unipolar process compatibility: The entire circuit is composed of MOS transistors of the same conductivity type, which is perfectly compatible with pure N-type or pure P-type TFT processes. No complementary devices are required, filling the gap in the design of high-performance broadband amplifiers under unipolar processes.
[0024] 5) Parametric design capability: For the first time, a closed-form analytical expression for the -3dB bandwidth after dual bandwidth extension is clearly proposed, providing circuit designers with a theoretical basis for quantitative optimization and possessing high engineering practicality. Attached Figure Description
[0025] Figure 1 A schematic diagram of the structure of a linear adjustable capacitive negative feedback amplifier circuit provided in one embodiment of this application; Figure 2A schematic diagram of the core circuit structure of a linear adjustable capacitive negative feedback amplifier circuit provided in one embodiment of this application; Figure 3 for Figure 2 A schematic diagram of the equivalent circuit structure of the negative capacitor compensation unit 3 and the second load unit 4; Figure 4 This is a schematic diagram of the structure of a half-equivalent circuit of a linear adjustable capacitive negative feedback amplifier circuit provided in one embodiment of this application; Figure 5 This is a flowchart illustrating a bandwidth expansion method provided in one embodiment of this application. Detailed Implementation
[0026] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.
[0027] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.
[0028] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.
[0029] Furthermore, in the description of this invention, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.
[0030] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.
[0031] Please see Figure 1 , Figure 1 A schematic diagram of the structure of a linear adjustable capacitive negative feedback amplifier circuit provided in one embodiment of this application; In one embodiment, a linearly adjustable capacitive negative feedback amplifier circuit includes a linearly adjustable unit 1, a first load unit 2, a negative capacitance compensation unit 3, and a second load unit 4.
[0032] Input terminals 5 and 6 of the linearly adjustable unit 1 serve as the differential signal input terminals of the linearly adjustable capacitive negative feedback amplifier circuit (where input terminal 5 is the non-inverting input terminal and input terminal 6 is the inverting input terminal). Its inverting output terminal 7 is connected to input terminal 9 of the first load unit 2, and its non-inverting output terminal 8 is connected to input terminal 10 of the first load unit 2. Simultaneously, its inverting output terminal 7 is connected to input terminal 11 of the negative capacitance compensation unit 3, and its non-inverting output terminal 8 is connected to input terminal 12 of the negative capacitance compensation unit 3. Output terminals 7 and 8 of the linearly adjustable unit 1 serve as the differential signal output terminals of the active feedback amplifier circuit, where output terminal 7 is the inverting output terminal and output terminal 8 is the non-inverting output terminal. The inverting output terminal 13 of the negative capacitance compensation unit 3 is connected to input terminal 15 of the second load unit 4, and its non-inverting output terminal 14 is connected to input terminal 16 of the second load unit 4.
[0033] Please see Figure 2 , Figure 2 A schematic diagram of the core circuit structure of a linear adjustable capacitive negative feedback amplifier circuit provided in one embodiment of this application; In one embodiment, the linearly adjustable unit 1 includes transistor M1 (corresponding to the first MOSFET), transistor M3 (corresponding to the third MOSFET), transistor M7 (corresponding to the seventh MOSFET), transistor M8 (corresponding to the eighth MOSFET), and a capacitive negative feedback network 17. The gates of transistors M1 and M3 serve as the differential input terminals 5 and 6 of the linearly adjustable capacitive negative feedback amplifier circuit. The gates of transistors M7 and M8 are shorted and connected to a fixed bias voltage VB1. The capacitive negative feedback network 17 includes transistor M5 (corresponding to the fifth MOSFET), transistor M6 (corresponding to the sixth MOSFET), transistor Ms (corresponding to the source MOSFET), and capacitor Cs (corresponding to the source capacitor). The gates of transistors M5 and M6 are shorted and connected to an adjustable bias voltage VR, and the gate of transistor Ms is connected to an adjustable bias voltage VRs. The first load unit 2 includes transistor M10 (corresponding to the tenth MOS transistor), transistor M11 (corresponding to the eleventh MOS transistor), transistor M12 (corresponding to the twelfth MOS transistor), transistor M13 (corresponding to the thirteenth MOS transistor), capacitor C1 (corresponding to the first capacitor), and capacitor C2 (corresponding to the second capacitor).
[0034] The negative capacitance compensation unit 3 includes transistor M2 (corresponding to the second MOSFET), transistor M4 (corresponding to the fourth MOSFET), capacitor CF1 (corresponding to the first feedback capacitor), and capacitor CF2 (corresponding to the second feedback capacitor). The gates of transistors M2 and M4 serve as the differential input terminals 11 and 12 of the negative capacitance compensation unit 3, and the gate of transistor M9 is connected to a fixed bias voltage VB2. The second load unit 4 includes transistors M14 (corresponding to the fourteenth MOSFET), M15 (corresponding to the fifteenth MOSFET), M16 (corresponding to the sixteenth MOSFET), M17 (corresponding to the seventeenth MOSFET), capacitor C3 (corresponding to the third capacitor), and capacitor C4 (corresponding to the fourth capacitor).
[0035] Please see Figure 3 , Figure 3 For this application Figure 2 A schematic diagram of the equivalent circuit structure of the negative capacitor compensation unit 3 and the second load unit 4; In one embodiment, the second load unit 4 can be equivalent to resistors RD1 and RD2. In the circuit structure composed of the negative capacitance compensation unit 3 and the second load unit 4, without considering the first feedback capacitor CF1 and the second feedback capacitor CF2, the equivalent input capacitance of the circuit input terminals 11 and 12 is represented by Cinput; considering the first feedback capacitor CF1 and the second feedback capacitor CF2, the equivalent input capacitance of the circuit input terminals 11 and 12 is represented by Cinput. express.
[0036] A comprehensive analysis of the circuit reveals the following expression for the low-frequency voltage gain from input terminals 11 and 12 to output terminals 13 and 14:
[0037] Where gm2,4 and ro2,4 correspond to the equivalent transconductance and output impedance of transistors M2 and M4, respectively, and resistors RD1,2 represent the equivalent resistance of half of the circuit of resistors RD1 and RD2.
[0038] Equivalent input capacitance of circuit input terminals 11 and 12 The expression is:
[0039] Where CF1 and CF2 are the equivalent capacitances of the first feedback capacitor CF1 and the second feedback capacitor CF2 in half of the circuit, respectively. Cinput consists of the parasitic capacitance at the circuit input terminal, which is much smaller than the feedback capacitance value, while the circuit voltage gain is much greater than 1. Therefore, the equivalent input capacitance is... The expression can be simplified to:
[0040] By adjusting the circuit voltage gain and feedback capacitor, the circuit structure composed of negative capacitor compensation unit 3 and second load unit 4 can obtain a capacitance at its input terminal. The equivalent negative capacitance.
[0041] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of a half-equivalent circuit of a linear adjustable capacitive negative feedback amplifier circuit provided in one embodiment of this application; In one embodiment, the input terminal 18 of the linearly adjustable unit 1 serves as the input terminal of the half-equivalent circuit of the linearly adjustable capacitive negative feedback amplifier circuit, and its output terminal 19 serves as the output terminal of the half-equivalent circuit of the linearly adjustable capacitive negative feedback amplifier circuit. The linearly adjustable unit 1 includes transistors M1 and M3 (corresponding to the first and third MOS transistors), a resistor R (the equivalent resistance of transistors M5 and M6 in the capacitive negative feedback network 17), a resistor Rs / 2 (the equivalent resistance of the source MOS transistor Ms in the capacitive negative feedback network 17 in the half-circuit), and a capacitor 2Cs (the capacitance corresponding to the source capacitor Cs in the capacitive negative feedback network 17 in the half-circuit). The first load unit 2 is equivalent to resistor R in the half-circuit. D Connected to the output terminal 19 of the linearly adjustable unit 1; the equivalent output load capacitance C of the linearly adjustable capacitive negative feedback amplifier circuit. L 20 is connected to the output terminal 10 of the linearly adjustable unit 1; the equivalent negative capacitance C formed by the negative capacitance compensation unit 3 and the second load unit 4 NCG21 is connected to the output terminal 19 of the linearly adjustable unit 1. The equivalent transconductance of transistors M1 and M3 is used... express.
[0042] For the overall analysis of this circuit, the equivalent negative capacitance C is not considered first. NCG At 21, the voltage transfer function can be expressed as:
[0043] From this, we can obtain the first pole. First Zero Point Second pole The corresponding expression:
[0044]
[0045]
[0046] The capacitive negative feedback network 17 is adjusted so that the first zero wz cancels the first pole wp1, making the second pole wp2, which has a higher frequency, the new dominant pole, thereby expanding the bandwidth. It is worth noting that the resistor Rs in the capacitive negative feedback network 17 is the equivalent resistance of the linear MOS transistor Ms. In this invention, an additional source linear MOS resistor is introduced for transistors M5 and M6 to stabilize the equivalent resistance Rs, thereby stabilizing the zeros introduced by the source MOS transistor and source capacitor, and thus stabilizing the expanded bandwidth of the circuit.
[0047] Consider the equivalent negative capacitance C NCG After connecting 21, the negative capacitor This can reduce the size of the circuit's equivalent output capacitance, thereby further expanding the circuit's bandwidth. Therefore, the circuit's -3dB bandwidth can be expressed as:
[0048] By adjusting Rs and Cs introduced by the linear adjustable unit 1, and the negative capacitance compensation unit 3... This allows for bandwidth expansion.
[0049] In summary, in this embodiment, the linearly adjustable capacitive negative feedback amplifier includes a linearly adjustable unit, a first load unit, a negative capacitance compensation unit, and a second load unit. By employing the linearly adjustable unit, a capacitive negative feedback structure is innovatively introduced into unipolar transistor technology, replacing the resistor in traditional capacitive negative feedback with a linear MOSFET. The resistance value of the feedback structure is stabilized by the source linear MOSFET resistor, effectively achieving bandwidth expansion. Simultaneously, by introducing an equivalent negative capacitance structure using a cross-Miller capacitor, the impact of the output load capacitance on the bandwidth is successfully reduced, further enhancing the bandwidth expansion effect. Furthermore, the first and second load units employ a capacitive bootstrap load structure, achieving further gain enhancement.
[0050] Please see Figure 5 This embodiment also provides a bandwidth extension method for unipolar transistor amplifier circuits, including the following steps: Step S1: Constructing a capacitive negative feedback network.
[0051] A capacitive negative feedback network, consisting of a linear MOSFET Rs and a capacitor Cs connected in series, is introduced between the sources of the input pair of transistors in the amplifier stage. This network constructs a zero in the circuit's transfer function. and a high-frequency pole .
[0052] Step S2: Pole-zero cancellation.
[0053] Adjust the gate bias voltage VRs of the linear region MOSFET Rs, and continuously change the resistance value of Rs to make the zero point The frequency is equal to the dominant pole of the output node of the amplifier stage. The frequency of the system. After pole-zero cancellation is achieved, the system's frequency response is determined by the high-frequency poles. Dominant, bandwidth expansion to .
[0054] Step S3: Construction of negative capacitance compensation network.
[0055] A negative capacitance generating circuit, consisting of common-source amplification and a cross-coupled Miller capacitor, is introduced at the drain node of the input pair transistors in the amplification stage. Utilizing the positive feedback characteristic of the cross-coupled capacitor, an equivalent negative capacitance is generated at this node. .
[0056] Step S4: Load capacitance cancellation.
[0057] The equivalent negative capacitance Connected in parallel to the output node of the amplifier stage to neutralize the parasitic capacitance of that node. The total equivalent capacitance of the output node is determined by... Reduce to ( + The dominant pole frequency is determined by... Upgraded to This enables a secondary expansion of bandwidth.
[0058] Step S5: Parameter Co-optimization.
[0059] Based on the bandwidth expression:
[0060] Collaborative optimization , , , , Parameters such as gain, power consumption, and area are used to maximize the -3dB bandwidth while meeting constraints.
[0061] The method of this embodiment has the following technical features: 1) Linear adjustability: The bandwidth can be continuously and linearly adjusted by continuously adjusting VRs, and adaptive bandwidth configuration is supported; 2) Process compatibility: All steps use only unipolar transistors, without the need for complementary devices, and are perfectly adapted to TFT process; 3) Quantitative design: It provides closed-loop bandwidth expression, supports parametric design flow, and greatly shortens the design cycle.
[0062] In the foregoing description of this specification, references to terms such as "one embodiment," "another embodiment," or "some embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0063] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
[0064] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.
Claims
1. A linear adjustable capacitive negative feedback amplifier circuit, characterized in that, Includes a linearly adjustable unit and a negative capacitance compensation unit; The linearly adjustable unit includes a differential input pair transistor and a capacitive negative feedback network. The differential input pair transistor is used to receive differential input signals and generate differential output signals. The capacitive negative feedback network is connected between the sources of the differential input pair transistor. The negative capacitance compensation unit is connected to the drain of the differential input pair transistors; The capacitive negative feedback network includes at least one source MOSFET operating in the linear region and a capacitor connected in parallel with the source MOSFET. The source MOSFET and the capacitor form a parallel RC network, introducing an adjustable zero point in the circuit transfer function. By adjusting the gate bias voltage of the source MOSFET, the equivalent impedance of the parallel RC network is linearly adjusted, thereby continuously adjusting the frequency position of the adjustable zero point.
2. The circuit according to claim 1, characterized in that, The capacitive negative feedback network also includes a fifth MOSFET and a sixth MOSFET; The drain of the fifth MOS transistor is connected to the source of the first input transistor in the differential input pair, and the drain of the sixth MOS transistor is connected to the source of the second input transistor in the differential input pair. The source and drain of the source MOSFET are connected between the source of the fifth MOSFET and the source of the sixth MOSFET. The two terminals of the capacitor element are respectively connected to the source of the fifth MOS transistor and the source of the sixth MOS transistor, thereby forming a parallel connection with the source MOS transistor.
3. The circuit according to claim 2, characterized in that, The source MOSFET, the capacitor element, the fifth MOSFET, and the sixth MOSFET together constitute a π-type or T-type capacitive negative feedback topology; The gates of the fifth and sixth MOS transistors are connected to a first adjustable bias voltage to introduce a series feedback resistor R at the source terminal of the differential input pair transistors. The gate of the source MOS transistor is connected to a second adjustable bias voltage to introduce a source linearly adjustable resistor Rs. The zero-point frequency introduced by the parallel RC network Where Cs is the capacitance value of the capacitor element; By independently adjusting the first adjustable bias voltage and the second adjustable bias voltage, the adjustment of circuit gain and zero frequency is decoupled.
4. The circuit according to claim 1, characterized in that, The differential input pair includes a first MOSFET and a third MOSFET; The gate of the first MOS transistor serves as the non-inverting input terminal of the linearly adjustable unit, and its source is connected to the drain of the fifth MOS transistor, whose drain serves as the inverting output terminal of the linearly adjustable unit. The gate of the third MOS transistor serves as the inverting input of the linearly adjustable unit, and its source is connected to the drain of the sixth MOS transistor, with its drain serving as the non-inverting output of the linearly adjustable unit.
5. The circuit according to claim 1, characterized in that, The negative capacitance compensation unit includes a second MOS transistor, a fourth MOS transistor, a ninth MOS transistor, a first feedback capacitor, and a second feedback capacitor. The gate of the second MOS transistor is connected to the negative output terminal of the linearly adjustable unit, its source is connected to the drain of the ninth MOS transistor, and its gate is connected to the drain of the fourth MOS transistor through the first feedback capacitor. The gate of the fourth MOS transistor is connected to the non-inverting output terminal of the linearly adjustable unit, its source is connected to the drain of the ninth MOS transistor, and its gate is connected to the drain of the second MOS transistor through the second feedback capacitor. The gate of the ninth MOS transistor is connected to a bias voltage, and its drain is connected to ground.
6. The circuit according to claim 1, characterized in that, Also includes: The first load unit is connected between the drain of the differential input pair transistors and the power supply voltage; The second load unit is connected between the output terminal of the negative capacitor compensation unit and the power supply voltage. Both the first load unit and the second load unit adopt a capacitively coupled bootstrap structure to improve the low-frequency gain of the circuit.
7. The circuit according to claim 6, characterized in that, The first load unit includes a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, a first capacitor, and a second capacitor; The source of the tenth MOS transistor is connected to the drain of the first input transistor in the differential input pair, and its gate and source are connected through a first capacitor, while its drain is connected to the power supply voltage; the source of the twelfth MOS transistor is connected to the drain of the second input transistor in the differential input pair, and its gate and source are connected through a second capacitor, while its drain is connected to the power supply voltage. The gate and drain of the eleventh MOS transistor are both connected to the power supply voltage, and its source is connected to the gate of the tenth MOS transistor. The gate and drain of the thirteenth MOS transistor are both connected to the power supply voltage, and its source is connected to the gate of the twelfth MOS transistor.
8. The circuit according to claim 6, characterized in that, The second load unit includes a fourteenth MOSFET, a fifteenth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, a third capacitor, and a fourth capacitor; The source of the fourteenth MOS transistor is connected to the drain of the second MOS transistor, and its gate and source are connected through a third capacitor, while its drain is connected to the power supply voltage; the source of the sixteenth MOS transistor is connected to the drain of the fourth MOS transistor, and its gate and source are connected through a fourth capacitor, while its drain is connected to the power supply voltage. The gate and drain of the fifteenth MOS transistor are both connected to the power supply voltage, and its source is connected to the gate of the fourteenth MOS transistor. The gate and drain of the seventeenth MOS transistor are both connected to the power supply voltage, and its source is connected to the gate of the sixteenth MOS transistor.
9. A method for bandwidth expansion applied to a unipolar transistor amplifier circuit, characterized in that, Includes the following steps: A capacitive negative feedback network consisting of a linear MOS transistor Rs connected in parallel and a capacitor Cs is introduced between the sources of the input pair of transistors in the amplification stage, constructing a zero in the transfer function. ; Adjust the gate bias voltage of the linear region MOS transistor Rs to make the zero point The frequency is equal to the dominant pole of the output node of the amplifier stage. The frequency of this is used to achieve pole-zero cancellation; A negative capacitance generating circuit, consisting of common-source amplification and cross-coupled Miller capacitors, is introduced at the drain node of the input pair transistors in the amplification stage to generate an equivalent negative capacitance at this node. ; Using the equivalent negative capacitance Neutralizing the parasitic capacitance of the node pushes the canceled dominant pole to a higher frequency, achieving a secondary expansion of the bandwidth.
10. The bandwidth expansion method according to claim 9, characterized in that, After extension, the bandwidth expression of the circuit is: in, R is the transconductance of the input pair, and R is the equivalent resistance of the input pair source in series. For load resistance, The original load capacitor, This is the introduced equivalent negative capacitance value.