A source adjustable resistance circuit for use in a high speed differential amplifier

By using a single MOSFET and a precision feedback control loop in a high-speed differential amplifier, the area and parasitic capacitance problems of traditional resistor array solutions are solved, achieving area reduction, parasitic capacitance reduction, and high-frequency performance improvement, making it suitable for GHz-level high-speed circuits.

CN122268292APending Publication Date: 2026-06-23CHONGQING XINLONG SEMICONDUCTOR TECHNOLOGY CO LTD
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Patent Information

Application Number
CN202610331962.8
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-03-18
Publication Date
2026-06-23

AI Technical Summary

Technical Problem

Traditional differential amplifiers with source-tunable resistor arrays suffer from problems such as large chip area, high parasitic capacitance, low adjustment accuracy, and complex layout, which affect the integrity of high-speed signals and high-frequency response.

Method used

By replacing the traditional resistor array with a single MOSFET, and adjusting the gate voltage of the MOSFET through a precision feedback control loop, a continuously and accurately adjustable degradation resistance is achieved, reducing parasitic capacitance and footprint.

Benefits of technology

It achieves an area reduction of over 70%, a significant reduction in parasitic capacitance, an increase in bandwidth, precise adjustment, a simple layout, and improves the high-frequency performance and matching of high-speed signals.

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Abstract

The application relates to a source adjustable resistance circuit for a high-speed differential amplifier, belonging to the technical field of high-speed analog and radio frequency integrated circuits, comprising a high-speed differential amplifier, a degeneration resistance unit and a control unit; the degeneration resistance unit is composed of a first MOS transistor; the source and the drain of the first MOS transistor are respectively connected to two source nodes of a differential pair transistor of the high-speed differential amplifier, serving as source degeneration resistance thereof, and the gate voltage of the first MOS transistor is generated by the control unit; the control unit is used for generating the gate control voltage of the first MOS transistor. The application replaces a large resistance array with a single MOS transistor, greatly reduces the area, greatly reduces the chip cost, significantly reduces the parasitic capacitance of the degeneration node to the ground, and improves the amplifier bandwidth.
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