Circuit and method providing a signal path with an adjustable attenuator

Abstract

The present disclosure relates to circuits and methods that provide a signal path with an adjustable attenuator. A system (100) includes a transceiver with at least one receive signal chain (105, 108) and at least one transmit signal chain (111). The receive signal chain can be coupled to an adjustable capacitive attenuator (103, 106). An automatic gain control (120) circuit can be configured to measure gain in the receive signal chain and adjust an amount of gain by adjusting attenuation at the adjustable capacitive attenuator.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit of Indian Provisional Patent Application No. 202441101245, filed on December 20, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This application relates to an electronic circuit and method, and in a particular embodiment, to a circuit and method for providing a signal path with an adjustable attenuator. Background Technology

[0004] Radio frequency (RF) transceivers are used in a variety of devices that rely on wireless communication. These RF transceivers can operate at various frequencies depending on their application. For example, cellular phones, Wi-Fi devices, Bluetooth devices, etc., operate at various frequencies and can use RF transceivers to receive signals over the air. Summary of the Invention

[0005] According to an embodiment, an electronic circuit includes: a first signal path comprising: a first current-mode mixer having first and second inputs and first and second outputs; a first amplifier circuit having first and second inputs respectively coupled to the first and second outputs of the first current-mode mixer; and a first adjustable capacitor attenuator circuit having first and second outputs respectively coupled to the first and second inputs of the first current-mode mixer; and a second signal path comprising: a second current-mode mixer having first and second inputs and first and second outputs; a second amplifier circuit having first and second inputs respectively coupled to the first and second outputs of the second current-mode mixer; and a second adjustable capacitor attenuator circuit having first and second outputs respectively coupled to the first and second inputs of the second current-mode mixer.

[0006] According to an embodiment, an electronic circuit includes: an antenna terminal; a low-noise transimpedance amplifier (LNTA) having an input coupled to the antenna terminal and first and second outputs; a current-mode mixer having first and second inputs; and an adjustable capacitor attenuator having a first terminal coupled to the first output of the LNTA and coupled to the first input of the current-mode mixer, and a second terminal coupled to the second output of the LNTA and coupled to the second input of the current-mode mixer.

[0007] According to an embodiment, a method includes: operating a receive signal chain at a first gain level, wherein the receive signal chain includes a capacitor attenuator having first and second terminals respectively coupled to first and second inputs of a current-mode mixer; adjusting a gain setting of the receive signal chain to a second gain level, wherein the second gain level is lower than the first gain level, without adjusting the capacitance of the capacitor attenuator; measuring a signal at the second gain level; and, in response to measuring the signal, adjusting the gain setting to a third gain level lower than the second gain level, including adjusting the capacitance of the capacitor attenuator to achieve the third gain level, wherein the third gain level is lower than the second gain level. Attached Figure Description

[0008] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 These are illustrations of example systems based on some embodiments;

[0010] Figure 2 These are illustrations of an example system for receiving wireless signals according to some embodiments; and

[0011] Figure 3 This is an illustration of an example system for receiving wireless signals according to some embodiments;

[0012] Figure 4 This is an illustration of an example analog-to-digital converter (ADC) resource that can be used in a receiver according to some embodiments;

[0013] Figure 5 This is an illustration of an adjustable capacitor attenuator circuit architecture according to some embodiments;

[0014] Figure 6 This is an illustration of an example receiving AGC circuit according to some embodiments;

[0015] Figure 7 These are illustrations of example configurations for receiving operations of an AGC circuit according to some embodiments; and

[0016] Figure 8 This is an illustration of an example method for adjusting gain in a circuit according to some embodiments.

[0017] Unless otherwise stated, corresponding reference numerals and symbols in different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the preferred embodiments, and are not necessarily drawn to scale. Detailed Implementation

[0018] This disclosure is described with reference to the accompanying drawings. The drawings are provided merely for illustrative purposes. For illustration, several aspects of this disclosure are described below with reference to examples. It should be understood that many specific details, relationships, and methods are set forth to provide an understanding of this disclosure. This disclosure is not limited to the described order of actions or events, as some actions may occur in a different order and / or simultaneously with other actions or events. Furthermore, implementing the method according to this disclosure does not require all of the described actions or events.

[0019] The following description illustrates various specific details to provide a thorough understanding of several exemplary embodiments based on the description. Embodiments may be obtained without one or more specific details or with other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so as not to obscure different aspects of the embodiments. References to "embodiment" in this specification indicate that a particular configuration, structure, or feature described with respect to an embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" that may appear in different places in this specification do not necessarily refer exactly to the same embodiment. Furthermore, specific forms, structures, or features may be combined in any suitable manner in one or more embodiments.

[0020] The receiver of a communication device, such as a wireless transceiver, may contain a set of signal processing stages arranged in the receiving signal chain. These stages may include one or more amplifier stages. To improve the reception of weaker signals, the combined gain of the amplifier stages can be relatively high. However, applying a large gain to a stronger signal can saturate the amplified signal, causing distortion (e.g., clipping) in the amplified signal, which can make it more difficult to extract data from the signal. In extreme cases, data may be completely lost. Therefore, some receivers use automatic gain control (AGC) mechanisms to dynamically control the gain based on signal strength.

[0021] Some embodiments may employ an AGC algorithm that uses a predetermined order to reduce the gain between devices in the receive signal chain. For example, an example AGC algorithm may reduce the gain of the downstream amplifier in the receive chain, and if reducing the gain of the amplifier to an operating minimum is insufficient to avoid saturation, the AGC algorithm may move to the next upstream component to reduce the gain, and repeat the process as necessary.

[0022] Some embodiments include an adjustable attenuator, which can be implemented in the receive signal chain between the amplifier circuit and the mixer. The adjustable attenuator provides more or less attenuation, where more attenuation corresponds to reduced gain, and less attenuation corresponds to increased gain. Therefore, the attenuator in the receive signal path can provide another component where the gain of the signal path can be reduced overall to avoid saturation.

[0023] In one example, an adjustable attenuator can be implemented as a capacitor attenuator. For instance, a capacitor attenuator can have multiple branches, each with at least one capacitor and a transistor that can be controlled by an AGC circuit. The branches can be arranged in parallel between the differential output terminals of the amplifier circuit. A capacitor attenuator causes attenuation by reducing the amount of current flowing from the amplifier circuit to the mixer through the differential output terminals. In one example, when more branches of the capacitor attenuator are controlled to be on, this reduces capacitance and increases attenuation (reduces gain), while when fewer branches of the capacitor attenuator are controlled to be on, this increases capacitance and reduces attenuation (increases gain).

[0024] The AGC circuit can measure the signal level at a downstream component (e.g., an analog-to-digital converter, ADC) and can increase or decrease the gain within the received signal chain based on the measurement results. The AGC circuit can adjust a capacitor attenuator as appropriate to increase or decrease the signal level at the downstream component. Furthermore, the capacitor attenuator can be used in systems where the input amplifier circuitry is implemented as a low-noise transimpedance amplifier (LNTA) or a low-noise amplifier (LNA) implemented separately from the transimpedance amplifier (TA).

[0025] Various embodiments can offer advantages. For example, some embodiments may implement an adjustable capacitor attenuator between the input amplifier circuit and the mixer, such that it is upstream of the mixer and other components (e.g., intermediate frequency amplifier, variable gain amplifier, analog-to-digital converter). Therefore, the upstream components can be advantageously designed for a smaller dynamic range because the gain can be reduced upstream of the mixer.

[0026] In another example, an adjustable capacitor attenuator can be implemented without a resistor, allowing the impedance of the attenuator to come almost entirely from the capacitance of the capacitor in the branch. This advantageously allows for increasing the attenuation step size without increasing the attenuator's resistance, thus avoiding a significant increase in noise. Therefore, the attenuator can be adjusted without negatively impacting the noise factor (NF) or signal-to-noise ratio (SNR).

[0027] In another example, some embodiments can implement adjustable capacitor attenuators without significantly increasing the circuit size. Therefore, the advantageous function of the attenuator can be achieved without negatively impacting the semiconductor area.

[0028] Figure 1 This is an illustration of an example system 100 according to some embodiments. In this example, system 100 may be implemented as a transceiver that can be used to receive and transmit RF signals.

[0029] System 100 includes input amplifier circuitry 102, which may include any suitable input amplifier component. Examples of suitable input amplifier components may be an LNTA, or a combination of an LNA and one or more TAs. Input amplifier circuitry 102 can receive RF signals from front-end module 113 and antenna 114. For example, receive signal chains 105, 108 may share front-end module 113 and antenna 114 with transmit signal chain 111. Front-end module 113 may include, for example, filters and switches, such that antenna 114 can be used for both over-the-air transmission and reception. For example, front-end module 113 may include switches to perform multiplexing over time, such that antenna 114 is used for reception at some times and for transmission at other times. Front-end module 113 may also include filters for removing unwanted signals. However, the scope of the implementation is not limited to amplifier circuitry 102 sharing antenna 114 with power amplifier 112. In fact, the scope of the implementation may include power amplifier 112, whose own antenna or antenna array is separate from the antenna or antenna array used for input amplifier circuitry 102.

[0030] The input amplifier circuit 102 includes a set of differential outputs coupled to RX signal chains 105 and RX signal chains 108 via attenuators 102 and 103, respectively. In this example, the positive (+) conductor of each differential output is labeled P, and the negative (-) conductor of each differential output is labeled M.

[0031] In some embodiments, capacitor attenuator 103 is implemented in, or coupled to, the RX signal chain 105 between a set of differential outputs of input amplifier circuit 102. Similarly, capacitor attenuator 106 may be implemented in, or coupled to, the RX signal chain 108 between a set of differential outputs of input amplifier circuit 102. (See also: Regarding...) Figure 5 To explain in more detail, capacitor attenuator 103 may comprise multiple branches, each having one or more capacitors and one or more transistors. Automatic gain control (AGC) circuitry 120 may apply control signals to each branch to increase or decrease the capacitance, thereby affecting the attenuation provided by capacitor attenuator 103. The same may be true for capacitor attenuator 106.

[0032] In some embodiments, capacitor attenuator 103 is coupled to receive signal chain 105 via a set of coupling capacitors 104. Similarly, capacitor attenuator 106 may be coupled to receive signal chain 108 via a set of coupling capacitors 107. Each coupling capacitor has a first terminal coupled to input amplifier circuit 102 and a second terminal coupled to its associated receive signal chain 105 or 108.

[0033] System 100 includes a receive signal chain 105 and a receive signal chain 108. In one example, receive signal chain 105 is associated with an in-phase (I) signal, and receive signal chain 108 is associated with a quadrature (Q) signal. Both RX signal chains 105 and 108 may contain components with adjustable gain. Examples of components in receive signal chains 105 and 108 may include mixers, filters, amplifiers, and / or other suitable components. Thus, in some examples, each receive signal chain 105, 108 may include a mixer for downsampling the signal to baseband or intermediate frequency, one or more filters and amplifiers for gain adjustment, and analog-to-digital converter (ADC) circuitry. At the output of each receive signal chain 105, 108 is a digital signal, which may be received by digital processing circuitry 110. Examples of digital processing components may include one or more general-purpose or custom processors or controllers coupled to memory and configured to execute instructions in memory, hardware accelerators, field-programmable gate arrays (FPGAs), and other (e.g., digital) circuitry that allows data processing and operation of the control system 100.

[0034] The transmit signal chain 111 is also coupled to the digital processing circuitry 110, and it can receive digital signals that can be converted into analog signals for transmission as RF signals via the antenna 114. For example, the transmit signal chain 111 may include a digital-to-analog converter (DAC) circuit, an amplifier, a filter, a mixer, etc. One or more components within the transmit signal chain 111 may include variable gain. The transmit signal chain 111 can provide the RF signal to the power amplifier 112. The power amplifier 112 can amplify the RF signal to an appropriate level for transmission via the wireless medium by the antenna 114.

[0035] The receiving AGC circuit 120 can control any receiving component, such as the input amplifier circuit 102, attenuators 103 and 106, and the adjustable gain in the receiving signal chains 105 and 108. (About...) Figure 7 A more detailed description is provided of example AGC algorithms that can be implemented by the receiving AGC circuit 120.

[0036] System 100 can be implemented on one or more chips. Each chip can be implemented using a semiconductor die in a semiconductor package. In one example, the entire system 100 can be implemented on a single integrated circuit (IC) chip. In another example, some parts of system 100 (e.g., antenna 114) may be on a separate chip or not on a chip at all. In yet another example, system 100 may be implemented as part of a larger system-on-a-chip, incorporating other circuitry such as modems, processor cores, and the like. In yet another example, all or part of the input amplifier circuitry 102 may be implemented separately from the chip on which other parts of system 100 are implemented (e.g., the low-noise transimpedance amplifier and antenna are implemented off-chip).

[0037] System 100 can be used in any suitable application, such as in Wi-Fi access points, smartphones, tablets or computers, Bluetooth devices (such as Bluetooth Low Energy (BLE) devices), ultra-wideband (UWB) devices, radar devices, key cards or cards for access control, etc.

[0038] Figure 2 This is an illustration of an example system 200 for receiving wireless signals according to some embodiments. For ease of illustration, in Figure 2 The transmit signal chain is not shown, but it should be understood that system 200 can be implemented using a transmit signal chain.

[0039] Example system 200 can be based on the above text about Figure 1 The principles discussed are used for implementation. For example, LNA 201, TA 202, and TA 203 can correspond to... Figure 1 The input amplifier circuit 102. Furthermore, mixer circuit 204, amplifiers 206 and 212, and ADC 214 can correspond to the receive signal chain 105. Mixer 205, amplifiers 209 and 213, and ADC 215 can correspond to the receive signal chain 108.

[0040] In some embodiments, LNA 201 is configured to receive RF signals over the air via antenna 114 and front-end module 113. LNA 201 can provide a certain amount of gain to the RF signal and can convert the RF signal from single-ended to differential. LNA 201 has differential outputs that are separated between an in-phase signal path (containing mixer circuit 204) and a quadrature-phase signal path (containing mixer circuit 205). LNA 201 may have variable gain. Slot circuit 218 is implemented between the differential output conductors of LNA 201, and slot circuit 218 may include at least a capacitor and an inductor. For example, both the capacitor and inductor of slot circuit 218 may be implemented in parallel between the positive and negative output terminals of LNA 201. Slot circuit 218 can be provided as a filter and used for impedance matching. Furthermore, in this example, slot circuit 218 is non-adjustable and implemented separately from the adjustable capacitor attenuator circuits 103, 106.

[0041] The differential outputs of LNA 201 are separated, such that TA 202 is coupled to both the positive and negative output terminals of LNA 201, and the same applies to TA 203. TA 202 provides adjustable gain and converts the voltage signal from the output of LNA 201 into a current-mode signal. TA 202 contains current-mode differential outputs with positive and negative terminals. TA 203 is implemented in a similar manner in this example.

[0042] An adjustable capacitor attenuator circuit 103 is coupled between the positive and negative output terminals of TA 202, and coupling capacitors 104 are also coupled to the positive and negative output terminals of TA 202, respectively. Adjustable capacitor attenuator circuit 106 and coupling capacitors 107 are arranged in a similar manner relative to TA 203.

[0043] Mixer circuit 204 is coupled to the positive and negative output terminals of TA 202 via coupling capacitor 104 and adjustable capacitor attenuator circuit 103. Similarly, mixer circuit 205 is coupled to the positive and negative output terminals of TA 202 via coupling capacitor 107 and adjustable capacitor attenuator circuit 106.

[0044] Each of mixer circuits 204 and 205 is coupled to oscillator circuit 216 via a corresponding clock input. Oscillator circuit 216 can be implemented in any suitable manner, such as as a PLL or other suitable circuit. The outputs of oscillator circuit 216 are split such that the output of oscillator 216 received by mixer circuit 205 is phase-shifted by phase-shift circuit 217 by 90°. In contrast, the output of oscillator 216 received by mixer circuit 204 is not phase-shifted. Therefore, mixer circuit 204 is implemented in phase, while mixer circuit 205 is implemented in quadrature phase. Each of mixer circuits 204 and 205 may include adjustable gain. Furthermore, mixer circuits 204 and 205 can downscale the frequency of the RF signal, such as from the gigahertz range to the megahertz range. However, the scope of the implementation is not limited to any particular operating frequency range. Therefore, taking 3.2 GHz and 2.4 GHz as examples, and the scope of the implementation can include any suitable operating frequency range, such as between 5 GHz and 13 GHz, or different frequency ranges, such as above 13 GHz or below 2.3 GHz, such as frequencies below 1 GHz.

[0045] In some embodiments, mixers 204 and 205 are current-mode mixers.

[0046] In some embodiments, mixer circuits 204 and 205 down-convert their respective I and Q current-mode signals to intermediate frequency or baseband. Furthermore, each of mixer circuits 204 and 205 includes a differential current-mode output.

[0047] In some embodiments, the intermediate frequency amplifier (IFA) 206 receives the differential output from the mixer circuit 204 at its input and provides a gain-adjusted differential voltage output. For example, resistor 207 is coupled from the positive input to the positive output of IFA 206, and resistor 208 is coupled from the negative input to the negative output of IFA 206. Each of resistors 207 and 208 can be implemented as adjustable to change the gain level provided by IFA 206. Furthermore, IFA 206 may include an analog filter to reduce unwanted frequencies from the intermediate frequency or baseband signal.

[0048] In some embodiments, IFA 209 is implemented similarly to IFA 206. For example, resistors 210 and 211 may be implemented similarly to resistors 207 and 208 to provide adjustable gain. Furthermore, IFA 209 may provide analog filtering to reduce unwanted frequencies from the intermediate frequency or baseband signal.

[0049] In some embodiments, variable gain amplifier (VGA) 212 receives the gain-adjusted differential output of IFA 206 and provides adjustable gain to the I signal. VGA 213 receives the gain-adjusted differential output of IFA 209 and provides adjustable gain to the Q signal. VGA 212 and VGA 213 may be implemented as operational amplifiers or other suitable amplifier circuit architectures. VGA 212 generates a differential voltage output, which is provided to ADC 214. VGA 213 generates a differential voltage output, which is provided to ADC 215. ADCs 214 and 215 perform analog-to-digital conversion on the corresponding I and Q signals and provide corresponding digital outputs to digital processing circuitry 110.

[0050] In some embodiments, the receiving AGC circuit 120 can control the adjustable gain of various components of the system 200. For example, the receiving AGC circuit 120 can provide control signals to each of the LNA 201, TA 202 and 203, adjustable capacitor attenuators 103 and 106, mixers 204 and 205, resistors 207-211, and VGA 212 and 213.

[0051] Figure 3 This is an illustration of an example system 300 for receiving RF signals according to some embodiments. System 300 can be configured according to the above description... Figure 1 The concepts discussed are for implementation, but for ease of explanation, Figure 3 The transmission signal chain is omitted. System 300 is similar to... Figure 2 System 200, but instead of using LNA and TA, System 300 uses LNTA 310 to provide current-mode differential RF signals to mixers 204 and 205.

[0052] The LNTA 310 is configured to receive a single-ended RF signal from the antenna 114 via the front-end module 113. The LNTA 310 can then provide adjustable gain and convert the single-ended voltage to a differential current-mode output. In this example, the LNTA 310 does not include a slot (e.g., slot 218) at its differential output terminals (or as part of the LNTA 310). Examples of LNTA architectures that can be used in LNTA310 are described in U.S. patent applications entitled “CIRCUIT HAVING MULTIPLE CASCODE AMPLIFIERS AND CONTROLLABLE COMPONENTS” associated with Attorney General’s Case No. T105611US01 and “CIRCUIT HAVING MULTIPLE CASCODE AMPLIFIERS” associated with Attorney General’s Case No. T105917US01, both of which were filed on the same day and are incorporated herein by reference.

[0053] The differential outputs of LNTA 310 are split, such that the positive and negative conductors are coupled to the inputs of mixer circuit 204 and mixer circuit 205, respectively.

[0054] Adjustable capacitor attenuators 103 and 106 are implemented between the positive and negative conductors at the inputs of mixer circuits 204 and 205, respectively. Similarly, coupling capacitor 104 couples mixer circuit 204 to the differential output terminal of LNTA 310, and coupling capacitor 107 couples mixer circuit 205 to the differential output terminal of LNTA 310.

[0055] Mixer circuits 204 and 205, IFA 206 and 209, VGA 212 and 213, and ADC 214 and 215 can be related to the above. Figure 2 The same approach is being discussed.

[0056] Although Figure 2 and 3 ADC 214 implemented in the I signal path and ADC 215 implemented in the Q signal path are shown, but various embodiments may share ADC resources (e.g., a single ADC) between the I signal path and the Q signal path. Figure 4 Example ADC resource 400 is shown, which can be used in a receiver, such as those mentioned above. Figure 1-3 The receivers discussed.

[0057] The receive multiplexer 401 includes a first input for differential signals from I-signal paths, such as the output from VGA 212, and a second input for Q-signal paths, such as the output from VGA 213. The multiplexer 401 can be controlled to provide time-division multiplexing, such that at some times the multiplexer 401 outputs differential current-mode signals from I-signal paths and at other times it outputs differential current-mode signals from queue paths.

[0058] ADC 402 receives the output of multiplexer 401 at its input. Therefore, ADC 402 receives only one of the differential current-mode signals I or Q at a given time. In some instances, ADC 402 may be implemented as a single ADC circuit, such as one of ADC 214 or 215. ADC 402 converts the signal at its input into a digital signal at its output. ADC 402 provides the output digital signal to digital processing circuitry 110.

[0059] Figure 1 System 100 can be adapted to utilize the architecture of ADC resource 400 by outputting analog current-mode I signals and analog current-mode Q signals from corresponding signal chains 105 and 108 to multiplexers (such as multiplexer 402). Alternatively, the outputs of VGA 212 and 213 can be applied to the multiplexer (e.g., ADC 214 and 215 can be omitted, and the outputs of VGA 212 and 213 can be used instead). Figure 4 Multiplexer 401) for adjustment Figure 2 System 200. It can be adjusted in a similar way. Figure 3 System 300.

[0060] Figure 5 This is an illustration of an example adjustable capacitor attenuator circuit architecture 500 according to some embodiments. In some embodiments, Figure 1-3 The adjustable capacitor attenuator circuits 103 and 106 can be adjusted according to... Figure 5 The architecture shown is 500 to be implemented.

[0061] exist Figure 5 In the example, capacitors 530 and 540 are coupling capacitors, and they may correspond to a set of coupling capacitors 104 and 107. For example, coupling capacitors 530 and 540 are implemented between the output of the adjustable capacitor attenuator circuit 501 and the differential current-mode input of a mixer (e.g., mixer circuit 204 or 205). In other words, coupling capacitor 530 has a first terminal coupled to the output of the adjustable capacitor attenuator circuit 501 and a second terminal coupled to the first input of the mixer. Similarly, coupling capacitor 540 has a first terminal coupled to the output of the adjustable capacitor attenuator circuit 501 and a second terminal coupled to the second input of the mixer.

[0062] The adjustable capacitor attenuator circuit 501 includes multiple branches (N) coupled between the positive and negative output terminals of the input amplifier circuit. In this example, N can be a suitable positive integer. The first branch includes a first capacitor 511, a second capacitor 512, and a transistor 510. The transistor 510 can be controlled by a signal AGC1 from the receiving AGC circuit 120. When the transistor 510 conducts current, it conducts current between the positive and negative input terminals of the input amplifier, thereby providing attenuation.

[0063] The Nth branch includes a first capacitor 521, a second capacitor 522, and a transistor 520, and is controlled by the control signal AGCN. When the transistor 520 conducts current, it conducts current between the positive and negative input terminals of the input amplifier, the same as the first branch described above.

[0064] exist Figure 5 In the examples shown, increasing the capacitance increases attenuation, and decreasing the capacitance decreases attenuation. In some examples, the sizes of capacitors 511, 512, 521, and 522 can be selected such that when the first branch is on and no other branches are on, the gain decreases by 6 dB, and each additional branch, when on, further decreases the gain by 6 dB. For example, when only the first branch is on, the adjustable capacitor attenuator circuit 501 can decrease the gain by 6 dB, while turning on the second branch provides a total gain reduction of 12 dB, and turning on the third branch provides a total gain reduction of 18 dB, and so on. However, the capacitance provided by the individual capacitors 511, 512, 521, and 522 can be selected according to any suitable criteria to provide any desired gain step.

[0065] The above examples can be implemented using digital control signals from the receiving AGC circuit 120. Therefore, the digital control signals will cause a given transistor (e.g., transistors 510 and 520) to turn on or off. In contrast, another example implementation can use analog control signals at the control terminals of transistors 510-520. The analog control signals can be configured to provide any suitable transistor operation, such as on (saturation region), off (cutoff region), or linear region operation. In the linear operating region, the transistor (e.g., transistor 510) can conduct some current, although this current is less than the current in its saturation region. However, operation in the linear region can involve a greater impedance due to the transistor itself compared to the impedance expected in the saturation operating region. The receiving AGC circuit 120 can be suitably configured to apply control signals AGC1-AGCN to provide the desired attenuation.

[0066] Figure 6 This is a diagram of a receiving AGC circuit 120 according to some embodiments. Specifically, Figure 6 The receiving AGC circuit 120 is configured to provide appropriate control signals to various components of the system 100, 200 and / or 300 to control the gain on both the I signal path and the Q signal path.

[0067] In one example, the receiving AGC circuit 120 can measure the signal levels at ADCs 214 and 215, as illustrated by the input signals from ADC_I and ADC_Q. The receiving AGC circuit 120 can use any suitable technique to measure gain, such as measuring the amplitude of the current or voltage at the ADC input, measuring the signal swing at the ADC input, measuring the signal swing at the ADC output, receiving digital measurements from the ADC itself, etc. In any case, the measured signal provides a representation of the total gain provided by the signal path and its various components.

[0068] In response to signal measurements, the receiving AGC circuit 120 can provide control signals to control the gain. For example, signals AGC VGA_I and AGC VGA_Q can be used to control the gain at VGA 212 and 213. Signals AGC IFA_I and AGC IFA_Q can be used to control the gain at IFA 206 and 209, such as by adjusting resistors 207, 208, 210, and 211. In another example, the receiving AGC circuit 120 can use signals AGC IFA_I and AGC IFA_Q to appropriately adjust the filtering properties of IFA 206 and 209. The signal AGC LNTA can be used to adjust the gain at LNTA 301, as described in U.S. Patent Application No. T105611US01 entitled "Circuit with Multiple Common-Source Cascode Amplifiers and Controllable Components". Signals AGC TA and AGC LNA can be used to adjust the corresponding gain levels at TA 202 and 203 and LNA 201. Signals AGC1-AGCN can be used to adjust the gain level at one or more adjustable capacitor attenuator circuits (e.g., 103 and 106).

[0069] Figure 7This is an illustration of an example configuration for receiving operation of AGC circuit 120 according to some embodiments. The column labeled "Step" lists 11 gain steps. Each row in the table corresponds to a single gain step among those gain steps. The column labeled "LNTA" shows the gain step setting for LNTA 301, the columns labeled "ATT 103, 106" show the gain step settings for adjustable capacitor attenuator circuits 103 and 106, the column labeled "MIXER" shows the gain step settings for mixers 204, 205, and the column labeled "IFA" shows the gain step settings for IFA 206 and 209. Various embodiments may include more or fewer columns corresponding to more or fewer adjustable components.

[0070] The column labeled Gain corresponds to the gain level measured at a specific time for a specific gain step. For example, the receiving AGC circuit 120 can measure a gain of 52 dB at gain step 1. The column labeled NF represents the noise figure of the I and Q signal paths at a specific time for a specific gain step. In this example, the gain steps can be implemented sequentially by the receiving AGC circuit 120, such that the receiving AGC circuit 120 can first implement gain step 1, then gain step 2, and so on as needed to reduce the gain, where gain step 11 is the last available gain step. Of course, other embodiments may have more or fewer gain steps as needed. Furthermore, the specific figures given for the gain in the gain column and the noise figure in the NF column are examples, and other embodiments may be adapted for use with different gain levels and noise figures.

[0071] With each increase in the gain step size, the gain measured at the ADC by the receiving AGC circuit 120 decreases, and the noise figure increases. Of course, the specific figures for gain and noise figure are for illustrative purposes only, and the scope of implementations can include any receiver or transceiver providing any suitable level of gain and having any suitable number of gain steps.

[0072] The IFA has three different gain step settings that can be adjusted by the receiving AGC circuit 120. Starting with gain step 1, each different component is at its corresponding gain step setting 1, which corresponds to the highest gain and lowest attenuation available in the received signal path.

[0073] If a gain of 52 dB results in saturation, the receive AGC circuit 120 can reduce the gain by moving from gain step 1 to gain step 2. The receive AGC circuit 120 can implement gain step 2 by adjusting the gain step setting of the IFA for gain step setting 2. If a gain of 46 dB is still too high, the receive AGC circuit 120 can move from gain step 2 to gain step 3 by further adjusting the gain of the IFA downwards. It should be noted that other components, namely the mixer, adjustable capacitor attenuator, and LNTA, remain at their gain step setting 1.

[0074] In this particular example, the receiving AGC circuit 120 moves to the next downstream component (e.g., the mixer) only after the gain step setting of the downstream adjustable component (e.g., the IFA) has been exhausted. In this example, exhausting the gain step setting of a component can refer to reducing the gain of the component to the lowest available gain step setting or increasing the attenuation of the component to the highest available gain step setting.

[0075] After exhausting the gain step settings of the IFA, the receive AGC circuit 120 can then move to the mixer by switching the system to gain step 4. In this example, the mixer is the next upstream component of the IFA. In this example, the mixer also has three available gain step settings, which can be adjusted at gain steps 4 and 5. If the 29.5 dB gain at gain step 5 still results in saturation, the receive AGC circuit 120 can move to gain step 6 by adjusting the gain step setting of the adjustable capacitor attenuator circuit. In this example, the adjustable capacitor attenuator circuit is the next upstream component of the mixer.

[0076] In one example, the adjustable capacitor attenuator circuit 501 can provide three different gain step settings. The first gain step setting, corresponding to gain steps 1-5, can include no branch conduction. Figure 5 In this example, both transistors 510 and 520 will be off. A second gain step setting corresponding to gain step 6 may involve turning on a single branch, such as by turning on transistor 510 but keeping transistor 520 off. A third gain step setting corresponding to gain step 7 may involve turning on another branch, such as by turning on transistor 520 while transistor 510 remains on. In this example, the two branches provide three different gain step settings, corresponding to gain steps 5-7.

[0077] Once the gain settings of the adjustable capacitor attenuator circuitry have been exhausted, for example by increasing the attenuation to the maximum permissible level, the receive AGC circuitry 120 can move to the LNTA, which is the most upstream component in system 300. In this example, the receive AGC circuitry 120 can reduce the gain using five different gain step settings provided by the LNTA. The last gain step setting 11 corresponds to each component providing its minimum permissible gain (or maximum permissible attenuation) and provides a gain of -13.4 dB.

[0078] Of course, in various embodiments, the receiving AGC circuit 120 may not use all available gain steps. For example, the receiving AGC circuit 120 may determine that 23.5 dB of gain is the highest available gain without causing unwanted saturation or other unwanted distortion, and therefore, the receiving AGC circuit 120 may keep the system at gain step 6. However, the strength of the received signal may change due to factors such as device movement, changes in the air medium, etc., and the receiving AGC circuit 120 may appropriately switch from one gain step to another.

[0079] Figure 8 This is an illustration of an example method 800 for adjusting gain in a circuit according to some embodiments. In some instances, method 800 may be performed by a receive AGC circuit 120 to adjust the receiver and / or transceiver system (e.g., Figure 1-3 The gain in those shown. The functionality in method 800 can be implemented using hardware logic in the receiving AGC circuit 120. Alternatively or additionally, the functionality of method 800 can be implemented by the receiving AGC circuit 120, which includes a processor core that executes computer-readable instructions to cause the receiving AGC circuit 120 to perform the actions of method 800.

[0080] Action 802 includes operating the receive signal chain at the first gain level. An example receive signal chain is shown below. Figure 1 The diagram shows receive signal chains 105 and 108. An example receive signal chain is also shown. Figure 2-3 The diagram shows components including a mixer, amplifier, ADC, etc. In various embodiments, the signal chain components may have adjustable gain step settings that provide a gain step size, such as those described above. Figure 7 The first gain level of action 802, as discussed, can correspond to... Figure 7 Example gain step size.

[0081] Action 804 involves measuring the signal at the first gain level. (As mentioned above...) Figure 6The AGC receiving circuit 120 discussed here can measure the signal at the ADC. However, the scope of the implementation is not limited to measuring the signal only at the ADC, as the signal can be measured at any suitable point in the receiving signal chain. In some instances, the measured signal may include measured current level, voltage level, voltage swing, digital data indicating the amplitude associated with the signal, etc.

[0082] Action 806 includes adjusting the gain setting to achieve a second gain level. For example, the measured signal at action 804 may be higher than a pre-programmed or predefined threshold associated with saturation or other distortion. In response, the receiving AGC circuit 120 may be configured to reduce the gain step size of the received signal chain to achieve the second gain level. (The above refers to...) Figure 7 Example gain step sizes are discussed.

[0083] At action 808, the downstream gain reduction is exhausted. For example, the receiving AGC circuit 120 can be configured to reduce the gain by one step at a time, first on the downstream component, and then only move upstream to other components after the downstream gain reduction has been exhausted. Figure 3 In this example, this can be achieved by first decreasing the gain step setting at VGA 212, and only after the gain reduction at VGA 212 has been exhausted, starting to decrease the gain step setting at IFA 206, and then only after the gain reduction at IFA 206 has been exhausted, starting to decrease the gain step setting at mixer circuit 204. This can continue component-by-component from downstream to upstream, adjusting capacitor attenuator circuit 103 only after the gain reduction at mixer circuit 204 has been exhausted, and then moving to LNTA 310 to adjust its gain setting only after the gain reduction at adjustable capacitor attenuator circuit 103 has been exhausted.

[0084] Of course, this is just one example, and the scope of the implementation can be applied to different components, fewer components, additional components, or components described above. Figure 1-3 The components discussed are rearranged to receive the signal chain of the components.

[0085] At action 810, the receiving AGC circuit 120 can measure the signal again, as described above with respect to step 804.

[0086] At action 812, the receiving AGC circuit 120 can readjust the gain setting by adjusting the attenuator capacitance to achieve a third gain level. For example, once it is appropriate to begin reducing the gain at the adjustable capacitor attenuator circuit (e.g., circuit 103), the receiving AGC circuit 120 can use a control signal to increase the attenuation at the adjustable capacitor attenuator circuit. (As mentioned above...) Figure 5As described, increasing attenuation may involve turning on additional transistors (e.g., using digital control signals) or adjusting the operation in the linear operating region (e.g., using analog control signals).

[0087] The above is about Figure 7 Gain step sizes 6 and 7 further discuss examples of adjusting the gain setting by adjusting the attenuator capacitance.

[0088] Action 814 includes measuring the signal at the third gain level, which can be performed in the same or similar manner as the measurement described above with respect to action 804.

[0089] Although not in Figure 8 As shown, however, method 800 may include additional steps, such as performing further adjustments after the measurement of action 814. Additionally, method 800 may further include adjusting the gain based on the measured signal. For example, as signal conditions change, the receiving AGC circuit 120 may determine that the signal level is below a pre-programmed or predefined threshold and may be configured to increase the gain in response. In one example, the receiving AGC circuit 120 may then first increase the gain from the downstream component and move upstream component by component as appropriate.

[0090] Furthermore, while the above discussion relates to method 800 with respect to a single receive signal chain, the scope of the implementation may include adjusting the gain in at least one additional receive signal chain. For example, the receive AGC circuit 120 may be configured to, for example... Figure 1-3 In the example system shown, the same gain adjustment is performed on both the I and Q signal paths each time.

[0091] Exemplary embodiments of this disclosure are summarized herein. Other embodiments can also be understood from the entire specification and technical solutions submitted herein.

[0092] Example 1. An electronic circuit includes: a first signal path comprising: a first current-mode mixer having first and second inputs and first and second outputs; a first amplifier circuit having first and second inputs respectively coupled to the first and second outputs of the first current-mode mixer; and a first adjustable capacitor attenuator circuit having first and second outputs respectively coupled to the first and second inputs of the first current-mode mixer; and a second signal path comprising: a second current-mode mixer having first and second inputs and first and second outputs; a second amplifier circuit having first and second inputs respectively coupled to the first and second outputs of the second current-mode mixer; and a second adjustable capacitor attenuator circuit having first and second outputs respectively coupled to the first and second inputs of the second current-mode mixer.

[0093] Example 2. The electronic circuit according to Example 1 further includes a phase-locked loop (PLL) having an output coupled to a clock input of a first current-mode mixer and a clock input of a second current-mode mixer.

[0094] Example 3. An electronic circuit according to one of Examples 1 or 2, further comprising a 90-degree phase shift circuit coupled between the output of the PLL and a second current-mode mixer.

[0095] Example 4. An electronic circuit according to any one of Examples 1 to 3, wherein a first amplifier circuit includes a first filter coupled to a first variable gain amplifier, and wherein a second amplifier circuit includes a second filter coupled to a second variable gain amplifier.

[0096] Example 5. An electronic circuit according to any one of Examples 1 to 4, wherein a first signal path includes a first analog-to-digital converter (ADC) having an input coupled to a first output of a first current-mode mixer, and wherein a second signal path includes a second ADC having an input coupled to a first output of a second current-mode mixer.

[0097] Example 6. An electronic circuit according to any one of Examples 1 to 5, further comprising an input amplifier circuit including a differential output having first and second outputs respectively coupled to first and second inputs of a first adjustable capacitor attenuator circuit.

[0098] Example 7. An electronic circuit according to any one of Examples 1 to 6, wherein the input amplifier circuit includes a low-noise amplifier (LNA).

[0099] Example 8. An electronic circuit according to any one of Examples 1 to 7, wherein the input amplifier circuit includes a transconductance amplifier (TA) having first and second inputs respectively coupled to first and second outputs of a first and second LNA, and first and second outputs respectively coupled to first and second inputs of a first adjustable capacitor attenuator circuit.

[0100] Example 9. An electronic circuit according to any one of Examples 1 to 8, further comprising an oscillating loop filter (tank filter) coupled to the output of the LNA.

[0101] Example 10. An electronic circuit according to any one of Examples 1 to 9, wherein the input amplifier circuit includes a low-noise transconductance amplifier (LNTA) having first and second outputs respectively coupled to first and second inputs of a first adjustable capacitor attenuator circuit.

[0102] Example 11. An electronic circuit according to any one of Examples 1 to 10, further comprising an antenna coupled to the input of an input amplifier circuit.

[0103] Example 12. An electronic circuit according to any one of Examples 1 to 11, wherein the first capacitor attenuator circuit comprises: a first branch having a first capacitor and a first transistor coupled between the first and second inputs of the first adjustable capacitor attenuator circuit; and a second branch having a second capacitor and a second transistor coupled between the first and second inputs of the first adjustable capacitor attenuator circuit.

[0104] Example 13. An electronic circuit according to one of Examples 1 to 12, further comprising a gain control circuit coupled to the first and second transistors.

[0105] Example 14. An electronic circuit according to any one of Examples 1 to 13, wherein the gain control circuit is configured to control the on and off states of the first and second transistors by applying a digital 1 or a digital 0 to the control terminals of the first and second transistors.

[0106] Example 15. An electronic circuit according to any one of Examples 1 to 14, wherein the gain control circuit is configured to control the first transistor and the second transistor within a linear operating region by applying an analog signal to the control terminals of the first transistor and the second transistor.

[0107] Example 16. An electronic circuit according to any one of Examples 1 to 15, wherein a first signal path includes an in-phase signal path, and wherein a second signal path includes a quadrature signal path.

[0108] Example 17. An electronic circuit according to any one of Examples 1 to 16, wherein the first adjustable capacitor attenuator circuit comprises: a first capacitor coupled between a first output of the first adjustable capacitor attenuator and a first input of a first current-mode mixer; and a second capacitor coupled between a second output of the first adjustable capacitor attenuator and a second input of the first current-mode mixer.

[0109] Example 18. An electronic circuit according to any one of Examples 1 to 17, wherein the second adjustable capacitor attenuator circuit comprises: a third capacitor coupled between a first output of the second adjustable capacitor attenuator and a first input of the second current-mode mixer; and a fourth capacitor coupled between a second output of the second adjustable capacitor attenuator and a second input of the second current-mode mixer.

[0110] Example 19. An electronic circuit according to any one of Examples 1 to 18, wherein a first signal path includes a first analog-to-digital converter having an input coupled to the output of a first amplifier circuit, and wherein a second signal path includes a second analog-to-digital converter having an input coupled to the output of a second amplifier circuit.

[0111] Example 20. An electronic circuit according to any one of Examples 1 to 19, further comprising: a multiplexer having a first input coupled to an output of a first signal path, a second input coupled to an output of a second signal path, and an output; and an analog-to-digital converter having an input coupled to the output of the multiplexer.

[0112] Example 21. An electronic circuit according to any one of Examples 1 to 20, further comprising: an analog-to-digital converter (ADC) having an input coupled to a first signal path; and a gain control circuit configured to: measure a signal at the input of the ADC or at the output of the ADC; and adjust the capacitance of a first adjustable capacitor attenuator circuit based on the measured signal.

[0113] Example 22. An electronic circuit according to any one of Examples 1 to 21, wherein, in order to adjust the capacitance of a first adjustable capacitor attenuator, a gain control circuit is configured to provide a first control signal to the first adjustable capacitor attenuator, wherein the gain control circuit is further configured to provide a first control signal to a second adjustable capacitor attenuator.

[0114] Example 23. An electronic circuit according to any one of Examples 1 to 22, wherein the gain control circuit is configured to reduce the gain of the first adjustable capacitor attenuator circuit after the gain of the first amplifier circuit has been reduced to a predetermined minimum gain.

[0115] Example 24. An electronic circuit according to any one of Examples 1 to 23, further comprising a low-noise transimpedance amplifier (LNTA) having an input configured to receive a signal from an antenna, and an output coupled to an input to a first signal path and coupled to an input to a second signal path.

[0116] Example 25. An electronic circuit according to any one of Examples 1 to 24, wherein the output of the LNTA is a differential output, wherein a first signal path includes a first pair of coupling capacitors coupled to the differential output of the LNTA and coupled to a first adjustable capacitor attenuator circuit, and wherein a first amplifier circuit includes: a first intermediate frequency amplifier having first and second inputs coupled to first and second outputs of a first current-mode mixer; a first variable gain amplifier having an input coupled to the output of the first intermediate frequency amplifier; and an analog-to-digital converter (ADC) having an input coupled to the output of the first variable gain amplifier.

[0117] Example 26. An electronic circuit according to any one of Examples 1 to 25, wherein the second signal path includes a second pair of coupling capacitors coupled to the differential output of the LNTA and coupled to a second adjustable capacitor attenuator circuit, and wherein the second amplifier circuit includes: a second intermediate frequency amplifier having first and second inputs coupled to first and second outputs of a second current-mode mixer; and a second variable gain amplifier coupled to the output of the second intermediate frequency amplifier.

[0118] Example 27. An electronic circuit according to any one of Examples 1 to 26, further comprising: a gain control circuit configured to measure the voltage swing at the input or output of the ADC, and to reduce the gain setting of the LTNA after the gain of the first adjustable attenuator circuit reaches a minimum gain.

[0119] Example 28. An electronic circuit according to any one of Examples 1 to 27, wherein the electronic circuit does not include an oscillating loop filter coupled to the input of the first signal path.

[0120] Example 29. An electronic circuit comprising: an antenna terminal; a low-noise transimpedance amplifier (LNTA) having an input coupled to the antenna terminal and first and second outputs; a current-mode mixer having first and second inputs; and an adjustable capacitor attenuator having a first terminal coupled to the first output of the LNTA and coupled to the first input of the current-mode mixer, and a second terminal coupled to the second output of the LNTA and coupled to the second input of the current-mode mixer.

[0121] Example 30. The electronic circuit according to Example 29, wherein the adjustable capacitor attenuator includes first and second capacitors coupled between first and second terminals of the adjustable capacitor attenuator, and a first transistor having a current path coupled between the first and second capacitors.

[0122] Example 31. An electronic circuit according to one of Examples 29 or 30, further comprising a gain control circuit having a first output coupled to a control terminal of a first transistor.

[0123] Example 32. An electronic circuit according to one of Examples 29 to 31, wherein a gain control circuit is configured to provide a control signal at a first output of the gain control circuit to operate a first transistor in the linear region.

[0124] Example 33. An electronic circuit according to one of Examples 29 to 32, wherein the gain control circuit is configured to provide a digital control signal at a first output of the gain control circuit.

[0125] Example 34. An electronic circuit according to one of Examples 29 to 33, wherein the adjustable capacitor attenuator further includes a second transistor coupled between the first and second terminals of the adjustable capacitor attenuator, and wherein the gain control circuit includes a second output coupled to a control terminal of the second transistor.

[0126] Example 35. An electronic circuit according to one of Examples 29 to 34, wherein the electronic circuit is implemented as an integrated circuit separate from the amplifier circuit.

[0127] Example 36. An electronic circuit according to one of Examples 29 to 35, wherein an adjustable capacitor attenuator and a mixer are implemented in an in-phase signal path, wherein the electronic circuit further includes a quadrature signal path.

[0128] Example 37. A method comprising: operating a receive signal chain at a first gain level, wherein the receive signal chain includes a capacitor attenuator having first and second terminals respectively coupled to first and second inputs of a current-mode mixer; adjusting a gain setting of the receive signal chain to a second gain level, wherein the second gain level is lower than the first gain level, without adjusting the capacitance of the capacitor attenuator; measuring a signal at the second gain level; and, in response to the measured signal, adjusting the gain setting to a third gain level lower than the second gain level, comprising adjusting the capacitance of the capacitor attenuator to achieve the third gain level, wherein the third gain level is lower than the second gain level.

[0129] Example 38. The method according to Example 37, wherein the measurement signal includes a measurement voltage, and wherein adjusting the capacitance of the capacitor attenuator to achieve a third gain level includes adjusting the capacitance of the capacitor attenuator in response to the voltage being higher than a predetermined voltage.

[0130] Example 39. According to one of Examples 37 or 38, adjusting the gain setting to a third gain level includes adjusting the gain setting to a third gain level in response to the measured signal being higher than a predetermined threshold.

[0131] Example 40. A method according to one of Examples 37 to 39, wherein the capacitor attenuator comprises: a first capacitor and a first transistor coupled between first and second terminals of the capacitor attenuator; and a second capacitor and a second transistor coupled between the first and second terminals of the capacitor attenuator, wherein adjusting the capacitance of the capacitor attenuator comprises changing the state of the first transistor from off to on to create a current path through the first capacitor.

[0132] Example 41. The method according to one of Examples 37 to 40, wherein the third gain level corresponds to the first transistor being turned on and the second transistor being turned off.

[0133] Example 42. The method according to one of Examples 37 to 41, further comprising: measuring a signal at a third gain level; and, in response to measuring the signal at the third gain level, adjusting the gain setting to a fourth gain level lower than the third gain level, including further adjusting the capacitance of a capacitor attenuator to achieve the fourth gain level.

[0134] Example 43. The method according to one of Examples 37 to 42, wherein the fourth gain level corresponds to the first transistor being turned on and the second transistor being turned on.

[0135] Example 44. The method according to one of Examples 37 to 43, wherein the second gain level corresponds to the first transistor being off and the second transistor being off.

[0136] Example 45. The method according to any one of Examples 37 to 44, wherein the third gain level is reduced by 6 dB relative to the second gain level, and wherein the fourth gain level is reduced by 6 dB relative to the third gain level.

[0137] Example 46. A method according to one of Examples 37 to 45, wherein adjusting the gain setting of the receive signal chain to a second gain level comprises: reducing the gain of the variable gain amplifier of the receive signal chain.

[0138] Example 47. A method according to one of Examples 37 to 46, wherein adjusting the gain setting of the receive signal chain to a second gain level comprises: reducing the gain of the intermediate frequency amplifier of the receive signal chain.

[0139] Example 48. A method according to one of Examples 37 to 47, wherein adjusting the gain setting of the receive signal chain to a second gain level comprises: reducing the gain of the mixer in the receive signal chain.

[0140] Example 49. The method according to one of Examples 37 to 48, wherein adjusting the gain setting of the receive signal chain to a second gain level comprises: reducing the gain of the means of the receive signal chain downstream of the depletion capacitor attenuator.

[0141] Example 50. A method according to one of Examples 37 to 49, wherein adjusting the capacitance of the capacitor attenuator to achieve the third gain level is performed only after the gain of the device in the downstream of the capacitor attenuator has decreased.

[0142] Example 51. A method according to one of Examples 37 to 50, wherein adjusting the capacitance of the capacitor attenuator to achieve the third gain level is performed only after the gain of the received signal chain is reduced to the minimum gain setting of the means of receiving signal chain downstream of the attenuator.

[0143] Example 52. A method according to one of Examples 37 to 51, wherein adjusting the capacitance of the capacitor attenuator to achieve the third gain level includes increasing the capacitance of the capacitor attenuator.

[0144] Example 53. The method according to one of Examples 37 to 52, wherein the method is performed by the automatic gain control circuitry of the transceiver.

[0145] Example 54. A method according to one of Examples 37 to 53, wherein adjusting the gain setting to a third gain level involves reducing the amount of current in the signal.

[0146] Example 55. The method according to one of Examples 37 to 54, wherein the capacitor attenuator includes a capacitor and a transistor coupled between first and second terminals of the capacitor attenuator, wherein adjusting the capacitance of the capacitor attenuator includes adjusting the operation of the transistor within the linear range of the transistor.

[0147] While various examples of this disclosure have been described above, it should be understood that these examples are presented by way of illustration only and not as a limitation. Many changes may be made to the disclosed examples based on the disclosure herein without departing from the spirit or scope of this disclosure. Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible. Therefore, the breadth and scope of the invention should not be limited to any of the examples described above. In fact, the scope of this disclosure should be defined according to the appended claims and their equivalents.

Claims

1. An electronic circuit comprising: The first signal path includes: A first current-mode mixer having first and second inputs and first and second outputs; A first amplifier circuit having first and second inputs respectively coupled to the first and second outputs of the first current-mode mixer; and A first adjustable capacitor attenuator circuit has first and second outputs respectively coupled to the first and second inputs of the first current-mode mixer; and The second signal path includes: A second current-mode mixer having first and second inputs and first and second outputs; A second amplifier circuit having first and second inputs respectively coupled to the first and second outputs of the second current-mode mixer; and The second adjustable capacitor attenuator circuit has first and second outputs respectively coupled to the first and second inputs of the second current-mode mixer.

2. The electronic circuit according to claim 1, further comprising: A phase-locked loop (PLL) having an output coupled to a clock input of the first current-mode mixer and a clock input of the second current-mode mixer; as well as A 90-degree phase shift circuit is coupled between the output of the PLL and the second current-mode mixer.

3. The electronic circuit of claim 1, wherein the first amplifier circuit includes a first filter coupled to a first variable gain amplifier, and wherein the second amplifier circuit includes a second filter coupled to a second variable gain amplifier.

4. The electronic circuit of claim 1, wherein the first signal path includes a first analog-to-digital converter (ADC) having an input coupled to a first output of the first current-mode mixer, and wherein the second signal path includes a second ADC having an input coupled to the first output of the second current-mode mixer.

5. The electronic circuit of claim 1, further comprising an input amplifier circuit including a differential output having first and second outputs respectively coupled to the first and second inputs of the first adjustable capacitor attenuator circuit.

6. The electronic circuit according to claim 5, wherein the input amplifier circuit comprises a low-noise amplifier (LNA).

7. The electronic circuit of claim 6, wherein the input amplifier circuit comprises a transconductance amplifier TA having first and second inputs respectively coupled to first and second outputs of the LNA, and first and second outputs respectively coupled to the first and second inputs of the first adjustable capacitor attenuator circuit; and The electronic circuitry further includes an oscillating loop filter coupled to the output of the LNA.

8. The electronic circuit of claim 5, further comprising an antenna coupled to an input of the input amplifier circuit.

9. The electronic circuit according to claim 5, wherein the first capacitor attenuator circuit comprises: The first branch has a first capacitor and a first transistor coupled between the first and second inputs of the first adjustable capacitor attenuator circuit; as well as The second branch has a second capacitor and a second transistor coupled between the first and second inputs of the first adjustable capacitor attenuator circuit.

10. The electronic circuit of claim 1, further comprising a gain control circuit coupled to the first and second transistors, wherein the gain control circuit is configured to control the on and off states of the first and second transistors by applying a digital 1 or a digital 0 to control terminals of the first and second transistors.

11. The electronic circuit of claim 10, wherein the gain control circuit is configured to control the first transistor and the second transistor within a linear operating region by applying analog signals to the control terminals of the first transistor and the second transistor.

12. The electronic circuit of claim 1, wherein the first signal path comprises an in-phase signal path, and wherein the second signal path comprises a quadrature signal path.

13. The electronic circuit according to claim 1, wherein the first adjustable capacitor attenuator circuit comprises: A first capacitor is coupled between the first output of the first adjustable capacitor attenuator and the first input of the first current-mode mixer. as well as A second capacitor is coupled between the second output of the first adjustable capacitor attenuator and the second input of the first current-mode mixer.

14. The electronic circuit of claim 13, wherein the second adjustable capacitor attenuator circuit comprises: A third capacitor is coupled between the first output of the second adjustable capacitor attenuator and the first input of the second current-mode mixer; as well as A fourth capacitor is coupled between the second output of the second adjustable capacitor attenuator and the second input of the second current-mode mixer.

15. The electronic circuit of claim 1, wherein the first signal path includes a first analog-to-digital converter having an input coupled to the output of the first amplifier circuit, and wherein the second signal path includes a second analog-to-digital converter having an input coupled to the output of the second amplifier circuit.

16. The electronic circuit according to claim 1, further comprising: A multiplexer having a first input coupled to the output of the first signal path, a second input coupled to the output of the second signal path, and an output; as well as An analog-to-digital converter having an input coupled to the output of the multiplexer.

17. The electronic circuit according to claim 1, further comprising: An analog-to-digital converter (ADC) having an input coupled to the first signal path; as well as The gain control circuit is configured to: Measure the signal at the input of the ADC or the output of the ADC; as well as Adjust the capacitance of the first adjustable capacitor attenuator circuit based on the measured signal.

18. The electronic circuit according to claim 17, wherein, In order to adjust the capacitance of the first adjustable capacitor attenuator, the gain control circuit is configured to provide a first control signal to the first adjustable capacitor attenuator, wherein the gain control circuit is further configured to provide the first control signal to the second adjustable capacitor attenuator.

19. The electronic circuit of claim 17, wherein the gain control circuit is configured to reduce the gain of the first adjustable capacitor attenuator circuit after reducing the gain of the first amplifier circuit to a predetermined minimum gain.

20. The electronic circuit of claim 1, further comprising a low-noise transimpedance amplifier (LNTA) having an input configured to receive a signal from an antenna, and an output coupled to an input of the first signal path and an input of the second signal path, wherein the output of the LNTA is a differential output, wherein the first signal path includes a first pair of coupling capacitors coupled to the differential output of the LNTA and coupled to the first adjustable capacitor attenuator circuit, and further wherein the first amplifier circuit includes: A first intermediate frequency amplifier having first and second inputs coupled to the first and second outputs of the first current-mode mixer; A first variable gain amplifier has an input coupled to the output of the first intermediate frequency amplifier; as well as An analog-to-digital converter (ADC) having an input coupled to the output of the first variable gain amplifier.

21. The electronic circuit of claim 20, wherein the second signal path includes a second pair of coupling capacitors, the second pair of coupling capacitors being coupled to the differential output of the LNTA and coupled to the second adjustable capacitor attenuator circuit, and wherein the second amplifier circuit includes: A second intermediate frequency amplifier having first and second inputs coupled to the first and second outputs of the second current-mode mixer; as well as A second variable gain amplifier is coupled to the output of the second intermediate frequency amplifier.

22. The electronic circuit of claim 1, wherein the electronic circuit does not include an oscillating loop filter coupled to the input of the first signal path.

Images