A medium-high voltage printed circuit board and a method for reinforcing insulation thereof

Abstract

The application provides a kind of medium-high voltage printed circuit board and its insulation strengthening method, it is related to printed circuit board insulation design technical field, the method is based on the initial structure data between positive direct current terminal pad and negative direct current terminal pad, obtains first insulation strengthening data;Based on the initial structure data between direct current pad and system midpoint potential conductor, obtains second insulation strengthening data;Based on the initial structure data at the capacitor terminal pad, obtains third insulation strengthening data;Based on the initial structure data of hole array area, the method of adding the shielding layer extending radially outside under the hole array area is used to obtain fourth insulation strengthening data;Based on first insulation strengthening data, second insulation strengthening data, third insulation strengthening data and fourth insulation strengthening data, the method of adding the outermost layer of insulation material to printed circuit board is used to obtain insulation strengthening result.The application solves the problems of high cost and poor insulation performance of the existing printed circuit board design method.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board insulation design technology, and in particular to a medium- and high-voltage printed circuit board and its insulation strengthening method. Background Technology

[0002] In power converters, the busbar serves as the mechanical and electrical interface for other components. Traditional multilayer busbars have thick copper layers and high current-carrying capacity. They are constructed by laminating vertically stacked copper plates and insulating materials together. These structures are prone to internal porosity defects during adhesive manufacturing and curing, such as pores on the conductor edges and in the adhesive layer. These problems are not prominent in low-voltage applications, but become severe in high-voltage applications with 10kV SiC devices. Partial discharge can occur in these pores, which ages the insulating material and shortens its lifespan. Furthermore, compared to Si-based devices, high-voltage SiC devices have much higher switching speeds, reaching tens of kHz, which means higher dv / dt, placing greater stress on the busbar insulation material. Multilayer busbars require thicker insulation layers to meet insulation requirements; however, excessive insulation thickness is detrimental to eliminating parasitic inductance.

[0003] Although the copper layer of a printed circuit board (PCB) busbar is thin and its current-carrying capacity is relatively small, its current-carrying capacity can be increased by increasing the number of copper layers, increasing the copper thickness, and adding vias. Furthermore, PCBs offer advantages such as high integration, flexible layout, good high-frequency impedance characteristics, better magnetic cancellation effect, and excellent insulation performance. Manufacturers use mature automated manufacturing lines, vacuum lamination, and hot pressing processes to obtain PCBs free of internal defects, forming a high-current, high-insulation, high-frequency power transmission circuit with extremely low busbar impedance.

[0004] Converters based on 10kV SiC devices will see a significant increase in power density. However, using low-voltage printed circuit board designs within small spaces will pose a significant insulation risk. Summary of the Invention

[0005] In view of the above-mentioned shortcomings in the prior art, the present invention provides a medium and high voltage printed circuit board and its insulation strengthening method, which solves the problems of high cost and poor insulation performance of the existing printed circuit board design methods.

[0006] To achieve the aforementioned objectives, the present invention employs the following technical solution: a method for strengthening the insulation of medium- and high-voltage printed circuit boards, comprising: S1: Based on the initial structural data between the positive DC terminal pad and the negative DC terminal pad, the first insulation reinforcement data is obtained by optimizing the spacing of the air groove width and the distance of the DC conductor from the point potential conductor in the system and adding the first shielding disk. S2: Based on the initial structural data between the DC pad and the point potential conductor in the system, the second insulation reinforcement data is obtained by reducing the extension structure of the DC pad on each printed circuit board layer and adding a second shielding pad. S3: Based on the initial structural data at the capacitor terminal pads, the third insulation reinforcement data is obtained by changing the horizontal offset distance between the point potential conductor and the midpoint potential conductor in the system and the horizontal spacing between the outer layer and the inner layer DC conductor. S4: Based on the initial structural data of the aperture array region, the fourth insulation enhancement data is obtained by adding a shielding layer extending outward in a circumferential direction below the aperture array region. S5: Based on the first insulation reinforcement data, the second insulation reinforcement data, the third insulation reinforcement data, and the fourth insulation reinforcement data, the insulation reinforcement result is obtained by adding the outermost layer of insulating material to the printed circuit board, thus completing the insulation reinforcement of the medium and high voltage printed circuit board.

[0007] Further, S1 includes: Based on the initial structural data between the positive DC terminal pad and the negative DC terminal pad, the first insulation reinforcement data is obtained by setting the optimization range of the air groove width as a first setting range and the optimization range of the distance between the DC conductor and the point potential conductor in the system as a second setting range, and arranging a larger-sized conductor of the same shape as a first shielding pad below the surface pad; wherein, the first setting range is one to four millimeters, and the second setting range is nine to thirteen millimeters.

[0008] Further, S2 includes: Based on the initial structural data between the DC pad and the point potential conductor in the system, the second insulation reinforcement data is obtained by subtracting the copper conductor of the middle layer of the DC pad and filling it with insulating material, while adding a second shielding disk.

[0009] Further, S3 includes: Based on the initial structural data at the capacitor terminal pads, a third insulation reinforcement data is obtained by setting the horizontal offset distance between the point potential conductor and the midpoint potential conductor in the system as a third setting range, and setting the horizontal spacing between the outer layer and the inner layer DC conductor as a fourth setting range; wherein the third setting range is 0.5 to 5 mm, and the fourth setting range is 0.5 to 2.5 mm.

[0010] Further, S4 includes: Based on the initial structural data of the aperture array region, the fourth insulation enhancement data was obtained by adding a shielding layer extending outward by one to two millimeters in the circumferential direction below the aperture array region.

[0011] The present invention provides a medium-voltage printed circuit board, comprising: a first shielding disk, a DC pad, a system midpoint potential conductor, a second shielding disk, a system midpoint potential conductor, a midpoint potential conductor, an outer DC conductor, an inner DC conductor, a via array region, and a shielding layer; The first shielding disk is arranged below the surface pads of the printed circuit board; The DC pad has the extension structure of the intermediate conductor layer removed, and a second shielding disk is arranged between the DC pad and the point potential conductor in the system; The system's point potential conductor, midpoint potential conductor, outer DC conductor, and inner DC conductor are respectively arranged in different potential conductor layers inside the printed circuit board; a horizontal offset distance is provided between the system's point potential conductor and the midpoint potential conductor; a horizontal spacing is provided between the outer DC conductor and the inner DC conductor; The shielding layer is disposed below the aperture array region and extends outward in the circumferential direction.

[0012] Furthermore, the printed circuit board also includes: a positive DC terminal pad, a negative DC terminal pad, and a DC conductor; An air groove is provided between the positive DC terminal pad and the negative DC terminal pad, and the air groove has a groove width; A distance is provided between the DC conductor and the point potential conductor in the system.

[0013] Furthermore, the printed circuit board has a ten-layer structure, including a first layer to a tenth layer stacked sequentially from the outside to the inside, and an insulating thickness is provided between adjacent layers; The first layer only has the surface pads and vias; The second layer and the ninth layer are the same shielding layer, and the first shielding disk, the second shielding disk and the shielding layer are arranged in the second layer and the ninth layer; The third layer and the eighth layer are the same system point potential conductor layers. The system point potential conductor and the system point potential conductor are arranged in the third layer and the eighth layer and are connected by potential through through holes. The fourth to the seventh layers contain the same DC conductor and midpoint potential conductor. Conductors with the same potential are connected by through holes, and conductors with different potentials are kept at an insulating distance. The midpoint potential conductor, the outer DC conductor, and the inner DC conductor are arranged in the fourth to the seventh layers. The third to eighth layers and the tenth layer contain the same AC terminal conductors, and the AC terminal conductors in each layer are electrically connected through through holes.

[0014] Furthermore, the extension structure of the intermediate conductor layer removed from the DC pad specifically involves removing the copper conductor of the DC pad in the third layer and filling the corresponding space of the third layer with insulating material; The second shielding disk is arranged in the second layer, such that the electric field interaction between the point potential conductor in the system and the surface pad is transferred to the second shielding disk.

[0015] Furthermore, the point potential conductor and the midpoint potential conductor in the system are horizontally offset to form the horizontal offset distance; The shielding layer is distributed directly below the aperture array region, and the edge of the shielding layer extends beyond the outer edge of the aperture array region, forming a circumferential outward extension.

[0016] The beneficial effects of the present invention are as follows: The present invention provides an insulation strengthening method for medium and high voltage printed circuit boards. (1) Based on the initial structural data between the positive DC terminal pad and the negative DC terminal pad, the method of optimizing the spacing of the air groove width and the distance between the DC conductor and the point potential conductor in the system and adding a first shielding disk is used to effectively increase the outermost insulation thickness. This technical feature transfers the point potential conductor in the system to the inner layer of the printed circuit board and transfers the electric field peaks in the air to the inside of the busbar, thus alleviating the problem of excessive electric field in this area. (2) Based on the initial structural data between the DC pad and the point potential conductor in the system, the method of reducing the extension structure of the DC pad in each printed circuit board layer and adding a second shielding disk is used to solve the problem of excessive electric field in the air and electric field peaks at the edge of the pad. This technical feature reduces the number of electric field peaks and guides the electric field interaction between the point potential conductor in the system and the surface pad to the shielding disk, further introducing the electric field peaks into the inside of the printed circuit board and reducing the risk of discharge. (3) Based on the initial structural data at the capacitor terminal pads, the vertical structural misalignment at the point potential conductor and the midpoint potential conductor in the system, as well as the horizontal spacing between the outer and inner DC conductors, was achieved by changing the horizontal offset distance between them. This feature separates the peak electric fields within the printed circuit board without affecting the current carrying capacity, reduces the accumulation of peak field strength, lowers the overall electric field strength, and achieves precise control of the electric field inside the printed circuit board. (4) Based on the initial structural data of the via array region, the electric field was optimized for the region with increased exposed metal area by adding a circumferentially outward-extending shielding layer below the via array region. This feature introduces the field strength peaks in this region from the air into the interior of the printed circuit board, reducing the risk of partial discharge (PD). (5) Based on the first to fourth insulation enhancement data, the outermost conductor was transferred to the interior of the printed circuit board by adding an outermost layer of insulation material. By combining the above multi-region electric field weakening designs, a significant optimization of insulation performance was achieved, resulting in an increase of 15% to 25% in the average partial discharge initiation voltage (PDIV) of each interface. Attached Figure Description

[0017] This specification will be further described by way of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting; in these embodiments, the same reference numerals denote the same structures, wherein: Figure 1 This is an exemplary schematic diagram of the DC terminal pads and electric field distribution according to some embodiments of this specification; Figure 2 This is an exemplary flowchart of an insulation strengthening method for a medium- or high-voltage printed circuit board according to some embodiments of this specification; Figure 3 This is an exemplary schematic diagram showing the relationship between the maximum electric field strength in the air at the DC terminal and L1 and L2, according to some embodiments of this specification. Figure 4 This is an exemplary schematic diagram showing the introduction of a shielding disk and its electric field distribution at a DC terminal pad according to some embodiments of this specification; Figure 5 This is an exemplary schematic diagram showing the electric field distribution at the DC terminal pad and N conductor, according to some embodiments of this specification; Figure 6 This is an exemplary schematic diagram showing the optimized electric field distribution at the insulation between the DC terminal pad and the N conductor, according to some embodiments of this specification; Figure 7 This is an exemplary schematic diagram of the capacitor terminal pads and their electric field optimization according to some embodiments of this specification; Figure 8 This is an exemplary schematic diagram of the aperture array region and its electric field distribution according to some embodiments of this specification; Figure 9 These are exemplary schematic diagrams illustrating partial discharge tests and their results according to some embodiments of this specification; Figure 10 This is an exemplary structural diagram of a medium-voltage printed circuit board according to some embodiments of this specification.

[0018] Wherein: 1. First shielding disk; 2. DC pad; 3. System midpoint potential conductor; 4. Extension structure of intermediate conductor layer; 5. Second shielding disk; 6. System midpoint potential conductor; 7. Midpoint potential conductor; 8. Outer DC conductor; 9. Inner DC conductor; 10. Hole array area; 11. Shielding layer. Detailed Implementation

[0019] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0020] Example 1 Figure 10 This is an exemplary structural diagram of a medium-voltage printed circuit board according to some embodiments of this specification.

[0021] In some embodiments, such as Figure 10As shown, the medium-voltage printed circuit board may include a first shielding disk 1, a DC pad 2, a system midpoint potential conductor 3, a second shielding disk 5, a system midpoint potential conductor 6, a midpoint potential conductor 7, an outer DC conductor 8, an inner DC conductor 9, a via array region 10, and a shielding layer 11; wherein, the first shielding disk 1 is arranged below the surface pads of the printed circuit board; the DC pad 2 has the extension structure 4 of the intermediate conductor layer removed, and the second shielding disk 5 is arranged between the DC pad 2 and the system midpoint potential conductor 3; the system midpoint potential conductor 3, the system midpoint potential conductor 6, the midpoint potential conductor 7, the outer DC conductor 8, and the inner DC conductor 9 are respectively arranged in different potential conductor layers inside the printed circuit board; a horizontal offset distance is provided between the system midpoint potential conductor 6 and the midpoint potential conductor 7; a horizontal spacing is provided between the outer DC conductor 8 and the inner DC conductor 9; the shielding layer 11 is arranged below the via array region 10, and the circumferential radius of the shielding layer 11 extends outward.

[0022] In some embodiments, the printed circuit board further includes: a positive DC terminal pad, a negative DC terminal pad, and a DC conductor; an air groove is provided between the positive DC terminal pad and the negative DC terminal pad, the air groove having a preset groove width, for example, the preset groove width can be 1.5mm or 2mm; a preset distance is provided between the DC conductor and the point potential conductor 3 in the system, for example, the preset distance can be 6mm or 7mm.

[0023] In some embodiments, the printed circuit board has a ten-layer structure, including a first layer to a tenth layer stacked sequentially from the outside to the inside, with an insulating thickness between adjacent layers; the first layer only has surface pads and vias; the second layer and the ninth layer are the same shielding layer, with the first shielding pad 1, the second shielding pad 5, and the shielding layer 11 arranged in the second layer and the ninth layer; the third layer and the eighth layer are the same system point potential conductor layers, with the system point potential conductor 3 and the system point potential conductor 6 arranged in the third layer and connected by potential through vias; the fourth layer to the seventh layer contain the same DC conductor and midpoint potential conductor, with conductors of the same potential connected by potential through vias, and conductors of different potentials maintaining an insulating distance, with the midpoint potential conductor 7, the outer layer DC conductor 8, and the inner layer DC conductor 9 arranged in the fourth layer to the seventh layer; the third layer to the eighth layer and the tenth layer contain the same AC terminal conductor, with the AC terminal conductors in each layer connected by potential through vias.

[0024] In some embodiments, the extension structure 4 of the intermediate conductor layer removed from the DC pad 2 specifically involves removing the copper conductor of the DC pad 2 in the third layer and filling the corresponding space of the third layer with insulating material; the second shielding disk 5 is arranged in the second layer such that the electric field interaction between the point potential conductor 3 in the system and the surface pad is transferred to the second shielding disk 5.

[0025] In some embodiments, the point potential conductor 6 and the midpoint potential conductor 7 in the system are staggered in the horizontal direction to form the horizontal offset distance; the shielding layer 11 is distributed directly below the aperture array region 10, and the edge of the shielding layer 11 extends beyond the outer edge of the aperture array region 10 to form the circumferential outward extension.

[0026] In some embodiments, a medium- and high-voltage printed circuit board can be used to perform an insulation strengthening method for a medium- and high-voltage printed circuit board, comprising: S1: obtaining first insulation strengthening data based on initial structural data between positive DC terminal pads and negative DC terminal pads by optimizing the spacing of air slots and the distance of DC conductors from point potential conductors in the system and adding a first shielding pad; S2: obtaining second insulation strengthening data based on initial structural data between DC pads and point potential conductors in the system by reducing the extension structure of DC pads on each printed circuit board layer and adding a second shielding pad; S3: based on capacitor terminals... S4: Based on the initial structural data at the pads, the third insulation reinforcement data is obtained by changing the horizontal offset distance between the point potential conductor and the midpoint potential conductor in the system, as well as the horizontal spacing between the outer and inner DC conductors; S5: Based on the initial structural data of the via array region, the fourth insulation reinforcement data is obtained by adding a circumferentially outward-extending shielding layer below the via array region; S6: Based on the first, second, third, and fourth insulation reinforcement data, the insulation reinforcement result is obtained by adding the outermost insulating material to the printed circuit board, thus completing the insulation reinforcement of the medium and high voltage printed circuit board.

[0027] In some embodiments of this specification, the processor utilizes a medium-high voltage printed circuit board to perform an insulation strengthening method for the medium-high voltage printed circuit board. (1) Based on the initial structural data between the positive DC terminal pad and the negative DC terminal pad, the outermost insulation thickness is effectively increased by optimizing the spacing of the air groove width and the distance between the DC conductor and the point potential conductor in the system and adding a first shielding disk. This technical feature transfers the point potential conductor in the system to the inner layer of the printed circuit board and transfers the electric field peaks in the air to the inside of the busbar, alleviating the problem of excessive electric field in this area. (2) Based on the initial structural data between the DC pad and the point potential conductor in the system, the problem of excessive electric field in the air and electric field peaks at the edge of the pad is solved by reducing the extension structure of the DC pad in each printed circuit board layer and adding a second shielding disk. This technical feature reduces the number of electric field peaks and guides the electric field interaction between the point potential conductor in the system and the surface pad to the shielding disk, further introducing the electric field peaks into the inside of the printed circuit board and reducing the risk of discharge. (3) Based on the initial structural data at the capacitor terminal pads, the vertical structural misalignment at the point potential conductor and the midpoint potential conductor in the system, as well as the horizontal spacing between the outer and inner DC conductors, was achieved by changing the horizontal offset distance between them. This feature separates the peak electric fields within the printed circuit board without affecting the current carrying capacity, reduces the accumulation of peak field strength, lowers the overall electric field strength, and achieves precise control of the electric field inside the printed circuit board. (4) Based on the initial structural data of the via array region, the electric field was optimized for the region with increased exposed metal area by adding a circumferentially outward-extending shielding layer below the via array region. This feature introduces the field strength peaks in this region from the air into the interior of the printed circuit board, reducing the risk of partial discharge (PD). (5) Based on the first to fourth insulation enhancement data, the outermost conductor was transferred to the interior of the printed circuit board by adding an outermost layer of insulation material. By combining the above multi-region electric field weakening designs, a significant optimization of insulation performance was achieved, resulting in an increase of 15% to 25% in the average partial discharge initiation voltage (PDIV) of each interface.

[0028] Example 2 Figure 2 This is an exemplary flowchart illustrating an insulation strengthening method for a medium-to-high voltage printed circuit board according to some embodiments of this specification. Figure 2 As shown, the process includes the following steps. In some embodiments, the process may be executed by a processor.

[0029] S1: Based on the initial structural data between the positive DC terminal pad and the negative DC terminal pad, the first insulation reinforcement data is obtained by optimizing the spacing of the air groove width and the distance of the DC conductor from the point potential conductor in the system and adding the first shielding disk.

[0030] The initial structural data between the positive and negative DC terminal pads refers to the three-dimensional model data and physical dimension information of the positive and negative DC terminal areas of the printed circuit board before insulation optimization. Specifically, it includes: the initial stack-up parameters of the printed circuit board, the geometric dimensions of the surface pads, the initial air groove width between the positive and negative terminals, and the distance of the DC conductor from the point potential conductor in the system in the initial state.

[0031] In some embodiments, the processor can obtain initial structural data between the positive DC terminal pad and the negative DC terminal pad by reading a preset initial printed circuit board design drawing in external memory or by receiving structural dimensions input by the user in 3D modeling software (such as Altium Designer).

[0032] The first shielding disk refers to a solid conductor structure used to weaken the electric field spikes between the positive DC terminal pad and the negative DC terminal pad. Specifically, it includes: a solid copper conductor model parameter with the same shape as the surface pad, slightly larger in size, and arranged below the surface pad.

[0033] In some embodiments, the processor can obtain the structural model of the first shielding disk by executing a conformal amplification instruction in the conductor layer of the 3D modeling software and adding it to a specified printed circuit board stack location.

[0034] The first insulation enhancement data refers to the structural and electric field distribution information after optimizing the spacing between the positive and negative DC terminals and adding the first shielding disk. Specifically, it includes: the air slot width range parameters determined by optimization, the distance parameters between the DC conductor and the point potential conductor in the system, and the three-dimensional electric field distribution matrix showing the transfer of electric field peaks from the air to the inside of the printed circuit board after adding the first shielding disk.

[0035] In some embodiments, the processor can obtain the first insulation reinforcement data by running electric field simulation software (such as COMSOL) to save the optimized model file after adjusting the spacing parameters and adding structures.

[0036] In some embodiments, the processor may obtain first insulation reinforcement data based on the initial structural data between the positive DC terminal pad and the negative DC terminal pad by setting the optimization range of the air groove width as a first setting range and the optimization range of the distance of the DC conductor from the point potential conductor in the system as a second setting range, and arranging a larger-sized conductor of the same shape as a first shielding pad below the surface pad; wherein the first setting range is one to four millimeters and the second setting range is nine to thirteen millimeters.

[0037] S2: Based on the initial structural data between the DC pad and the point potential conductor in the system, the second insulation reinforcement data is obtained by reducing the extension structure of the DC pad on each printed circuit board layer and adding a second shielding pad.

[0038] The initial structural data between the DC pads and the point potential conductors in the system refers to the physical arrangement information before any improvements were made to the pad structure. Specifically, this includes: the extension structural parameters of the DC pads on each printed circuit board layer, as well as the overlap area and relative distance data between the DC pads and the point potential conductors in the system in the initial vertical projection direction.

[0039] In some embodiments, the processor can obtain initial structural data between the DC pads and the point potential conductors in the system by calling the first test group overlay routing file of the printed circuit board and extracting the cross-sectional features of the DC terminal area.

[0040] The second shielding disk refers to the solid conductor structure located between the DC pad and the point potential conductor in the system, used to guide the interaction of electric fields. Specifically, it includes the area size, thickness, and insulation spacing parameters of the shielding layer arranged on the outermost or inner layer of the printed circuit board, as well as the distance between the shielding layer and the upper and lower conductors.

[0041] In some embodiments, the processor can obtain the structure of the second shielding disk by receiving an instruction to add a shielding layer in the PCB fabrication file and generating a conductor polygon mesh in a specified physical layer.

[0042] The second insulation enhancement data refers to the internal structural parameters of the printed circuit board after improving the DC pad structure and adding a second shielding pad. Specifically, it includes: the volume and position parameters of the insulating material filling after removing the copper conductor of the intermediate layer (such as the L3 layer), as well as the insulation distance and electric field strength data between conductors at different potentials after the second shielding pad is installed.

[0043] In some embodiments, the processor can obtain second insulation reinforcement data by saving a three-dimensional solid model file after structural reduction and insulation material property assignment operations.

[0044] In some embodiments, the processor can obtain second insulation reinforcement data based on the initial structural data between the DC pad and the point potential conductor in the system, by subtracting the copper conductor of the intermediate layer of the DC pad and filling it with insulating material, while adding a second shielding disk.

[0045] S3: Based on the initial structural data at the capacitor terminal pads, the third insulation reinforcement data is obtained by changing the horizontal offset distance between the point potential conductor and the midpoint potential conductor in the system, as well as the horizontal spacing between the outer and inner DC conductors.

[0046] The initial structural data at the capacitor terminal pads refers to the relative position information of the multi-potential conductor cluster area before offset processing. Specifically, it includes: the initial horizontal coordinates of the point potential conductor and the midpoint potential conductor in the system, as well as the initial vertical projection and horizontal distance parameters of the outer DC conductor and the inner DC conductor.

[0047] In some embodiments, the processor can obtain the initial structural data at the capacitor terminal pads by parsing the geometric topological relationship of the capacitor terminal area in the printed circuit board design drawings.

[0048] The third insulation enhancement data refers to the spatial distribution and electric field strength changes in the capacitor terminal area after implementing conductor offset technology. Specifically, it includes: the changed horizontal offset distance between the point potential conductor and the midpoint potential conductor in the system, the changed horizontal spacing between the outer and inner DC conductors, and simulation data after the peak electric field is separated and the overall strength is reduced.

[0049] In some embodiments, the processor can obtain third insulation reinforcement data by recording the execution results of coordinate translation instructions and the electric field simulation report of the corresponding region.

[0050] In some embodiments, the processor may obtain third insulation reinforcement data based on the initial structural data at the capacitor terminal pads by setting the horizontal offset distance between the point potential conductor and the midpoint potential conductor in the system to a third set range, and setting the horizontal spacing between the outer layer and the inner layer DC conductor to a fourth set range; wherein the third set range is 0.5 to 5 mm, and the fourth set range is 0.5 to 2.5 mm.

[0051] S4: Based on the initial structural data of the aperture array region, the fourth insulation enhancement data is obtained by adding a shielding layer extending outward in a circumferential direction below the aperture array region.

[0052] The initial structural data of the via array region refers to the geometric parameters of the area with a large exposed metal area on the printed circuit board. Specifically, it includes: the diameter of the vias, the spacing between vias, the array arrangement, and the initial thickness and material parameters of the insulating medium beneath the via array.

[0053] In some embodiments, the processor can obtain the initial structural data of the via array region by reading the drilling table and stack-up attributes in the printed circuit board via design file.

[0054] The fourth insulation enhancement data refers to the physical structure and electric field optimization information after shielding is implemented below the via array. Specifically, it includes: the size of the shielding layer located directly below the via array, the circumferential extension distance of the shielding layer edge beyond the outer edge of the via array, and the electric field distribution pattern of the field strength peaks introduced into the printed circuit board.

[0055] In some embodiments, the processor can obtain fourth insulation enhancement data by saving model parameters after the shielding layer extension operation and partial discharge test simulation data.

[0056] In some embodiments, the processor may obtain fourth insulation enhancement data based on the initial structural data of the aperture array region by adding a shielding layer extending outward in a circumferential direction by one to two millimeters below the aperture array region.

[0057] S5: Based on the first insulation reinforcement data, the second insulation reinforcement data, the third insulation reinforcement data, and the fourth insulation reinforcement data, the insulation reinforcement result is obtained by adding the outermost layer of insulating material to the printed circuit board, thus completing the insulation reinforcement of the medium and high voltage printed circuit board.

[0058] Insulation enhancement results refer to the final overall printed circuit board design scheme after integrating all optimization methods in high field strength areas. Specifically, it includes: the complete stack-up sequence of the ten-layer printed circuit board, the conductor layout coordinates of each layer, the insulation thickness data between layers, and the target test value for the improvement of the average partial discharge initiation voltage (PDIV) of each interface.

[0059] In some embodiments, the processor can obtain the insulation reinforcement result by aggregating the first to fourth insulation reinforcement data and fusing the outermost insulation addition instructions to generate a complete photoplot file (Gerber file) that can be used for manufacturing pipelines.

[0060] Figure 1 This is an exemplary schematic diagram showing the DC terminal pads and electric field distribution according to some embodiments of this specification. Between the positive DC terminal pads, as... Figure 1 As shown in part (a), the voltage difference between the positive and negative DC terminals is 6 kilovolts, L1 is the preset slot width, and L2 is the preset distance between the DC conductor and the point potential conductor in the system. An electric field simulation is performed at this location as follows: Figure 1 As shown in (b), the high field strength points are all concentrated in the air region.

[0061] Parameter scans were performed sequentially on L1 and L2, and the relationship between the maximum electric field strength in the air and L1 and L2 was plotted, as follows: Figure 3Finally, the range of L1 was selected as [1,4] mm, and L2 as [9,13] mm.

[0062] To further suppress the risk of discharge at this location, a shielding disk 3 is introduced, such as... Figure 4 (a) A conductor of the same shape, larger than the surface pad, is arranged below the surface pad as a first shielding pad 1, effectively increasing the outermost insulation thickness. This transfers the point potential conductor in the system to the inner layer of the printed circuit board, while simultaneously transferring the electric field strength interaction to the interior of the printed circuit board. For example... Figure 4 As shown in (b), the electric field distribution is further optimized, and the electric field peaks in the air are transferred to the interior of the busbar.

[0063] The structure between DC pad 2 and point potential conductor 3 in the system is as follows: Figure 5 (a) Different potential layers cluster nearby, causing electric field spikes to appear in this region. To simplify the simulation process, the four-layer DC conductor is simplified to two layers, such as... Figure 5 As shown in (b), the white area indicates an electric field strength exceeding the limit of 2 kV / mm. The electric field strength in the air is greater than 2 kV / mm.

[0064] To reduce the risk of discharge, optimizations are made to the conventional pads. This involves reducing the extension structure of the pads on each layer (i.e., the original conventional structure) without affecting the current carrying capacity, thus reducing the number of electric field spikes. Figure 6 As shown, the copper conductor of layer L3 of the pads was removed and filled with insulating material. After optimizing the pad structure and adding the outermost layer of insulation, the point potential conductor in the system was transferred to the second outermost layer of the printed circuit board. After adding a shielding pad 7, the point potential conductor 3 in the system was transferred to the inner layer of the printed circuit board. The electric field interaction that originally existed between the point potential conductor 3 in the system and the surface DC pad 2 was guided to the shielding pad, and the electric field spikes were also transferred to the interior of the printed circuit board, as shown in the figure. Figure 6 As shown.

[0065] The structure at the capacitor terminal pads is as follows Figure 7 (a) Here, multi-potential conductors are clustered, posing a high risk of partial discharge. Based on previous insulation optimization, conductor offset technology will be further employed to optimize the electric field. Here, offset represents the horizontal offset distance between the point potential conductor 6 and the midpoint potential conductor 7 in the system, and w represents the horizontal distance between the outer DC conductor 8 and the inner DC conductor 9. Figure 7 (b) shows the internal electric field distribution of the printed circuit board without conductor offset technology. As the offset increases, the peak electric field in region I separates and the overall intensity decreases, therefore the offset range is [0.5, 5] mm. Further scanning of parameter w is performed at [-2.5, 0.5, 2.5] mm. Figure 7(c) shows the relationship between the maximum electric field strength inside the printed circuit board and W. Therefore, the range of W is set to [0.5, 2.5] mm, at which point the maximum electric field strength inside the printed circuit board decreases to [0.5, 2.5] mm. Figure 7 (d) shows the electric field distribution after using the conductor offset technique.

[0066] Hole array region 10 Figure 8 As shown in (a), the increased exposed metal area can easily lead to excessive field strength in the air, resulting in partial discharge. Therefore, it is necessary to add a shielding layer 11 extending 1-2 mm outward in the circumferential direction below this area to reduce the risk of discharge. Figure 8 (b) and Figure 8 (c) shows a comparison of the electric field distribution with and without a shielding layer, where the shielding layer introduces the field strength spikes from the air into the printed circuit board.

[0067] A 50Hz AC test was performed on the printed circuit board using sinusoidal AC excitation to measure the partial discharge level, such as... Figure 9 As shown. Three versions of printed circuit boards were fabricated sequentially for comparison: the first test group had no insulation optimization; the second test group applied shielding technology and added an outermost layer of insulation (transferring the outer conductor to the inside of the printed circuit board); the third test group, based on the third version, further adopted spacing optimization and conductor offset technology. The experiment covered the main test combinations by connecting the high-voltage terminal and the ground terminal to the terminals of the printed circuit board. The test results are shown below. Figure 9 (a) Figure 9 (b) Figure 9 As shown in (c), five samples were tested for each version, with the red dots representing the design target values. Figure 9 (d) shows the average and target values ​​of the partial discharge initiation voltage for the three printed circuit boards. The second test group achieved significant optimization of insulation performance by increasing insulation thickness and shielding structure. The third test group used spacing optimization and conductor offset technology to optimize the spacing between DC terminals + and -, between DC terminals and N, and between N and M. This reduced the electric field strength inside the printed circuit board to a certain extent, achieving precise control of the electric field and further increasing the average partial discharge initiation voltage of each interface by 15% to 25% compared to the second test group.

[0068] It should be noted that different embodiments may produce different beneficial effects. In different embodiments, the beneficial effects may be any one or a combination of the above, or any other possible beneficial effects.

Claims

1. A method for strengthening the insulation of medium- and high-voltage printed circuit boards, characterized in that, include: S1: Based on the initial structural data between the positive DC terminal pad and the negative DC terminal pad, the first insulation reinforcement data is obtained by optimizing the spacing of the air groove width and the distance of the DC conductor from the point potential conductor in the system and adding the first shielding disk. S2: Based on the initial structural data between the DC pad and the point potential conductor in the system, the second insulation reinforcement data is obtained by reducing the extension structure of the DC pad on each printed circuit board layer and adding a second shielding pad. S3: Based on the initial structural data at the capacitor terminal pads, the third insulation reinforcement data is obtained by changing the horizontal offset distance between the point potential conductor and the midpoint potential conductor in the system and the horizontal spacing between the outer layer and the inner layer DC conductor. S4: Based on the initial structural data of the aperture array region, the fourth insulation enhancement data is obtained by adding a shielding layer extending outward in a circumferential direction below the aperture array region. S5: Based on the first insulation reinforcement data, the second insulation reinforcement data, the third insulation reinforcement data, and the fourth insulation reinforcement data, the insulation reinforcement result is obtained by adding the outermost layer of insulating material to the printed circuit board, thus completing the insulation reinforcement of the medium and high voltage printed circuit board.

2. The insulation strengthening method for medium and high voltage printed circuit boards according to claim 1, characterized in that, S1 includes: Based on the initial structural data between the positive DC terminal pad and the negative DC terminal pad, the first insulation reinforcement data is obtained by setting the optimization range of the air groove width as a first setting range and the optimization range of the distance between the DC conductor and the point potential conductor in the system as a second setting range, and arranging a larger-sized conductor of the same shape as a first shielding pad below the surface pad; wherein, the first setting range is one to four millimeters, and the second setting range is nine to thirteen millimeters.

3. The insulation strengthening method for medium and high voltage printed circuit boards according to claim 1, characterized in that, S2 includes: Based on the initial structural data between the DC pad and the point potential conductor in the system, the second insulation reinforcement data is obtained by subtracting the copper conductor of the middle layer of the DC pad and filling it with insulating material, while adding a second shielding disk.

4. The insulation strengthening method for medium and high voltage printed circuit boards according to claim 1, characterized in that, S3 includes: Based on the initial structural data at the capacitor terminal pads, a third insulation reinforcement data is obtained by setting the horizontal offset distance between the point potential conductor and the midpoint potential conductor in the system as a third setting range, and setting the horizontal spacing between the outer layer and the inner layer DC conductor as a fourth setting range; wherein the third setting range is 0.5 to 5 mm, and the fourth setting range is 0.5 to 2.5 mm.

5. The insulation strengthening method for medium and high voltage printed circuit boards according to claim 1, characterized in that, S4 includes: Based on the initial structural data of the aperture array region, the fourth insulation enhancement data was obtained by adding a shielding layer extending outward by one to two millimeters in the circumferential direction below the aperture array region.

6. A medium- and high-voltage printed circuit board, used to perform the insulation strengthening method for a medium- and high-voltage printed circuit board as described in any one of claims 1 to 5, characterized in that, include: First shielding disk (1), DC pad (2), system point potential conductor (3), second shielding disk (5), system point potential conductor (6), midpoint potential conductor (7), outer DC conductor (8), inner DC conductor (9), hole array area (10), and shielding layer (11); The first shielding disk (1) is arranged below the surface pads of the printed circuit board; The DC pad (2) has the extension structure (4) of the intermediate conductor layer removed, and the second shielding disk (5) is arranged between the DC pad (2) and the point potential conductor (3) in the system. The system's point potential conductor (3), the system's point potential conductor (6), the midpoint potential conductor (7), the outer layer DC conductor (8), and the inner layer DC conductor (9) are respectively arranged in different potential conductor layers inside the printed circuit board; a horizontal offset distance is provided between the system's point potential conductor (6) and the midpoint potential conductor (7); a horizontal spacing is provided between the outer layer DC conductor (8) and the inner layer DC conductor (9); The shielding layer (11) is arranged below the hole array region (10), and the shielding layer (11) extends outward in a circumferential direction.

7. The medium-voltage printed circuit board according to claim 6, characterized in that, The printed circuit board also includes: a positive DC terminal pad, a negative DC terminal pad, and a DC conductor; An air groove is provided between the positive DC terminal pad and the negative DC terminal pad, and the air groove has a preset groove width. A preset distance is provided between the DC conductor and the point potential conductor (3) in the system.

8. The medium-voltage printed circuit board according to claim 6, characterized in that, The printed circuit board has a ten-layer structure, including the first to tenth layers stacked sequentially from the outside to the inside, and an insulating thickness is provided between adjacent layers; The first layer only has the surface pads and vias; The second layer and the ninth layer are the same shielding layer, and the first shielding disk (1), the second shielding disk (5) and the shielding layer (11) are arranged in the second layer and the ninth layer; The third layer and the eighth layer are the same system point potential conductor layers. The system point potential conductor (3) and the system point potential conductor (6) are arranged in the third layer and the eighth layer, and are connected by potential through through holes. The fourth to the seventh layers contain the same DC conductor and midpoint potential conductor. Conductors with the same potential are connected by a through hole, and conductors with different potentials are kept at an insulating distance. The midpoint potential conductor (7), the outer DC conductor (8), and the inner DC conductor (9) are arranged in the fourth to the seventh layers. The third to eighth layers and the tenth layer contain the same AC terminal conductors, and the AC terminal conductors in each layer are electrically connected through through holes.

9. The medium-voltage printed circuit board according to claim 8, characterized in that, The extension structure (4) of the intermediate conductor layer subtracted from the DC pad (2) is specifically the copper conductor of the DC pad (2) in the third layer, and the space corresponding to the third layer is filled with insulating material. The second shielding disk (5) is arranged in the second layer, such that the electric field interaction between the point potential conductor (3) in the system and the surface pad is transferred to the second shielding disk (5).

10. The medium-voltage printed circuit board according to claim 6, characterized in that, The point potential conductor (6) and the midpoint potential conductor (7) in the system are misaligned in the horizontal direction, forming the horizontal offset distance; The shielding layer (11) is distributed directly below the hole array region (10), and the edge of the shielding layer (11) extends beyond the outer edge of the hole array region (10), forming a circumferential outward extension.

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