Multifunctional ceramic package substrate and method of manufacturing the same

Abstract

This invention proposes a multifunctional ceramic packaging substrate and its fabrication method, relating to the field of semiconductor technology. The multifunctional ceramic packaging substrate includes a ceramic core board and a wiring layer; the wiring layer is disposed on the side of the ceramic core board, and multiple chips and multiple passive devices are embedded within the wiring layer, with the chips and passive devices electrically interconnected with the wiring layer. This invention also proposes a fabrication method for the multifunctional ceramic packaging substrate, comprising the following steps: providing a ceramic core board; forming a plurality of interconnect holes through the ceramic core board; embedding corresponding chips and passive devices within the wiring layer; forming a second layer by distributing a plurality of stacked ABF / BT layers outside the first layer, the first and second layers forming an ABF / BT composite layer; distributing a solder resist layer outside the ABF / BT composite layer; and distributing a surface treatment layer outside the solder resist layer. This invention embeds chips and passive devices into the wiring layer, improving circuit reliability and the overall area utilization of the ceramic core board, and reducing signal transmission delay.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a multifunctional ceramic packaging substrate and its preparation method. Background Technology

[0002] As the core carrier of high-precision electronic devices, the ceramic core board's outer wiring layer only serves the single function of "circuit interconnection." Chips and passive components (resistors, capacitors, inductors) need to be individually fixed to the wiring layer surface using surface mount technology. This separate structure of "wiring layer + surface mount components" has significant drawbacks: First, the connection between the components and the wiring layer surface relies on solder joints, which are prone to cracking and increased contact resistance due to long-term temperature changes and vibrations, leading to decreased circuit reliability. Second, the components protrude from the wiring layer surface, requiring additional protective structures and increasing the overall thickness of the device (usually by 0.3-0.8 mm), failing to meet the requirements for thinner and lighter electronic devices. Third, the dispersed layout of the wiring layer and components lengthens the signal transmission path (40%-60% longer than the ideal path), easily causing signal delay and crosstalk, making it difficult to adapt to high-frequency and high-speed circuit scenarios. Summary of the Invention

[0003] The purpose of this invention is to provide a multifunctional ceramic packaging substrate and its preparation method to solve the technical problems in the background.

[0004] The embodiments of the present invention are implemented as follows: This application provides a multifunctional ceramic packaging substrate, including a ceramic core board and a wiring layer; the wiring layer is disposed on the side of the ceramic core board, and multiple chips and multiple passive devices are embedded in the wiring layer, and the chips and passive devices are electrically interconnected with the wiring layer.

[0005] In some embodiments of the present invention, the ceramic core board includes a ceramic substrate and an electroplated copper coating layer; a plurality of interconnecting holes are provided on the ceramic substrate, the interconnecting holes penetrating the upper and lower surfaces of the ceramic substrate; the electroplated copper coating layer is provided on the upper and lower surfaces of the ceramic substrate and on the hole walls of the interconnecting holes; the interconnecting holes are also filled with ink.

[0006] In some embodiments of the present invention, the above-mentioned wiring layer is an ABF / BT composite layer, and ABF / BT composite layers are provided on both sides of the ceramic core board. The ABF / BT composite layer includes a plurality of stacked ABF / BT layers, and a copper clad laminate layer is provided on the outer side of each ABF / BT layer. A plurality of grooves are provided on the copper clad laminate layer, and blind vias are provided on the ABF / BT layers at each groove. Copper pillars are provided in the blind vias. A solder mask layer is provided on the surface of the outermost ABF / BT layer, and a surface treatment layer is provided on the outside of the solder mask layer; blind holes with built-in copper pillars are also provided on the surface treatment layer. The electroplated copper film layer, copper clad laminate layer and surface treatment layer are all metal layers, and each metal layer is provided with several interconnected solder pads. Electrical connections are made between the interconnecting pads of different copper clad laminate layers, and between the interconnecting pads of the copper clad laminate layer and the electroplated copper coating layer, through corresponding copper pillars.

[0007] In some embodiments of the present invention, the ceramic substrate is 92 ceramic, 95 ceramic or 99 ceramic, and is made of alumina, aluminum nitride or silicon nitride material.

[0008] In some embodiments of the present invention, the wiring layer is provided with a first cavity corresponding to the chip, the chip is disposed in the first cavity corresponding to it, and the inner wall of the first cavity is provided with a first conductive contact corresponding to the wiring layer and connected to the wiring layer. The first conductive contact is used to realize the electrical interconnection between the wiring layer and the chip.

[0009] In some embodiments of the present invention, a second cavity corresponding to each of the passive devices is provided in the wiring layer. The passive devices are disposed in the corresponding second cavities. The inner wall of the second cavity is provided with a second conductive contact corresponding to the wiring layer and connected to the wiring layer. The second conductive contact is used to realize the electrical interconnection between the wiring layer and the passive devices.

[0010] Secondly, embodiments of this application provide a method for preparing a multifunctional ceramic packaging substrate, comprising the following steps: S101, Provide ceramic core board; S102. Several interconnecting holes are drilled through the ceramic core board, and an electroplated copper coating layer is set on the surface of the ceramic core board and the hole walls of the interconnecting holes. Finally, ink is filled into the interconnecting holes. S103. An ABF / BT composite layer is provided on both sides of the ceramic core board, and corresponding chips and passive devices are embedded in the ABF / BT composite layer. S104. Several overlapping ABF / BT layers are arranged on the outside of the first layer to form a second layer, and the first layer and the second layer form an ABF / BT composite layer. S105. A solder resist layer is provided on the outside of the ABF / BT composite layer; S106. A surface treatment layer is provided on the outside of the solder resist layer.

[0011] In some embodiments of the present invention, step S103 specifically includes: providing the plurality of stacked ABF / BT layers on both sides of the ceramic core board to form a first layer body, providing a copper clad laminate layer on the outside of each ABF / BT layer, and forming a plurality of interconnecting pads on the copper clad laminate layer; providing a plurality of grooves on the copper clad laminate layer, and providing blind vias on the ABF layer at each groove; and providing copper pillars in the blind vias. A first cavity for mounting the chip and a second cavity for mounting passive devices are provided on the outer side of the first layer, so that the chip and passive devices are respectively embedded into the corresponding first cavity and second cavity.

[0012] Compared with the prior art, the embodiments of the present invention have at least the following advantages or beneficial effects: 1. Significantly improved reliability: By embedding chips and passive components into the wiring layer, the passive components and wiring layer form an integrated structure, avoiding problems such as solder joint cracking and increased contact resistance caused by exposing the solder joints of passive components to the external environment in traditional structures and processes, thus improving circuit reliability; 2. Passive components are embedded inside the wiring layer, eliminating the need to reserve installation space for passive components on the surface of the wiring layer or add additional protective structures for passive components. The overall area utilization of the ceramic core board is greatly improved, and the thickness is reduced compared to the traditional structure, making it fully compatible with the needs of thin and light electronic devices. 3. The connection distance between chips and embedded devices and wiring layers is effectively shortened, signal transmission delay is reduced, and the needs of high-frequency and high-speed circuits can be met. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the structure of an embodiment of the present invention rotated 90°; Figure 2 This is a schematic diagram of the structure of a traditional ceramic substrate in the prior art.

[0015] Icons: 001-Ceramic packaging substrate; 100-Ceramic core board; 101-Ceramic substrate; 210-Electroplated copper coating layer; 230-Blind via; 240-Groove; 250-Surface treatment layer; 300-ABF / BT composite layer; 310-Interconnect via; 320-ABF / BT layer; 330-Solder resist layer; 511-Passive components; 700-Protective structure. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0017] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0018] Example 1 Please refer to Figure 1 This embodiment provides a multifunctional ceramic packaging substrate 101, including a ceramic core board 100 and a wiring layer. The wiring layer is disposed on the side of the ceramic core board 100, and multiple chips and multiple passive devices 511 are embedded in the wiring layer. The chips and passive devices 511 are electrically interconnected with the wiring layer. Embedding the chips and passive devices 511 into the wiring layer makes the passive devices 511 and the wiring layer form an integrated structure, avoiding the traditional ceramic substrate 101 structure (please refer to...). Figure 2 This design avoids issues like solder joint cracking and increased contact resistance caused by exposing the solder joints of passive components 511 to the external environment, thus improving circuit reliability. The passive components 511 are embedded within the wiring layer, eliminating the need for pre-reserved mounting space and additional protective structures 700 on the wiring layer surface. This significantly improves the overall area utilization of the ceramic core board 100 and reduces its thickness compared to traditional structures, perfectly meeting the demands of thinner and lighter electronic devices. The connection distance between the chip and embedded devices and the wiring layer lines is effectively shortened, reducing signal transmission delay and meeting the needs of high-frequency and high-speed circuits.

[0019] Furthermore, this embodiment also has the advantage of strong process compatibility: the prefabrication of the embedded first cavity and the second cavity can be carried out simultaneously with the conventional fabrication process of the wiring layer without the need to introduce new equipment, and the passive device 511 embedding process can be adapted to the transformation and upgrading of existing surface mount production lines, which is convenient for industrial mass production; at the same time, the embedded chip or passive device 511 can be flexibly replaced according to circuit requirements, improving the versatility and maintainability of the ceramic core board 100, and further expanding its application scope in aerospace, automotive electronics, precision instruments and other fields.

[0020] Please refer to Figure 1Furthermore, in this embodiment, the ceramic core board 100 includes a ceramic substrate 101 and an electroplated copper coating layer 210. The ceramic substrate 101 has a plurality of interconnecting holes 310, which penetrate the upper and lower surfaces of the ceramic substrate 101. The upper and lower surfaces of the ceramic substrate 101, as well as the walls of the interconnecting holes 310, are all provided with the electroplated copper coating layer 210. The interconnecting holes 310 are also filled with ink. Specifically, in this embodiment, the interconnecting holes 310 penetrating the ceramic substrate 101 are formed by laser drilling, and electroplating is performed on the sidewalls of the interconnecting holes 310 to form a conductive copper dielectric layer. This technology ensures reliable conductivity between the ceramic substrate 101 and the ABF or BT material. The ink filling in the interconnecting holes 310 improves the filling reliability of the interconnecting holes 310 and also enhances the conductivity of the upper and lower surfaces.

[0021] Please refer to Figure 1 Preferably, the aforementioned wiring layer is an ABF / BT composite layer 300. ABF / BT composite layers 300 are provided on both sides of the ceramic core board 100. Each ABF / BT composite layer 300 includes several stacked ABF / BT layers 320, and a copper-clad laminate layer is provided on the outer side of each ABF / BT layer 320. Several grooves 240 are provided on the copper-clad laminate layer, and blind vias 230 are provided on the ABF / BT layer 320 at each groove 240. Copper pillars are provided within the blind vias 230. A solder mask layer 330 is provided on the surface of the outermost ABF / BT layer 320, and a surface treatment layer 250 is provided on the outer side of the solder mask layer 330. Blind vias 230 with built-in copper pillars are also provided on the surface treatment layer 250. The electroplated copper film layer 210, the copper-clad laminate layer, and the surface treatment layer 250 are all metal layers, and several interconnecting pads are provided on each metal layer. Electrical connections are established between the interconnecting pads of different copper-clad laminate layers and between the interconnecting pads of the copper-clad laminate layer and the electroplated copper film layer 210 via corresponding copper pillars. An ABF layer or a BT layer is formed on the upper and lower surfaces of the ceramic core board 100, respectively, and a copper-clad laminate layer is prepared outside the dielectric layer. This multi-layer structure effectively improves the mechanical strength and electrical performance of the packaging substrate, while ensuring good heat dissipation and corrosion resistance. The above structure compensates for the shortcomings of ceramic materials in high-density wiring, cost control, and packaging compatibility, while retaining the core advantages of the ceramic core board 100. The ABF composite layer has good flexibility and compatibility, allowing passive components (resistors, capacitors, inductors) to be mounted on its surface or inside, or serving as a "transition layer" to connect the ceramic core board 100 with other organic substrates (such as PCBs), solving the "rigid matching" problem between ceramic and organic materials.

[0022] Please refer to Figure 1Furthermore, the aforementioned solder mask layer 330 protects the ABF / BT layer 320 and the corresponding wiring layers, isolating them from external damage and environmental corrosion. During the packaging process, soldering (such as chip bump soldering, solder ball placement, and passive component mounting) needs to be performed on the copper pads of the ABF / BT layer 320. The solder mask layer 330 precisely defines the soldering area through a "window design." The ABF layer itself has low hardness (Shore hardness D≈60-70), making it easily scratched during packaging, handling, and pressing. The solder mask layer 330, after curing, has high hardness (Shore hardness D≈85-90), which can resist minor mechanical friction or impact, protecting the ABF layer and copper wiring from physical damage. The copper pads exposed in the windowed area are roughened to improve solder wettability. With a significantly improved contact angle (≤30°), defects such as cold solder joints and poor solder joints can be reduced. At the same time, the solder mask layer 330 can prevent solder from spreading to non-pad areas, ensuring that the solder joint volume (e.g., Solder Ball diameter deviation ≤±10%) and shape meet the packaging requirements, thus improving soldering reliability. The fully cured solder mask layer 330 has excellent resistance to damp heat (no blistering or peeling of the coating and no corrosion of copper wiring after 1000 hours in an environment of 85℃ / 85%RH) and chemical resistance (can withstand immersion in common cleaning agents such as soldering flux, alcohol, and acetone), preventing the ABF layer and copper wiring from failing due to environmental factors.

[0023] Preferably, the ceramic substrate 101 is 92 ceramic, 95 ceramic or 99 ceramic, and is made of alumina, aluminum nitride or silicon nitride material.

[0024] Specifically, in this embodiment, the wiring layer is provided with a first cavity corresponding to the chip, and the chip is disposed in the first cavity (not shown in the figure). The inner wall of the first cavity is provided with a first conductive contact corresponding to the wiring layer and connected to the wiring layer. The first conductive contact is used to realize the electrical interconnection between the wiring layer and the chip.

[0025] Furthermore, in this embodiment, a second cavity (not shown in the figure) corresponding to the passive device 511 is provided in the wiring layer. The passive device 511 is disposed in the corresponding second cavity. The inner wall of the second cavity is provided with a second conductive contact corresponding to the wiring layer. The second conductive contact is used to realize the electrical interconnection between the wiring layer and the passive device 511.

[0026] Example 2 This embodiment provides a method for preparing a multifunctional ceramic packaging substrate, including the following steps: S101, Provide ceramic core board; S102. Several interconnecting holes are drilled through the ceramic core board, and an electroplated copper coating layer is set on the surface of the ceramic core board and the hole walls of the interconnecting holes. Finally, ink is filled into the interconnecting holes. S103. An ABF / BT composite layer is provided on both sides of the ceramic core board, and corresponding chips and passive devices are embedded in the ABF / BT composite layer. S104. Several overlapping ABF / BT layers are arranged on the outside of the first layer to form a second layer, and the first layer and the second layer form an ABF / BT composite layer. S105. A solder resist layer is provided on the outside of the ABF / BT composite layer; S106. A surface treatment layer is provided on the outside of the solder resist layer.

[0027] Furthermore, in this embodiment, step S103 specifically includes: setting the plurality of stacked ABF / BT layers on both sides of the ceramic core board to form a first layer, setting a copper clad laminate layer on the outside of each ABF / BT layer, and forming a plurality of interconnecting pads on the copper clad laminate layer; setting a plurality of grooves on the copper clad laminate layer, and setting blind holes on the ABF layer at each groove; and setting copper pillars in the blind holes. A first cavity for mounting the chip and a second cavity for mounting passive devices are provided on the outer side of the first layer, so that the chip and passive devices are respectively embedded into the corresponding first cavity and second cavity.

[0028] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multifunctional ceramic packaging substrate, characterized in that, It includes a ceramic core board and a wiring layer; the wiring layer is disposed on the side of the ceramic core board, and multiple chips and multiple passive devices are embedded in the wiring layer, and the chips and the passive devices are electrically interconnected with the wiring layer.

2. The multifunctional ceramic packaging substrate according to claim 1, characterized in that, The ceramic core board includes a ceramic substrate and an electroplated copper coating layer; the ceramic substrate has a plurality of interconnecting holes, which penetrate the upper and lower surfaces of the ceramic substrate; the electroplated copper coating layer is disposed on the upper and lower surfaces of the ceramic substrate and on the walls of the interconnecting holes; the interconnecting holes are also filled with ink.

3. The multifunctional ceramic packaging substrate according to claim 2, characterized in that, The wiring layer is an ABF / BT composite layer. Both sides of the ceramic core board are provided with ABF / BT composite layers. The ABF / BT composite layer includes several stacked ABF / BT layers. A copper clad laminate layer is provided on the outer side of each ABF / BT layer. Several grooves are provided on the copper clad laminate layer. Blind vias are provided on the ABF / BT layers at each groove. Copper pillars are provided in the blind vias. A solder mask layer is provided on the surface of the outermost ABF / BT layer, and a surface treatment layer is provided on the outside of the solder mask layer; blind holes with built-in copper pillars are also provided on the surface treatment layer. The electroplated copper film layer, copper clad laminate layer and surface treatment layer are all metal layers, and each metal layer is provided with several interconnected solder pads. Electrical connections are made between the interconnecting pads of different copper clad laminate layers, and between the interconnecting pads of the copper clad laminate layer and the electroplated copper coating layer, through corresponding copper pillars.

4. The multifunctional ceramic packaging substrate according to claim 1, characterized in that, The ceramic substrate is 92, 95, or 99 ceramic and is made of alumina, aluminum nitride, or silicon nitride.

5. The multifunctional ceramic packaging substrate according to claim 1, characterized in that, The wiring layer is provided with a first cavity corresponding to each chip. The chip is disposed in the first cavity corresponding to it. The inner wall of the first cavity is provided with a first conductive contact corresponding to the wiring layer and connected to it. The first conductive contact is used to realize the electrical interconnection between the wiring layer and the chip.

6. The multifunctional ceramic packaging substrate according to claim 1, characterized in that, The wiring layer is provided with a second cavity corresponding to each of the passive devices. The passive devices are disposed in the corresponding second cavities. The inner wall of the second cavity is provided with a second conductive contact that is connected to the wiring layer. The second conductive contact is used to realize the electrical interconnection between the wiring layer and the passive devices.

7. A method for preparing a multifunctional ceramic packaging substrate, characterized in that, Includes the following steps: S101, Provide ceramic core board; S102. Several interconnecting holes are drilled through the ceramic core board, and an electroplated copper coating layer is set on the surface of the ceramic core board and the hole walls of the interconnecting holes. Finally, ink is filled into the interconnecting holes. S103. An ABF / BT composite layer is provided on both sides of the ceramic core board, and corresponding chips and passive devices are embedded in the ABF / BT composite layer. S104. Several overlapping ABF / BT layers are arranged on the outside of the first layer to form a second layer, and the first layer and the second layer form an ABF / BT composite layer. S105. A solder resist layer is provided on the outside of the ABF / BT composite layer; S106. A surface treatment layer is provided on the outside of the solder resist layer.

8. The method for preparing a multifunctional ceramic packaging substrate according to claim 7, characterized in that, Step S103 specifically includes: setting the plurality of stacked ABF / BT layers on both sides of the ceramic core board to form a first layer, setting a copper clad laminate layer on the outside of each ABF / BT layer, and forming a plurality of interconnecting pads on the copper clad laminate layer; setting a plurality of grooves on the copper clad laminate layer, and setting blind vias on the ABF layer at each groove; and setting copper pillars in the blind vias. A first cavity for mounting the chip and a second cavity for mounting passive devices are provided on the outer side of the first layer, so that the chip and passive devices are respectively embedded into the corresponding first cavity and second cavity.

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