Semiconductor aging monitoring

Abstract

This disclosure relates to semiconductor aging monitoring. An aging monitor circuit is provided that compares the frequency of an aging oscillator with the frequency of a fresh oscillator to determine an aging value. A power supply voltage regulation circuit is also provided that can use first and second oscillators to identify the amount of power supply voltage regulation required to maintain the transistor performance level.

Description

Technical Field

[0001] This disclosure generally relates to the semiconductor field, and more specifically to semiconductor aging monitoring. Background Technology

[0002] The aging process of modern electronic and semiconductor devices poses a significant risk to their reliable operation throughout their expected lifespan. A reliable aging sensor is needed to prevent device failure and alert users before failure occurs.

[0003] Various aging monitoring schemes exist. So-called digital aging sensors (DAS) use sophisticated methods to measure the delay differences of the same timing path under stress and without stress, and translate these differences into voltage degradation. The drawbacks of these DAS methods include their complexity, the need for a relatively large number of fuses, calibration procedures, manufacturing and verification support operations, and temperature-related accuracy. Another approach calculates the number of time-critical circuits under stress by capturing and accumulating the duration under high-stress conditions (e.g., higher voltage / frequency patterns) and converting these durations into voltage degradation levels using predefined formulas. However, this approach typically requires non-volatile memory to store the accumulated stress information. Another drawback is their reliance on predefined correlation formulas based on worst-case cell values ​​rather than per-cell values, leading to accuracy issues. Summary of the Invention

[0004] One aspect of this disclosure provides an apparatus comprising: a circuit group coupled to a power supply voltage node; a management circuit; a first oscillator including a first power node coupled to the power supply voltage node via a switch controlled by the management circuit; and a second oscillator coupled to the power supply voltage node along with the circuit group.

[0005] One aspect of this disclosure provides an apparatus comprising: a circuit group coupled to a power supply voltage node; a management circuit; a first oscillator including a first power supply node coupled to the power supply voltage node via a switch controlled by the management circuit; a second oscillator including a second power supply node; and a multiplexer including: (i) a multiplexer output node coupled to the second power supply node, (ii) a first multiplexer input coupled to the power supply voltage node, and (iii) a second multiplexer input coupled to a variable voltage source controllable by the management circuit.

[0006] One aspect of this disclosure provides a non-transient computer-readable storage medium having instructions that, when executed, perform a method comprising: measuring a first frequency from a first oscillator; measuring a second frequency from a second oscillator configured identically to the first oscillator and powered together with a circuit group to be monitored; removing power from the first oscillator when the first frequency is not measured; and determining an aging value for the circuit group based on the first frequency and the second frequency.

[0007] One aspect of this disclosure provides a system including a processor, the processor including the aforementioned storage medium. Attached Figure Description

[0008] This disclosure can be best understood by referring to the following description and accompanying drawings, which illustrate the embodiments. In the drawings: Figure 1 This is a block diagram illustrating a processor with an aging monitor circuit according to some embodiments.

[0009] Figure 2 This is a block diagram illustrating an aging monitor circuit according to some embodiments.

[0010] Figure 3 This is a mixed flowchart illustrating an aging monitoring routine according to some embodiments.

[0011] Figure 4 This is a block diagram illustrating an aging monitor circuit for monitoring a group of circuits according to some embodiments.

[0012] Figure 5 This is a flowchart illustrating another routine for monitoring aging according to some embodiments.

[0013] Figure 6A This is a block diagram illustrating a dynamic voltage regulation circuit for regulating the power supply voltage of a monitored circuit according to some embodiments.

[0014] Figure 6B This is a flowchart illustrating a routine for dynamically adjusting the power supply voltage according to some embodiments.

[0015] Figure 7A This is a diagram illustrating the voltage required to maintain operational performance according to some embodiments.

[0016] Figure 7B This is a graph illustrating the relationship between the operating frequency of a circuit and the voltage required to reach that frequency as the circuit ages, according to some embodiments.

[0017] Figure 8The figure illustrates an example computing system comprising one or more aging monitors and / or voltage regulation circuits according to some embodiments.

[0018] Figure 9 The figure shows a block diagram of an example processor and / or SoC 900 according to some embodiments, which may have one or more cores and an integrated memory controller, and may include an aging monitor and / or voltage regulation circuitry.

[0019] Figure 10 This is a block diagram illustrating a computing system 1000 configured to implement one or more aspects of the examples described herein. Detailed Implementation

[0020] In addition to allowing for stricter power supply voltage protection bands, efficient and accurate aging monitor circuits can be used to prevent counterfeiting (e.g., to identify old chips masquerading as new chips), as well as for other purposes.

[0021] In some embodiments, an aging monitor circuit is provided that is reasonably independent of temperature and voltage, accurate, and relatively easy to implement.

[0022] Figure 1 This is a block diagram illustrating an aging monitor circuit 102 according to some embodiments. The processor 100 includes IP (intellectual property) circuitry 105, a system management controller (SMC) 110, a processing core 115, shared cache circuitry 120, a memory controller 125, I / O interface circuitry 130, and system architecture 135, all coupled together as shown. It also includes a memory module 145 coupled to one or more memory controllers 125 via memory channels. Similarly, it includes I / O devices 155 coupled to I / O interface circuitry 150 via I / O interface channels.

[0023] Processor device 100 includes at least one hardware circuit configured to execute instructions contained in program code (e.g., in processor core 115). The hardware circuit can be implemented using one or more integrated circuits. Examples of processor types that can be implemented in processor 100 include, but are not limited to, central processing unit (CPU), array processor, vector processor, digital signal processor (DSP), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), graphics processing unit (GPU), artificial intelligence processing unit (AIPU), etc. It should be understood that processor 100 can be implemented in a variety of different ways. For example, it can be implemented on a single die, multiple dies (small die, chiplet), one or more dies in a shared package, or one or more dies in multiple packages. Based on the above, some of the described blocks can be located on different dies separately, or together on two or more different dies.

[0024] IP circuit 105 is a circuit that performs a specific function. An IP circuit (or IP) can be a reusable unit of logic, circuitry, cell, or chip layout. Some examples of IP circuits include processor cores, memory, caches, floating-point processors, memory controllers, bus controllers, graphics processors, transceivers, network interface controllers, and display controllers. One or more portions of a larger IP can be designated as an IP circuit itself. For example, an instruction execution unit and a cache controller can be IPs for a processor IP. In some embodiments, one or more IP blocks may include aging monitor circuitry 102 (including aging determination and / or dynamic power supply voltage regulation), as described below, to monitor and, in certain cases, respond to transistor aging in one or more IP blocks.

[0025] The SMC 110 includes one or more microcontrollers, state machines, and / or other logic circuitry for controlling various aspects of the processor 100. For example, it can manage functions such as security, boot configuration, and power and performance (including power utilization and allocation, and thermal management). The SMC may also be referred to as a P-cell, power management unit (PMU), power control unit (PCU), system management unit (SMU), etc., and may include multiple SMCs, PMUs, die management controllers, etc.

[0026] In some embodiments, SMC 110 includes aging monitor control logic to control, monitor, and / or respond to data from aging monitor circuitry 102. Aging monitor control logic 112 can be implemented using SMC runtime code (e.g., firmware), or it can be implemented wholly or partially using dedicated control logic circuitry (e.g., a microcontroller or finite state machine (FSM)), or any other suitable combination of hardware and / or executable code.

[0027] Processing cores 115 include cores for executing code according to the desired functionality of processor 100. These can include any suitable combination of core types such as computing (e.g., CPU) cores, graphics cores, parallel processing cores, vector processing cores, etc., and can be implemented with core instances of different sizes and / or by using the same or different instruction set architectures. The specific implementation will depend on functionality and power and performance targets. One or more cores 115 may include aging monitor circuitry 102 for monitoring aging, circuit degradation, and / or dynamic voltage regulation within the core. In some embodiments, they may also be used, or alternatively, to regulate the voltage levels used to power the cores, for example, on a core-by-core or even more fine-grained partition level. Other blocks of processor 100 may also include aging monitor circuitry 102, as shown in the figure. Examples of aging monitor circuitry are given below.

[0028] Shared cache 120 includes one or more levels of cache memory, typically random access memory (RAM), used by other blocks in the processor, including processor core 115. Some or all of it may be part of an overall memory system that also includes memory module 145. I / O devices 155 and their associated I / O interfaces 130 are coupled to processor 100 to provide additional functionality and / or better performance capabilities. For example, they may include I / O interface devices such as Fast Peripheral Chip Interconnect (PCIe), Universal Serial Bus (USB), and / or Fast Compute Link (CXL) interfaces for peripheral user interface devices, displays, accelerometers, graphics cards, etc.

[0029] One or more memory controllers 125 are coupled to memory modules 145. Memory modules typically consist of DRAM memory chips, and each module may include power delivery circuitry and a memory module controller for interfacing between the raw memory and the memory controllers 125. The memory can be implemented using any suitable type, such as Double Data Rate (DDR), Low Power DDR (LPDDR), etc. Therefore, the channels constituting the memory channels operate according to any memory type being implemented.

[0030] Structure 135 is a communication network of interconnect nodes used to couple various different blocks of processor 100 to each other. In some embodiments, it facilitates high-speed data transfer and communication, which allows the creation of a unified computing system in which different components can operate collaboratively. For convenience, a single monolithic structure is shown, but structure 135 may include multiple different structures and interconnect structures, such as mesh networks and ring networks, as well as bus and point-to-point connections. In some embodiments, it may include separate, different structures, such as a main data structure for transferring data between blocks and a control structure for setting parameters, reading operating states, managing operating modes, communicating telemetry, etc. Communication for controlling and / or reading aging monitor circuitry 102 may be implemented using one or more interconnects in structure 135 or via other communication links within the processor.

[0031] Figure 2 This is a block diagram illustrating a processor with an aging monitor circuit 202 according to some embodiments. The aging monitor (AM) circuit 202 may be used in the AM circuit 102 and / or distributed in various different circuit groups 201 (e.g., cores, IP blocks, etc. to be monitored). In some embodiments, each core of the processor has at least one aging monitor circuit 202; in some cases, depending on the core size and architecture, there may be multiple AM ​​circuits.

[0032] One or more circuits 202 include a monitor management (or simply management) circuit 210, a power gate (PG) switch, a first ring oscillator (RO1) 225A, a second ring oscillator (RO2) 225B, a third ring oscillator (RO3) 225C, and associated counters (230A-230C) coupled together as shown. RO1 and RO2 are used to determine the aging condition of the monitored circuit group 201, while RO1 and RO3 are used to identify the temperature (T), and in some cases, the voltage (V), for aging determination. Therefore, RO1 and RO3 are kept "fresh," i.e., energized when used for aging and / or temperature determination, and otherwise kept de-energized. On the other hand, RO2 is allowed to age along with the monitored circuit. Thus, RO1 and RO3 are coupled to the power supply voltage (Vcc) of the monitored circuit group through the power gate (PG) controlled by the management circuit 210, while the oscillator RO2 is coupled to the power supply voltage (Vcc) of the monitored circuit. The power supply voltage (Vcc) is the power source used to power the circuitry within the partition to be monitored (e.g., core, IP, etc.). RO2 will operate in conjunction with these circuits. Therefore, although it is shown as being directly connected to Vcc, it should be understood that it can be connected to any rail, power gate, or other dummy power source that can also be used to power the monitored circuitry. That is, in some embodiments, it will be subject to the same constraints as the monitored circuitry. Based on these principles, the RO circuitry itself should be manufactured using the same process as the monitored circuitry and should also be located sufficiently close, or even within, that circuitry.

[0033] An exemplary ring oscillator circuit 225 is shown in the dashed box. It includes N inverters (e.g., P / N MOS inverters) coupled together as shown in a ring oscillator configuration (e.g., with an odd number of inverter stages). (As used herein, a P / N inverter is an inverter formed by P-type and N-type transistors, whose gates are coupled to each other and whose drains are also coupled to each other.) In some embodiments, the ring oscillator may use a relatively large number (e.g., 21 or more) of individual inverters to provide a larger sample size, thereby better averaging out significant inverter deviations from design parameters. (Note that while a ring oscillator circuit is shown, any suitable oscillator design can be used, as long as its transistor aging can be monitored according to the techniques described herein.) The monitor management circuit 210 manages the operation of the ring oscillator to determine the aging condition of one or more monitored circuits. It can be implemented with any suitable circuit, such as a microcontroller, one or more state machines, a combination thereof, or even other controllers, such as a central monitor management control circuit, an SMC, and / or software running in the processor (such as control code, drivers, or BIOS software).

[0034] The depicted management circuitry 210 includes logic for implementing aging monitoring routine 212 and / or logic for implementing V / F (voltage / frequency) regulation routine 214. Management circuitry 210 also includes a memory comprising a status / control register 216 for storing various parameters, such as aging values, operational control information, etc. The management circuitry may also include tables and / or arithmetic information corresponding to the modeling or test voltages, temperatures, and aging parameters of the monitored circuit(s) to determine aging information for circuits using a ring oscillator. This table and / or arithmetic information may alternatively be stored externally to the aging monitor, such as in the central management control logic 112 or elsewhere.

[0035] In some embodiments, the oscillators are implemented with the same circuit configuration, except that the first and second oscillators (RO1, RO2) use transistors with the same voltage threshold (Vt1), while the third oscillator (RO3) uses a transistor with a different threshold (Vt2). Because different thresholds are used to determine the temperature, in some embodiments, the widest available spacing can be used to select the Vt1 and Vt2 thresholds.

[0036] In operation, the first and third ring oscillators RO1 (Vt1) and RO3 (Vt2) are used to determine instantaneous voltage and temperature. This can be achieved by generating lookup tables and / or curves through pre-characterization and simulation of the ring oscillators. Using a similar method, RO1 and RO2 are used to determine aging values. For either measurement, counter 230 is used to measure the oscillator frequency. When a frequency measurement is to be performed, the management circuit controls the counter to reset, start counting, and then stop counting after a known set amount of time. A faster oscillator (lower aging or lower Vt) will have a higher count. Thus, the frequency can be determined, or the count itself can be used without converting it to the actual frequency.

[0037] Since RO1 and RO3 have different voltage thresholds but are otherwise identical, they can be used to determine the temperature and voltage by essentially (or effectively) reading them simultaneously at the same frequency and extracting their temperature and voltage from a lookup / arithmetic model generated using the following two linear relationships: F1 = aV + bT (1) F3 = cV + dT (1) Where F1 is the frequency of RO1, F3 is the frequency of RO3, V is the voltage applied to each oscillator, and T is their temperature. The coefficients a, b, c, and d can be determined by testing, modeling, and / or simulating oscillators at different operating points. This can be done during pre-silicon simulation and / or post-silicon characterization and calibration. The generated data can then be stored in a lookup table or fitted into a formula, from which V and T, or even just T, can be determined based on measurements of F1 and F3. (Note that in some embodiments, the oscillator voltage can be identified from a known Vcc applied value, but in other embodiments, a more accurate voltage value can be derived from the frequency measurements and the generated oscillator F / V / T relationship.) Then, RO1 and RO2 can be used to determine aging values, such as aging time, which can be normalized relative to the expected aging time as a function of the actual degradation.

[0038] Similarly, RO1 and RO2 are identical in transistor type and layout, and are located close to each other. The difference between them is that RO1 is new and is usually not connected to the power supply; while RO2 is old and is continuously connected to the power supply and the circuitry it monitors.

[0039] Aside from the different mathematical relationships, a method similar to the one described earlier for determining V and T from RO1 and RO3 can also be used for aging determination. For aging, the aging condition of the actual circuit / transistor type is compared to its expected normal aging condition; the effective aging condition is as follows: Where A(T,V) is a second-order polynomial estimate of the voltage, and the A and B polynomial parameters are linear estimates of the temperature using fixed coefficient values ​​derived by modeling the circuit at a series of operating points and temperatures. F1 is the frequency of RO1, F2 is the frequency of RO2, and the degradation degree is (F1-F2) / F1. Therefore, it can be seen that, given a voltage and temperature, an estimate of the number of years of degradation under specific stress and silicon sensitivity can be generated based on the degree of RO frequency degradation. Different stresses and materials may produce the same effect, but this value can at least be used as a reference. Note that in some embodiments, circuitry other than the oscillator can be used to measure the delay, which can be applied as the reciprocal of the frequency.

[0040] By using pre-silicon modeling and / or simulation and / or post-silicon characterization and / or calibration, lookup tables and / or formulas can be generated using the relationship between voltage, temperature, and RO frequency of a similar aged oscillator and a fresh test oscillator. These can then be used later with an operating AM circuit to determine the effective aging of the monitored circuit.

[0041] Figure 3 This is a hybrid flowchart illustrating an aging monitoring routine according to some embodiments. For example, this routine can be used... Figure 2 The circuitry. In some embodiments, this routine for determining a valid aging value can be executed in response to a specific request, such as from the OS, BIOS, or security agent, or it can be executed at a regular rhythm, such as from once per hour to once per day. The results can then be stored in the management circuitry or elsewhere in a more centralized location. The aging value can be stored in non-volatile memory, although this is not necessary, as it can be determined as a new value at any desired time.

[0042] When determining the aging value, power is switched on to RO1 and RO3 so that all three oscillators are running. The frequencies of RO1, RO2, and RO3 are measured together at points 302, 304, and 306. At point 308, voltage and temperature are identified, for example, using the technique described above. Next, at point 310, the effective aging value is determined using T, V, and the F2 / F1 ratio. Once the parameters required for determining the aging value are identified, power is switched off to RO1 and RO3 to keep them in a fresh and reasonably achievable state.

[0043] At 312, the routine checks whether the determined aging value is abnormal, for example, problematic or actionable. If so, at 314, actions are taken such as triggering an alarm or shifting operation from the circuit (e.g., the core) to another circuit block with less aging. Finally, at 316, it updates the voltage level at the frequency operating point (i.e., the V / F curve of the monitored circuit in question) based on the new aging value. If aging is determined to be normal or at least without other problems at 312, it proceeds directly to block 316. From there, it continues to 318, essentially waiting for the next aging determination event to occur.

[0044] Figure 4 This is a block diagram illustrating an aging monitor circuit 402 for monitoring circuit 401 according to some embodiments. This circuit is similar to... Figure 2 The circuit differs in that it uses a single temperature sensor 435 instead of two oscillators to measure temperature. Therefore, this aging test only requires two oscillators, RO1 and RO2. Any suitable temperature sensor circuit (e.g., a digital temperature sensor (DTS)) can be used for the temperature sensor 435.

[0045] Using this aging monitor circuit, as described above, the voltage can be extracted using RO1, based on the known temperature from temperature sensor 435 and the frequency of the fresh oscillator (RO1). Furthermore, by knowing the temperature and voltage, the aging value can be determined using the fresh frequency from fresh RO1 and the "aging" frequency from aging RO2. In some applications where a self-contained aging sensor is desired, i.e., where a usable temperature sensor is not required, Figure 2 Such embodiments may be preferred. On the other hand, where a temperature circuit is readily available, Figure 4 The embodiments described may be preferred.

[0046] Figure 5 This is a flowchart illustrating another routine for monitoring aging, according to some embodiments. This routine is similar to... Figure 3 The routine differs in that the temperature is derived from a temperature sensor 435, rather than relying on a third oscillator. In some embodiments, this routine for determining a valid aging value can be executed in response to a specific request, such as from the OS, BIOS, or security agent, or it can be executed at a regular rhythm, such as from once per hour to once per day. The results can then be stored in management circuitry or elsewhere, for example, in a more centralized location. The aging value can be stored in non-volatile memory, although this is not necessary, as it can be determined as a new value at any desired time.

[0047] When aging determination is to be performed, power is switched on RO1, causing RO1 and RO2 to start operating. Temperature is detected at 502 from temperature sensor 435, frequencies F1 and F2 of RO1 and RO2 are measured together at 504 and 506, and their ratio is identified at 510. At 508, voltage is identified, for example, by extracting temperature information from RO1 or simply by knowing the programmed power supply voltage, using the techniques described above.

[0048] Next, at 512, the effective aging value is determined using T, V, and the F2 / F1 (or F1 / F2) ratio. Once the parameters needed to determine the aging value are identified, the power supply to RO1 is removed to keep it in a fresh state that can be reasonably achieved.

[0049] At 514, the routine checks whether the determined aging value is abnormal, for example, problematic or intervention-prone. If so, at 516, it takes actions such as triggering an alarm or shifting operation from the circuit (e.g., the core) to another circuit block with less aging. Finally, at 518, it updates the voltage level at the frequency operating point (i.e., the V / F curve of the monitored circuit in question) based on the new aging value. If aging is determined to be normal or at least without other problems at 312, it proceeds directly to block 316. From there, it continues to 520, essentially waiting for the next aging determination event to occur.

[0050] refer to Figure 6A , 6B 7A, 7B, and a scheme for dynamically updating the processor power supply voltage based on aging conditions according to some embodiments will now be described. Figure 6A This is a block diagram illustrating a dynamic voltage regulation circuit 602 for regulating the power supply voltage of a monitored circuit 601 according to some embodiments. Figure 6B This is a flowchart illustrating a routine for dynamically adjusting the power supply voltage. Figure 7A This is a graph showing the voltage required to maintain operational performance. Figure 7B It is a graph showing the relationship between the operating frequency of a circuit and the voltage required to reach that frequency as the circuit ages.

[0051] Digital CMOS (Complementary Metal-Oxide-Semiconductor) logic typically operates at high voltages and temperatures to achieve performance, but prolonged operation under these conditions alters transistor parameters, leading to speed degradation. If not compensated for with appropriate voltage increases, this speed degradation can eventually cause cell malfunctions.

[0052] The specific speed degradation of a given circuit depends on voltage and temperature, and on operating conditions (e.g., operating load, voltage waveform, duration, etc.), making each chip's speed degradation different. For conventional platforms, the traditional method to prevent cell failure due to speed degradation is to apply a flat overvoltage (voltage protection band) to compensate for expected speed degradation at the end of the product's lifespan. However, applying a worse-case overvoltage protection band inevitably leads to higher power consumption, lower performance, and greater degradation.

[0053] Therefore, in some embodiments, novel methods are provided. For example, in some embodiments, it is not necessary to measure speed degradation, but at the same time, the voltage can be gradually increased over time according to the measured performance to keep the circuit in a reasonably fresh operating state. In some embodiments, fresh and aged ring oscillators (e.g., RO1, RO2 from 202 or 402) are used, without the need for stored parameters (e.g., in fuses, etc.).

[0054] It has been observed that while speed degradation depends largely on temperature and voltage, the voltage offset leading to speed recovery is primarily voltage-dependent. This observation allows for schemes that can neglect temperature or temperature control. Avoiding high-voltage protection belts from the outset not only helps prevent power waste but also reduces stress under high voltage, thus enabling longer runs without the need for protection belts.

[0055] refer to Figure 6A Dynamic voltage regulation circuit and Figure 2 and Figure 4 The monitor circuit is similar, except that it does not need to include circuitry for measuring temperature, but it does include circuitry for managing circuitry 610 to switch the aging oscillator (RO2) between the monitored circuit power supply (Vcc) and the controllable voltage power supply 624. A multiplexer-type switch 622 is used for this purpose. Typically, the aging oscillator (RO2) is powered by the Vcc power supply, such as... Figure 2 and Figure 4 The aging oscillator shown is used, but when voltage regulation is required, the power supply switches to a controllable voltage of 624.

[0056] Now will be presented Figure 6B The voltage regulation routine is as follows: At 652, a fresh oscillator (e.g., RO1) is coupled to the power supply Vcc (the power supply of the monitored circuit). At 654, the frequency (F1) of the fresh oscillator (RO1) is measured, for example, by counting the cycles over a known time interval. At 656, an aged oscillator (e.g., RO2) is coupled to a controllable power supply voltage. At 658, the frequency (F2) of the aged oscillator (RO2) is measured (e.g., counted) over a period of time. Note that although these steps are presented as different, separate sequential steps, in some embodiments, they are related to... Figure 3 and Figure 5 Similar to some methods, frequencies (F1, F2) can be measured together, for example, by applying a shared enable / disable signal to the counters of two cooperating oscillators through a management circuit.

[0057] At 660, the routine determines whether the aging frequency (F2) is greater than or equal to the frequency of the fresh oscillator (RO1). If not, at 662, the controllable supply voltage is increased and the loop returns to 658. For example, a relatively small increment (such as 5 to 10 mV) can be used to increase the voltage. The routine continues this loop until it is determined at 660 that F2 is greater than or equal to F1. Once this occurs, the routine continues to 614 and identifies and / or stores the amount of voltage increase required to reach this point (i.e., F2 becomes greater than or equal to F1). Then, at 616, the routine updates the relevant VF curve.

[0058] It is worth noting that voltage regulators can cause ripple in the supply voltage, which may temporarily alter the oscillator speed. One way to address this is to make the frequency counting duration long enough to overcome the ripple effects and localized drops caused by sudden increases in current. Based on these principles, for each frequency determined, multiple measurements can be taken and then averaged or at least confirmed to be consistent with each other.

[0059] Furthermore, measurements of fresh and aged oscillators can be performed and / or compared at different times, thus potentially affected by load variations during the test period. This is because the voltage is set at VR, and varying loads during the test can alter the actual voltage, for example, due to the IR drop on the oscillator between fresh and aged oscillator tests at different voltages (and also at different times). One approach to address this is to ensure no load variation during the test by performing measurements during a forced idle period (e.g., idle C state or during reset). If the normal operating time is long (without state changes), testing can also be forced using an idle mode. Another approach could be to allow testing during normal operation, but repeat the reference and test several times, raising and lowering the controlled voltage to obtain consistent results, verifying that the average load does not change during voltage offsets.

[0060] Another issue is oscillator variation. Variation between oscillators can lead to incorrect aging measurements, and when a fresh oscillator is slower than an aged oscillator from the start, it can cause adjustment delays.

[0061] Figure 8The figure illustrates an example computing system including one or more aging monitors and / or voltage regulation circuitry according to some embodiments. The multiprocessor system 800 is an interface system including multiple processors, including a first processor 870 and a second processor 880 coupled via an interface 850 (such as a point-to-point (PP) interconnect, architecture, and / or bus). In some examples, the first processor 870 and the second processor 880 are homogeneous. In some examples, the first processor 870 and the second processor 880 are heterogeneous. While the example system 800 is shown as having two processors, the system may have three or more processors, or it may be a single-processor system. In some examples, the computing system is implemented wholly or partially using a system-on-a-chip (SoC) or multi-chip (or multi-chiplet) module in the same or different package combinations.

[0062] Processors 870 and 880 are shown as including integrated memory controller (IMC) circuitry 872 and 882, respectively. Processor 870 also includes interface circuitry 876 and 878, as well as a core set. Similarly, the second processor 880 includes interface circuitry 886 and 888, as well as a core set. A core set typically refers to one or more computing cores that may or may not be grouped into different clusters, hierarchical groups, or groups of common core types. Cores may be configured differently to execute different functions and / or instructions at different performance and / or power levels. Processors may also include other blocks, such as memory and other processing unit engines.

[0063] Processors 870 and 880 can exchange information via interface 850 using interface circuits 878 and 888. IMC 872 and 882 couple processors 870 and 880 to corresponding memories, namely memories 832 and 834, which may be portions of the main memory locally attached to the corresponding processor.

[0064] Processors 870 and 880 can each exchange information with network interface (NW I / F) 890 via corresponding interfaces 852 and 854 using interface circuits 876, 894, 886, and 898, respectively. Network interface 890 (e.g., one or more of interconnects, buses, and / or structures, in some examples a chipset) can optionally exchange information with coprocessor 838 via interface circuit 892. In some examples, coprocessor 838 is a dedicated processor, such as a high-throughput processor, network or communication processor, compression engine, graphics processor, general-purpose graphics processing unit (GPGPU), neural network processing unit (NPU), embedded processor, etc.

[0065] A shared cache (not shown) may be included in or outside of processors 870, 880, but connected to the processors via an interface such as PP interconnect, such that if the processors are in a low-power mode, the local cache information of one or both processors can be stored in the shared cache.

[0066] Network interface 890 may be coupled to first interface 816 via interface circuitry 896. In some examples, first interface 816 may be an interface such as a Peripheral Component Interconnect (PCI) interconnect, PCI Fast Interconnect, or other I / O interconnect. In some examples, first interface 816 is coupled to power control unit (PCU) 817, which may include circuitry, software, and / or firmware to perform power management operations with respect to processors 870, 880, and / or coprocessor 838. PCU 817 provides control information to one or more voltage regulators (not shown) to cause the voltage regulator(s) to generate appropriate one or more regulated voltages. PCU 817 also provides control information to control the generated operating voltage. In various examples, PCU 817 may include various power management logic units (circuitry) to perform hardware-based power management. This power management may be entirely processor-controlled (e.g., controlled by various processor hardware and may be triggered by operating load and / or power, thermal, or other processor constraints) and / or may be performed in response to external sources such as platform or power management sources or system software.

[0067] The PCU 817 is shown as logic separate from the processor 870 and / or processor 880. In other cases, the PCU 817 may execute on one or more cores (not shown) of the processor 870 or 880. In some cases, the PCU 817 may be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code (sometimes called P-code). In another example, the power management operations performed by the PCU 817 may be implemented outside the processor, for example, through a separate power management integrated circuit (PMIC) or another component outside the processor. In yet another example, the power management operations performed by the PCU 817 may be implemented within the BIOS or other system software. Based on these principles, power management can be performed collaboratively with other autonomous or semi-autonomous power control units (e.g., as execution software in controllers or cores, clusters, IP blocks, and / or other parts of the system).

[0068] Various I / O devices 814 can be coupled to a first interface 816 along with a bus bridge 818, which in turn couples the first interface 816 to a second interface 820. In some examples, one or more additional processors 815, such as coprocessors, high-throughput multi-core (MIC) processors, GPGPUs, accelerators (such as graphics accelerators or digital signal processing (DSP) units), field-programmable gate arrays (FPGAs), or any other processors, are coupled to the first interface 816. In some examples, the second interface 820 may be a low pin count (LPC) interface. Various devices can be coupled to the second interface 820, including, for example, a keyboard and / or mouse 822, a communication device 827, and storage circuitry 828. Storage circuitry 828 may be one or more non-transient machine-readable storage media as described below, such as disk drives or other mass storage devices (which may include instructions / code and data 830, and in some examples may implement storage). Additionally, audio I / O 824 may be coupled to the second interface 820. Note that other architectures besides the point-to-point architecture described above are also possible. For example, instead of a point-to-point architecture, systems such as the multiprocessor system 800 can implement multipoint interfaces or other such architectures.

[0069] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) general-purpose ordered cores for general-purpose computing; 2) high-performance general-purpose out-of-order cores for general-purpose computing; and 3) dedicated cores primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) CPUs comprising one or more general-purpose ordered cores for general-purpose computing and / or one or more general-purpose out-of-order cores for general-purpose computing; and 2) coprocessors comprising one or more dedicated cores primarily for graphics and / or scientific (throughput) computing. Such different processors result in different computer system architectures, which may include: 1) coprocessors located on a separate chip relative to the CPU; 2) coprocessors and CPUs located on separate dies within the same package; 3) coprocessors and CPUs located on the same die (in which case, such coprocessors are sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or dedicated cores); and 4) system-on-a-chip (SoCs) that may be included on the same die as the CPU (sometimes referred to as application cores or application processors), the aforementioned coprocessors, and additional functionality. The example core architecture is described next, followed by the example processor and computer architecture.

[0070] Figure 9The diagram illustrates a block diagram of an example processor and / or SoC 900 according to some embodiments, which may have one or more cores and an integrated memory controller, and may include an aging monitor and / or voltage regulation circuitry. Solid-line boxes illustrate a processor and / or SoC 900 having a single core 902(A), system proxy unit circuitry 910, and a set of one or more interface controller unit circuits 916, while optional additions in dashed-line boxes illustrate another processor and / or SoC 900 having multiple cores 902(A)-(N), a set of one or more integrated memory controller unit circuits 914 in the system proxy unit circuitry 910, dedicated logic 908, and a set of one or more interface controller unit circuits 916. Note that the processor and / or SoC 900 may be… Figure 8 One of the processors 870 or 880 or the coprocessor 838 or 815.

[0071] Therefore, different implementations of the processor and / or SoC 900 may include: 1) a CPU having dedicated logic 908 and cores 902(A)-(N), wherein the dedicated logic 908 is a high-throughput processor, network or communication processor, compression engine, graphics processor, general-purpose graphics processing unit (GPGPU), neural network processing unit (NPU), embedded processor, security processor, matrix accelerator, memory analysis accelerator, compression accelerator, dataflow accelerator, data graph operations, etc. (which may include one or more cores, not shown), and cores 902(A)-(N) are one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose out-of-order cores, or a combination thereof); 2) coprocessors having cores 902(A)-(N), which are a large number of dedicated cores primarily used for graphics and / or scientific (throughput); and 3) coprocessors having cores 902(A)-(N), which are a large number of general-purpose ordered cores. Therefore, the processor and / or SoC 900 can be a general-purpose processor, coprocessor, or dedicated processor, such as a network or communication processor, compression engine, graphics processor, GPGPU (General Purpose Graphics Processing Unit), high-throughput multi-core (MIC) coprocessor (including 30 or more cores), embedded processor, etc. The processor can be implemented on one or more chips. The processor and / or SoC 900 can be part of one or more substrates using any of a variety of process technologies and / or can be implemented on one or more substrates, such as complementary metal-oxide-semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal-oxide-semiconductor (PMOS), and N-type metal-oxide-semiconductor (NMOS).

[0072] The memory hierarchy includes one or more levels of cache cell circuitry 904(A) / (N) within cores 902(A)-(N), a set of one or more shared cache cell circuitry 906, and external memory (not shown) coupled to the set of integrated memory controller cell circuitry 914. The set of one or more shared cache cell circuitry 906 may include one or more intermediate caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache (e.g., last-level cache (LLC)), and / or combinations thereof. While in some examples, interface network circuitry 912 (e.g., a ring interconnect) interfaces with dedicated logic 908 (e.g., integrated graphics logic), the set of shared cache cell circuitry 906, and system agent cell circuitry 910, alternative examples use any number of known techniques to interface these cells. In some examples, consistency is maintained between the one or more shared cache cell circuitry 906 and cores 902(A)-(N). In some examples, the interface controller unit circuit 916 couples the core 902(A)-(N) to one or more other devices 918, such as one or more I / O devices, storage devices, one or more communication devices (e.g., wireless networks, wired networks, etc.).

[0073] In some examples, one or more of the cores 902(A)-(N) are capable of multi-threaded processing. The system agent unit circuitry 910 includes those components that coordinate and operate the cores 902(A)-(N). The system agent unit circuitry 910 may include, for example, power control unit (PCU) circuitry and / or display unit circuitry (not shown). The PCU may be, or may include, the logic and components required for regulating the power state of the cores 902(A)-(N) and / or dedicated logic 908 (e.g., integrated graphics logic). The display unit circuitry is used to drive one or more externally connected displays.

[0074] Cores 902(A)-(N) can be homogeneous in terms of instruction set architecture (ISA). Alternatively, cores 902(A)-(N) can be heterogeneous in terms of ISA; that is, a subset of cores 902(A)-(N) may be able to execute an ISA, while other cores may only be able to execute that ISA or a subset of another ISA.

[0075] BPC—System with PP Figure 10This is a block diagram illustrating a computing system 1000 configured to implement one or more aspects of the examples described herein. The computing system 1000 includes a processing subsystem 1001 and a system memory 1004. The processing subsystem 1001 has one or more processors 1002. The system memory 1004 communicates via an interconnect path, which may include a memory hub 1005. The memory hub 1005 may be a separate component within a chipset assembly or integrated within one or more processors 1002. The memory hub 1005 is coupled to an I / O subsystem 1011 via a communication link 1006. The I / O subsystem 1011 includes an I / O hub 1007 that enables the computing system 1000 to receive input from one or more input devices 1008. Furthermore, the I / O hub 1007 enables a display controller, which may be included in one or more processors 1002, to provide output to one or more display devices 1010A. In some examples, one or more display devices 1010A coupled to I / O hub 1007 may include local, internal, or embedded display devices.

[0076] For example, processing subsystem 1001 includes one or more parallel processors 1012 coupled to memory hub 1005 via a bus or communication link 1013. Communication link 1013 can be any number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Fast, or it can be a vendor-specific communication interface or communication architecture. The one or more parallel processors 1012 can form a computation-centric parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as multi-integrated core (MIC) processors. For example, the one or more parallel processors 1012 form a graphics processing subsystem that can output pixels to one of one or more display devices 1010A coupled via I / O hub 1007. The one or more parallel processors 1012 may also include a display controller and display interface (not shown) for direct connection to one or more display devices 1010B.

[0077] Within the I / O subsystem 1011, system storage unit 1014 can be connected to I / O hub 1007 to provide storage for computing system 1000. I / O switch 1016 can be used to provide an interface mechanism to enable connectivity between I / O hub 1007 and other components (e.g., network adapter 1018 and / or wireless network adapter 1019 that can be integrated into the platform, and various other devices that can be added via one or more add-on devices 1020). Add-on devices 1020 may also include, for example, one or more external graphics processing units, graphics cards, and / or computing accelerators. Network adapter 1018 can be an Ethernet adapter or another wired network adapter. Wireless network adapter 1019 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0078] The computing system 1000 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 1007. Figure 10 The communication paths for interconnecting various components can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI Express), or any other bus or point-to-point communication interface and / or protocol, such as NVLink high-speed interconnect, Compute Express Link™ (CXL™) (e.g., CXL.mem), Infinity Fabric (IF), Ethernet (IEEE 802.3), Remote Direct Memory Access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Fast UDP Internet Connection (QUIC), RDMA over Converged Ethernet (RoCE), Intel Quick Path Interconnect (QPI), Intel Ultra Path Interconnect (UPI), Intel System-on-Chip Architecture (IOSF), Omnipath, HyperTransport, Advanced Microcontroller Bus Architecture (AMBA) Interconnect, OpenCAPI, Gen-Z, Accelerator Cache Coherent Interconnect (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G and its variants, or wired or wireless interconnect protocols known in the art. In some examples, data can be copied or stored to virtualized storage nodes using protocols such as Non-Volatile Memory Fast (NVMe) on Fabric (NVMe-oF) or NVMe.

[0079] One or more parallel processors 1012 may include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). Alternatively or additionally, one or more parallel processors 1012 may include circuitry optimized for general-purpose processing while retaining the underlying computing architecture described in more detail herein. Components of the computing system 1000 may be integrated with one or more other system elements on a single integrated circuit. For example, the parallel processor(s), memory hub(s), processor(s), and I / O hub(s) 1007 may be integrated into a system-on-a-chip (SoC) integrated circuit. Alternatively, components of the computing system 1000 may be integrated into a single package to form a system-in-package (SIP) configuration. In some examples, at least a portion of the components of the computing system 1000 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computing system.

[0080] It should be understood that the computing system 1000 shown herein is illustrative, and variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processors 1002, and the number of parallel processors 1012, can be modified as needed. For example, system memory 1004 may be connected directly to processor(s) 1002 instead of via a bridge, while other devices communicate with system memory 1004 via memory hub 1005 and processor(s) 1002. In other alternative topologies, parallel processor(s) 1012 may be connected to I / O hub 1007 or directly to one of the processors 1002, instead of to memory hub 1005. In other examples, I / O hub 1007 and memory hub 1005 may be integrated into a single chip. It is also possible that two or more sets of processors 1002 are connected via multiple sockets, which can couple to two or more instances of parallel processor(s) 1012.

[0081] Some specific components shown in this article are optional and may not be included in all implementations of the computing system 1000. For example, any number of additional cards or peripherals may be supported, or certain components may be eliminated. Furthermore, some architectures may be adapted to... Figure 10 The components shown are similar to those described using different terminology. For example, in some architectures, the memory hub 1005 may be referred to as the Northbridge, while the I / O hub 1007 may be referred to as the Southbridge.

[0082] Illustrative examples of the techniques disclosed herein are provided below. Embodiments of these techniques may include any one or more of the examples described below, as well as any compatible combinations.

[0083] Example 1 is an apparatus including a circuit group, a management circuit, a first oscillator, and a second oscillator. The circuit group is coupled to a power supply voltage node. The first oscillator includes a first power supply node coupled to the power supply voltage node via a switch controlled by the management circuit. The second oscillator is coupled to the power supply voltage node along with the circuit group.

[0084] Example 2 includes the subject of Example 1, and wherein the first oscillator and the second oscillator are ring oscillators.

[0085] Example 3 includes the subject of any one of Examples 1 to 2, and includes a first counter coupled to a first oscillator and a second counter coupled to a second oscillator, the first and second counters being controllable by management circuitry.

[0086] Example 4 includes the subject of any one of Examples 1 to 3, and includes a temperature sensing circuit coupled to the management circuit.

[0087] Example 5 includes the subject of any one of Examples 1 to 4, and wherein the temperature sensing circuit is formed by a first oscillator and a third oscillator, the third oscillator including a third power node coupled to the first power node.

[0088] Example 6 includes the subject of any one of Examples 1 to 5, and wherein the temperature sensing circuit is a digital temperature sensor circuit.

[0089] Example 7 includes the subject of any one of Examples 1 to 6, and wherein the management circuitry includes a lookup table with parameters to identify aging values ​​of the circuit group based on measured frequencies from the first oscillator and the second oscillator.

[0090] Example 8 includes the subject of any one of Examples 1 to 7, and wherein the management circuitry includes mathematical functions to generate aging values ​​for the circuitry based on measured frequencies from the first and second oscillators.

[0091] Example 9 includes the subject of any one of Examples 1 to 8 and includes multiple processing cores, each of which includes a first oscillator and a second oscillator to determine the aging value of the core.

[0092] Example 10 includes the subject of any one of Examples 1 to 9, wherein the first oscillator and the second oscillator are formed using the same circuit design and include more than 20 sequentially coupled inverters.

[0093] Example 11 is an apparatus including a circuit group, management circuitry, a first oscillator, a second oscillator, and a multiplexer switch. The circuit group is coupled to a power supply voltage node. The first oscillator includes a first power supply node coupled to the power supply voltage node via a power gate controlled by the management circuitry. The second oscillator includes a second power supply node. The multiplexer switch includes: (i) a multiplexer switch output node coupled to the second power supply node, (ii) a first multiplexer switch input coupled to the power supply voltage node, and (iii) a second multiplexer switch input coupled to a variable voltage source controllable by the management circuitry.

[0094] Example 12 includes the subject of Example 11, and wherein the first oscillator and the second oscillator are ring oscillators.

[0095] Example 13 includes the subject of any one of Examples 11 to 12 and includes a first counter coupled to a first oscillator and a second counter coupled to a second oscillator, the first and second counters being controllable by management circuitry.

[0096] Example 14 includes the subject of any one of Examples 11 to 13, and wherein the management circuitry has logic to increase the variable voltage source until the frequency of the second oscillator is greater than or equal to the frequency of the first oscillator.

[0097] Example 15 includes the subject of any one of Examples 11 to 14, where logic is used to adjust the voltage / frequency operating point of a circuit group based on the amount of voltage increase from a variable voltage source.

[0098] Example 16 includes the subject of any one of Examples 11 to 15 and includes multiple processing cores, each processing core including a first oscillator and a second oscillator to determine the operating point voltage increase of the core.

[0099] Example 17 is a non-transient computer-readable storage medium having instructions for executing a method at execution. The method includes measuring a first frequency from a first oscillator. It also includes measuring a second frequency from a second oscillator configured identically to the first oscillator, the second oscillator being powered together with a group of circuits to be monitored. It further includes removing power from the first oscillator when the first frequency is not being measured. It also includes determining an aging value for the circuit group based on the first and second frequencies.

[0100] Example 18 includes the subject of Example 17 and includes identifying the temperature and voltage of the first and second oscillators when measuring the first and second frequencies.

[0101] Example 19 includes the subject of any one of Examples 17 to 18, and wherein a third oscillator with a transistor having a different voltage threshold than the first oscillator is used to identify the temperature.

[0102] Example 20 includes the subject of any one of Examples 17 to 19, and in which a third oscillator is used to identify the voltage.

[0103] Example 21 includes the subject of any one of Examples 17 to 20, and in which voltage is identified from power supply voltage control code.

[0104] Example 22 includes the subject of any one of Examples 17 to 21, and in which a temperature sensor is used to identify the temperature.

[0105] Example 23 is a system that includes a processor with a storage medium comprising the subject of any one of Examples 17 to 22, and it also includes memory coupled to the processor.

[0106] The terms "embodiment," "one embodiment," "some embodiments," or "other embodiments" used in this specification refer to specific features, structures, or characteristics described in connection with an embodiment that are included in at least some embodiments, but not necessarily in all embodiments. Various appearances of "embodiment," "one embodiment," or "some embodiments" do not necessarily refer to the same embodiment. If the specification specifies that a component, feature, structure, or characteristic "may," "may," or "can" be included, then it is not necessary to include that particular component, feature, structure, or characteristic.

[0107] Throughout the specification and claims, the term "connection" refers to a direct connection between connected things, such as an electrical, mechanical, or magnetic connection, without the need for any intermediate devices.

[0108] The term "coupling" refers to a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection or indirect connection between things connected through one or more passive or active intermediate devices.

[0109] The terms "circuit" or "module" can refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. It should be understood that different circuits or modules can consist of individual components, which may include different and shared components, or they may consist of the same components. For example, a controller circuit can be a first circuit for performing a first function, while it can be a second controller circuit for performing a second function that is related to or unrelated to the first function.

[0110] Unless explicitly distinguished in the specific description, "in" means both "in" and "on".

[0111] Unless otherwise stated, the terms “substantially,” “close to,” “approximately,” “near,” and “about” generally refer to within + / -10% of the target value.

[0112] Unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” and “third” to describe a common object merely indicates that different instances of similar objects are being referred to, and does not mean that the objects being described must be in a given order, whether in time, space, ranking, or any other way.

[0113] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” refer to (A), (B), or (A and B). For the purposes of this disclosure, the phrases “A, B, and / or C” refer to (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).”

[0114] It should be noted that elements in a figure that have the same reference numerals (or names) as elements in any other figure can operate or function in any manner similar to those described, but are not limited thereto.

[0115] For the purposes of this embodiment, unless otherwise explicitly described, the transistors in the various circuits and logic blocks described herein may be implemented using any suitable transistor type, such as field-effect transistors (FETs) or bipolar transistors. FET transistor types may include, but are not limited to, metal-oxide-semiconductor (MOS) FETs, such as tri-gate, FinFET, and gate-all-around (GAA) FET transistors, as well as tunnel FET (TFET) transistors and ferroelectric FET (FeFET) transistors.

[0116] In the accompanying drawings of the embodiments, signals are represented by lines. For ease of understanding, some lines may appear different from others, for example, thicker or shaded, to distinguish them from other depicted signals. Along these lines, one or more ends of some signal lines may have arrows to indicate the primary direction of information flow. However, these indications are not intended to be limiting. Rather, the lines are used in conjunction with one or more exemplary embodiments in the given figures to facilitate a more readily understood understanding of the concepts embodied in the block diagrams, circuit diagrams, and / or flowcharts. Depending on design requirements or preferences, any represented signal may actually include one or more signals that can propagate in either direction and can be implemented on the platform implementing this disclosure using any suitable type of signaling scheme, such as analog, digital, wired, or wireless.

[0117] As defined herein, the term "computer-readable storage medium" means a storage medium that contains or stores program code for use in or related to an instruction execution system, apparatus, or device. As defined herein, a "computer-readable storage medium" is not itself a transient propagating signal. A computer-readable storage medium can be, but is not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. As described herein, storage elements are examples of computer-readable storage media.

[0118] As defined herein, the term "processor" refers to at least one piece of hardware circuitry configured to execute instructions contained in program code. This hardware circuitry can be implemented using one or more integrated circuits. Examples of processors include, but are not limited to, central processing units (CPUs), array processors, vector processors, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic arrays (PLAs), application-specific integrated circuits (ASICs), programmable logic circuits, graphics processing units (GPUs), controllers, etc. It should be understood that, on the other hand, a logic processor is a processing abstraction associated with a core; for example, when using one or more SMT cores, multiple logic processors can be associated with a given core, such as in the context of core thread allocation.

[0119] It should be understood that processors or processor systems can be implemented in a variety of different ways. For example, they can be implemented on a single die, multiple dies (small dies, chiplets), one or more dies in a shared package, or one or more dies in multiple packages. Based on these principles, some of these blocks can be located individually on different dies, or they can be located together on two or more different dies.

[0120] Although the flowcharts in the figures show a specific order of operations performed in some embodiments, it should be understood that such order is exemplary (e.g., alternative embodiments may perform operations in a different order, combine some operations, overlap some operations, etc.).

[0121] Although described with reference to several embodiments, those skilled in the art will recognize that this disclosure is not limited to the described embodiments and that modifications and variations may be made within the spirit and scope of the appended claims. Therefore, this description should be considered illustrative rather than restrictive.

Claims

1. An apparatus comprising: The circuit group is coupled to the power supply voltage node; Management circuits; The first oscillator includes a first power node coupled to the power supply voltage node via a switch controlled by the management circuit. as well as The second oscillator is coupled to the power supply voltage node along with the circuit group.

2. The apparatus according to claim 1, wherein, The first oscillator and the second oscillator are ring oscillators.

3. The apparatus according to claim 1, comprising: A first counter coupled to the first oscillator and a second counter coupled to the second oscillator, the first counter and the second counter being controllable by the management circuit.

4. The apparatus according to any one of claims 1 to 3, comprising: Temperature sensing circuit coupled to the management circuit.

5. The apparatus according to claim 4, wherein, The temperature sensing circuit is formed by the first oscillator and the third oscillator, the third oscillator including a third power node coupled to the first power node.

6. The apparatus according to claim 4, wherein, The temperature sensing circuit is a digital temperature sensor circuit.

7. The apparatus according to claim 1, wherein, The management circuitry includes a lookup table with parameters for identifying the aging values ​​of the circuit group based on measured frequencies from the first oscillator and the second oscillator.

8. The apparatus according to claim 1, wherein, The management circuitry includes mathematical functions for generating aging values ​​for the circuit group based on measured frequencies from the first and second oscillators.

9. The apparatus according to any one of claims 1, 7, or 8, comprising: Multiple processing cores, each including the first oscillator and the second oscillator, are used to determine the aging value of the core.

10. The apparatus according to claim 1, wherein, The first oscillator and the second oscillator are formed using the same circuit design and include more than 20 sequentially coupled inverters.

11. An apparatus comprising: The circuit group is coupled to the power supply voltage node; Management circuits; The first oscillator includes a first power node coupled to the power supply voltage node via a switch controlled by the management circuit. The second oscillator includes a second power supply node; as well as The multiplexing switch includes: (i) a multiplexing switch output node coupled to the second power node, (ii) a first multiplexing switch input coupled to the power voltage node, and (iii) a second multiplexing switch input coupled to a variable voltage source that can be controlled by the management circuit.

12. The apparatus according to claim 11, wherein, The first oscillator and the second oscillator are ring oscillators.

13. The apparatus of claim 11, comprising: A first counter coupled to the first oscillator and a second counter coupled to the second oscillator, the first counter and the second counter being controllable by the management circuit.

14. The apparatus according to any one of claims 11 to 13, wherein, The management circuit has logic for increasing the variable voltage source until the frequency of the second oscillator is greater than or equal to the frequency of the first oscillator.

15. The apparatus according to claim 14, wherein, The logic is used to adjust the voltage / frequency operating point of the circuit group based on the increased voltage of the variable voltage source.

16. The apparatus of claim 11, comprising: Multiple processing cores, each including the first oscillator and the second oscillator, to determine the operating point voltage increase of that core.

17. A non-transitory computer-readable storage medium having instructions that, when executed, perform a method comprising: Measure the first frequency from the first oscillator; A second frequency is measured from a second oscillator, which is configured the same as the first oscillator and is powered together with the circuit group to be monitored. When the first frequency is not being measured, remove the power supply from the first oscillator; as well as The aging value of the circuit group is determined based on the first frequency and the second frequency.

18. The storage medium according to claim 17, wherein the method comprises: When the first frequency and the second frequency are measured, the temperature and voltage of the first oscillator and the second oscillator are identified.

19. The storage medium according to claim 18, wherein, The temperature is identified using a third oscillator whose transistor voltage threshold is different from that of the first oscillator.

20. The storage medium according to claim 19, wherein, The voltage is identified using the third oscillator.

21. The storage medium according to claim 19, wherein, The voltage is identified from the power supply voltage control code.

22. The storage medium according to claim 18, wherein, The temperature is identified using a temperature sensor.

23. The storage medium according to claim 17, wherein, The circuit group is the processing core in the processor.

24. The storage medium according to claim 23, wherein, The core of the processing is the graphics processing core circuit.

25. A system comprising a processor, the processor including the storage medium as described in claim 17.

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