Temperature coefficient current generating circuit, chip and electronic device

Abstract

This application discloses a temperature coefficient current generation circuit, chip, and electronic device. The circuit includes: a voltage generation module providing first and second reference voltages, the difference between which has a positive temperature coefficient; a clock signal generation module generating at least one set of clock control signals containing non-overlapping relationships; a switched capacitor module responding to the clock signal, coupling the second reference voltage to an internal capacitor for charging in a first operating phase, and coupling the first reference voltage to the internal capacitor and discharging it to output voltage in a second operating phase; an error amplification module generating an error control signal based on the output voltage; and a current output module providing an output current based on the error control signal. This application replaces resistors with a switched capacitor network, making the output current independent of resistance, eliminating the influence of resistor temperature drift, and allowing for flexible adjustment via clock frequency or capacitor value, thus improving current accuracy and design freedom.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuit technology, specifically to a temperature coefficient current generating circuit, chip, and electronic device. Background Technology

[0002] Positive temperature coefficient (PTAT) current generation circuits are fundamental functional modules in analog integrated circuits, widely used in temperature sensors, bandgap reference sources, and RF power amplifier biasing. In related technologies, PTAT current typically utilizes the positive temperature coefficient characteristic of the base-emitter voltage difference (ΔVBE) of a bipolar transistor, applying this voltage difference to a resistive element to achieve current conversion.

[0003] However, the aforementioned resistor-based PTAT current generation method has inherent drawbacks: the temperature characteristics of the output current depend not only on the positive temperature coefficient of ΔVBE but also on the temperature coefficient of the resistor itself. Temperature drift of the resistor causes the actual temperature coefficient of the PTAT current to deviate from the theoretical design value, thus affecting the accuracy and stability of subsequent circuits (such as bandgap references and temperature sensors). Furthermore, adjusting the current magnitude in this method typically requires changing the resistor value, which often necessitates changes in circuit layout area or the introduction of external components, limiting the circuit's design flexibility and integration. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a temperature coefficient current generating circuit, a chip, and an electronic device to solve the above technical problems.

[0005] In a first aspect, embodiments of this application provide a temperature coefficient current generating circuit, comprising: a voltage generation module for providing a first reference voltage and a second reference voltage; wherein the difference between the second reference voltage and the first reference voltage has a positive temperature coefficient; a clock signal generation module for generating at least one set of clock control signals containing non-overlapping relationships; and a switched capacitor module connected to the voltage generation module and the clock signal generation module respectively; wherein the switched capacitor module is configured to respond to the clock control signal, receive the second reference voltage in a first operating phase to charge the internal capacitor of the switched capacitor module; and receive the first reference voltage in a second operating phase to discharge the internal capacitor of the switched capacitor module, thereby achieving the desired current generation. The circuit comprises: an output terminal that generates a detection voltage; an error amplification module connected to the switched capacitor module for generating an error control signal based on the detection voltage; and a current output module, the control terminal of which is connected to the error amplification module, and the output terminal of which is connected to the switched capacitor module. The current output module provides an output current based on the error control signal, enabling the output current to be independent of the resistive element, eliminating the influence of resistor temperature drift on the current temperature characteristics, and making the temperature coefficient of the output current depend only on the difference between the first reference voltage and the second reference voltage. Furthermore, the output current magnitude can be independently controlled by adjusting the clock frequency or capacitor value without affecting its temperature coefficient, significantly improving the circuit design flexibility and temperature stability.

[0006] Secondly, embodiments of this application also provide a chip including the temperature coefficient current generating circuit described above.

[0007] Thirdly, embodiments of this application also provide an electronic device, including the aforementioned chip or temperature coefficient current generating circuit.

[0008] The temperature coefficient current generation circuit, chip, and electronic device provided in this application replace traditional resistive elements with switched capacitor modules. By using a non-overlapping clock to control the charging and discharging of the capacitor, the reference voltage difference with a positive temperature coefficient is converted into an output current. A negative feedback loop is introduced to achieve automatic adjustment. This solves the technical problems of positive temperature coefficient current generation circuits in related technologies, such as reliance on resistive elements, inaccurate current temperature characteristics due to resistance temperature drift, and low design freedom. It has the advantages of eliminating the influence of resistance temperature drift, making the output current temperature characteristics depend only on the reference voltage difference, allowing the current magnitude to be independently adjusted by clock frequency or capacitor value without affecting its temperature coefficient, and facilitating chip integration.

[0009] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A block diagram illustrating the implementation principle of the temperature coefficient current generation circuit provided in an embodiment of this application is shown. Figure 2 This paper illustrates another implementation principle block diagram of the temperature coefficient current generation circuit provided in an embodiment of this application; Figure 3 This paper illustrates another implementation principle block diagram of the temperature coefficient current generation circuit provided in the embodiments of this application; Figure 4 A circuit diagram of the temperature coefficient current generating circuit provided in an embodiment of this application is shown; Figure 5 Another circuit diagram of the temperature coefficient current generating circuit provided in the embodiment of this application is shown; Figure 6 A block diagram illustrating the implementation principle of the chip provided in an embodiment of this application is shown; Figure 7 A block diagram illustrating the implementation principle of the electronic device provided in the embodiments of this application is shown. Detailed Implementation

[0012] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0013] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0014] In the embodiments of this application, "at least one" refers to one or more; "multiple" refers to two or more. In the description of this application, the terms "first," "second," "third," etc., are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance, nor should they be construed as indicating or implying order.

[0015] References such as “one embodiment” or “some embodiments” described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the terms “comprising,” “including,” “having,” and variations thereof, in this specification, mean “including but not limited to,” unless otherwise specifically emphasized.

[0016] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three kinds of relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0017] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0018] The temperature coefficient current generating circuit provided in this application can be applied to electronic devices that require temperature detection or temperature compensation functions, such as wearable devices, IoT terminals, and portable medical devices. Taking a wearable device as an example, the wearable device may include a temperature monitoring system, which is used to collect ambient temperature or human body temperature and execute corresponding system control strategies based on the temperature data.

[0019] Specifically, the wearable device includes a temperature sensor, a signal processing circuit, and a system control unit. The temperature sensor converts the physical quantity of temperature into an electrical signal, typically employing a temperature-sensing element based on a bipolar transistor or thermistor. The signal processing circuit includes the temperature coefficient current generation circuit, analog-to-digital converter, and digital logic circuit of this application. The system control unit adjusts the device's operating state based on temperature data, such as adjusting display brightness, controlling charging current, or triggering a temperature alarm. The raw signal output by the temperature sensor is converted into a current signal proportional to the absolute temperature by the temperature coefficient current generation circuit of this application. This current signal is then converted into a digital temperature code value by the analog-to-digital converter after current-to-voltage conversion. The digital code value generated by the analog-to-digital converter is sent to the system control unit. Based on a preset temperature threshold and mapping relationship, the system control unit outputs corresponding control signals to the controlled module, such as adjusting the bias current of the power amplifier to compensate for the effect of temperature on radio frequency performance, or controlling the start and stop of the cooling fan to maintain the device within a safe operating temperature range.

[0020] Alternatively, the wearable device can be a smart bracelet, smartwatch, wireless earphones, smart glasses, or medical monitoring patch, etc.

[0021] Please see Figure 1 This is a block diagram illustrating the implementation principle of the temperature coefficient current generating circuit provided in this embodiment. The temperature coefficient current generating circuit 100 provided in this embodiment, as shown... Figure 1 As shown, it includes a voltage generation module 10, a clock signal generation module 20, a switched capacitor module 30, an error amplification module 40, and a current output module 50.

[0022] The voltage generation module 10 is used to provide a first reference voltage VBE1 and a second reference voltage VBE2; wherein the difference between the second reference voltage VBE2 and the first reference voltage VBE1 has a positive temperature coefficient.

[0023] The clock signal generation module 20 is used to generate at least one set of clock control signals that do not overlap.

[0024] The switched capacitor module 30 is connected to both the voltage generation module 10 and the clock signal generation module 20. Specifically, the switched capacitor module 30 responds to a clock control signal, receiving a second reference voltage VBE2 in a first operating phase to charge its internal capacitor; and receiving a first reference voltage VBE1 in a second operating phase to discharge its internal capacitor and generate a detection voltage at the output of the switched capacitor module 30.

[0025] The error amplification module 40 is connected to the switched capacitor module 30, and the error amplification module 40 generates an error control signal CTRL based on the detected voltage.

[0026] The control terminal of the current output module 50 is connected to the error amplification module 40, and the output terminal of the current output module 50 is connected to the switched capacitor module 30. The current output module 50 is used to provide the output current IOUT according to the error control signal CTRL.

[0027] The error amplification module 40 detects the output voltage of the switched capacitor module 30 in real time to generate an error control signal, which dynamically adjusts the output current IOUT of the current output module 50. This output current IOUT is then fed back to the switched capacitor module 30, affecting its output voltage in subsequent operating stages.

[0028] The above process constitutes a complete negative feedback regulation cycle. Within one cycle, if the output current IOUT is too large, the charging charge in the first operating stage is excessive, leading to a higher detection voltage at the end of the second operating stage. This error will be corrected by the feedback loop in the next cycle, reducing the output current IOUT. Conversely, if the output current IOUT is too small, the detection voltage is too low, and the feedback loop will increase the output current IOUT. After multiple cycles of dynamic adjustment, the system eventually reaches a stable state, and the amount of charge charged into the internal capacitor within one cycle equals the amount of charge discharged.

[0029] According to the law of conservation of charge and circuit parameters, under steady-state conditions, the value of the output current IOUT is related to the clock frequency, the capacitance value of the switched capacitor module 30 that participates in charging and discharging, and ΔVBE (i.e., ΔVBE = VBE2 - VBE1), and is independent of the resistive element.

[0030] Since ΔVBE has a positive temperature coefficient, the output current IOUT also has a positive temperature coefficient, and its temperature coefficient is determined only by the temperature characteristics of ΔVBE and is not affected by the temperature drift of the resistor.

[0031] The current generation circuit provided in this application embodiment comprises a switched capacitor network module, an error amplification module, and a current output module forming a negative feedback loop. By replacing the resistive element in the traditional PTAT circuit with a switched capacitor module, and combining non-overlapping clock control with the negative feedback loop, a positive temperature coefficient current output independent of the resistance value is achieved. This circuit effectively eliminates the influence of resistor temperature drift on the current temperature coefficient, improving the accuracy of the current's temperature characteristics. Simultaneously, the output current magnitude can be independently controlled by adjusting the clock frequency or capacitor value without affecting the current temperature coefficient during adjustment. This solves the technical problems of PTAT current generation circuits in related technologies, such as reliance on resistive elements, susceptibility to resistor temperature drift, and limited design freedom, significantly improving the circuit's design flexibility and application adaptability.

[0032] In some embodiments, the clock signal generation module 20 may be implemented using a ring oscillator, an RC oscillator, or a crystal oscillator in conjunction with a frequency divider / delay circuit. The specific circuit structure may be selected according to the system’s requirements for clock frequency, phase accuracy, and power consumption.

[0033] In some embodiments, the voltage generation module 10 includes a first bipolar transistor and a second bipolar transistor. The first reference voltage VBE1 is the base-emitter voltage of the first bipolar transistor, and the second reference voltage VBE2 is the base-emitter voltage of the second bipolar transistor.

[0034] By setting the first bipolar transistor and the second bipolar transistor to operate at different current densities, the base-emitter voltage difference ΔVBE = VBE2 - VBE1 between the two can have a positive temperature coefficient.

[0035] Please see Figure 2 In some embodiments, the error amplification module 40 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to the output terminal of the switched capacitor module 30, and the second input terminal is used to receive a reference voltage VREF. The error amplification module 40 is used to output an error control signal CTRL at its output terminal based on the difference between the detected voltage and the reference voltage VREF.

[0036] In one specific embodiment, the error amplification module 40 is implemented using an operational transconductance amplifier (OTA), and the error control signal CTRL is a current signal.

[0037] The error amplification module 40 continuously monitors the difference between the detected voltage and the reference voltage VREF. When the second working stage ends, if the detected voltage is higher than VREF, the error amplification module 40 outputs a negative error current, causing the output current IOUT of the current output module 50 to decrease; if the detected voltage is lower than VREF, the error amplification module 40 outputs a positive error current, causing the output current IOUT of the current output module 50 to increase; if the detected voltage is equal to VREF, the output current of the error amplification module 40 is zero, and the output current IOUT of the current output module 50 remains unchanged.

[0038] The error amplification module 40 provided in this embodiment detects the deviation between the output voltage of the switched capacitor module 30 and the reference voltage in real time, and generates an error control signal based on the deviation to dynamically adjust the output current IOUT of the current output module 50. The output current IOUT is then fed back to the switched capacitor module 30, affecting its output voltage in subsequent operating stages. Through the above closed-loop adjustment mechanism, the loop can automatically search for and stabilize in a balanced state. In this state, the average value of the output current IOUT is stabilized at a preset value determined by the circuit parameters. Since the difference between the second reference voltage VBE2 and the first reference voltage VBE1 has a positive temperature coefficient, the output current IOUT correspondingly has a predetermined positive temperature coefficient characteristic.

[0039] In one specific embodiment, the current output module 50 may be implemented using a voltage-controlled current source (VCCS).

[0040] The voltage-controlled current source provides a proportional output current IOUT at its output terminal based on the error control signal CTRL received at its control terminal. Using a VCCS as the current output module, its output current has a linear relationship with the control voltage, facilitating precise adjustment through a feedback loop. Simultaneously, the VCCS has high output impedance, effectively suppressing the impact of load changes on the output current.

[0041] In some embodiments, the clock control signal includes a first clock signal CLK1, a second clock signal CLK2, a delay signal CLK1P of the first clock signal, and a delay signal CLK2P of the second clock signal; wherein the first clock signal CLK1 and the second clock signal CLK2 are non-overlapping clock signals, and the delay signals CLK1P of the first clock signal and CLK2P of the second clock signal are non-overlapping clock signals.

[0042] Please see Figure 3 In some embodiments, the switched capacitor module 30 includes a switching unit 31 and a capacitor unit 32. The switching unit 31 includes multiple switching elements 310, the control terminals of which are respectively used to receive clock control signals (i.e., a first clock signal CLK1, a second clock signal CLK2, a delayed signal CLK1P of the first clock signal, and a delayed signal CLK2P of the second clock signal). The capacitor unit 32 is connected to the switching unit 31 and includes a first capacitor C1 and a second capacitor C2. The first terminal of the second capacitor C2 is grounded. The switching unit 31 is used to connect the second reference voltage VBE2 to the first terminal of the first capacitor C1 and the current output module 50 to the second terminal of the first capacitor C1 and the second terminal of the second capacitor C2 in the first working stage, so that the first capacitor C1 and the second capacitor C2 are charged together; in the second working stage, the first reference voltage VBE1 is connected to the first terminal of the first capacitor C1 and the second terminal of the first capacitor C1 is connected to the input terminal of the error amplification module 40, and the second capacitor C2 is shorted to ground, so that the first capacitor C1 forms a discharge circuit through the error amplification module 40 and the current output module 50, so as to form the detection voltage at the input terminal of the error amplification module 40.

[0043] Specifically, the switching unit 31 is configured as follows: In response to the first clock signal CLK1 and its delay signal CLK1P, during the first operating phase, the second reference voltage VBE2 is connected to the first terminal of the first capacitor C1, and the current output module 50 is connected to the second terminals of both the first capacitor C1 and the second capacitor C2. At this time, the output current of the current output module 50 simultaneously charges the first capacitor C1 and the second capacitor C2 for a duration equal to the duration of the first operating phase. At the end of this phase, the voltage VC1 at the second terminal of the first capacitor C1 is IOUT / 2·F(C1+C2).

[0044] In response to the second clock signal CLK2 and its delay signal CLK2P, during the second operating phase, the first reference voltage VBE1 is connected to the first terminal of the first capacitor C1, the second terminal of the first capacitor C1 is connected to the input terminal of the error amplifier module 40, and the second capacitor C2 is shorted to ground and set to zero. At the instant the voltage at the first terminal of the first capacitor C1 jumps from the second reference voltage VBE2 to the first reference voltage VBE1, the voltage at the second terminal of the first capacitor C1 drops by ΔVBE = VBE2 - VBE1. Then, the first capacitor C1 discharges through the discharge circuit formed by the error amplifier module 40 and the current output module 50, causing the voltage at the second terminal of the first capacitor C1 to drop, thereby forming a detection voltage at the input terminal of the error amplifier module 40.

[0045] In some embodiments, the capacitance value of the first capacitor C1 is configured to balance the amount of charge transfer in the first operating phase and the second operating phase.

[0046] Specifically, by increasing the capacitance of the first capacitor C1, a preset matching relationship can be achieved between the amount of charge stored in the first operating stage and the amount of charge released in the second operating stage, thereby ensuring stable operation of the circuit over a wide temperature range. Those skilled in the art can configure the capacitance of the first capacitor C1 to a value sufficient to balance the charge transfer amounts in the first and second operating stages, thereby simplifying the circuit structure while maintaining the normal operating characteristics of the circuit.

[0047] In some embodiments, such as Figure 4 As shown, the switch unit 31 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, and a sixth switch S6.

[0048] The first terminal of the first switch S1 is connected to the voltage generation module 10 to receive the first reference voltage VBE1, the second terminal is connected to the first terminal of the first capacitor C1, and the control terminal is connected to the clock signal generation module 20 to receive the second clock signal CLK2.

[0049] The first terminal of the second switch S2 is connected to the voltage generation module 10 to receive the second reference voltage VBE2, the second terminal is connected to the first terminal of the first capacitor C1, and the control terminal is connected to the clock signal generation module 20 to receive the first clock signal CLK1.

[0050] The first terminal of the third switch S3 is connected to the second terminal of the first capacitor C1, and the second terminal is connected to the first terminal of the fifth switch S5. The control terminal is connected to the clock signal generation module 20 to receive the second clock signal CLK2.

[0051] The first terminal of the fourth switch S4 is connected to the second terminal of the first capacitor C1, the second terminal is connected to the current output module 50 and the second terminal of the second capacitor C2, and the control terminal is connected to the clock signal generation module 20 to receive the delay signal CLK1P of the first clock signal.

[0052] The second terminal of the fifth switch S5 is connected to the first input terminal of the error amplification module 40, and the control terminal is connected to the clock signal generation module 20 to receive the delay signal CLK2P of the second clock signal.

[0053] The first terminal of the sixth switch S6 is connected to the first terminal of the second capacitor C2, and the second terminal is connected to the second terminal of the second capacitor C2. The control terminal is connected to the clock signal generation module 20 to receive the second clock signal CLK2.

[0054] Specifically, when the first clock signal CLK1 and its delay signal CLK1P are active (e.g., CLK1=1, CLK1P=1, CLK2=0, CLK2P=0), the circuit enters the first operating stage. At this time, the states of each switch are as follows: The first switch S1, the third switch S3, the fifth switch S5, and the sixth switch S6 are disconnected; The second switch S2 is turned on, and the second reference voltage VBE2 is applied to the first terminal of the first capacitor C1; The fourth switch S4 is turned on, connecting the output terminal of the current output module 50 to the second terminal of the first capacitor C1 and the second terminal of the second capacitor C2.

[0055] In the aforementioned switching state, the first terminal of the second capacitor C2 is grounded, and the second terminal of the second capacitor C2 is connected to the second terminal of the first capacitor C1 through the conducting fourth switch S4. At this time, the second capacitor C2 and the first capacitor C1 are connected in parallel. The output current IOUT of the current output module 50 flows through the conducting fourth switch S4, simultaneously charging the parallel first capacitor C1 and the second capacitor C2, causing the voltage across the first capacitor C1 and the second capacitor C2 to rise linearly. At the end of this stage, the voltage value of the first capacitor C1 is related to factors such as the output current IOUT, the clock frequency F, and the capacitance value C1.

[0056] When the second clock signal CLK2 and its delay signal CLK2P are active (e.g., CLK1=0, CLK1P=0, CLK2=1, CLK2P=1), the circuit enters the second operating phase. At this time, the states of each switch are as follows: The first switch S1 is turned on, and the first reference voltage VBE1 is applied to the first terminal of the first capacitor C1; When the third switch S3 and the fifth switch S5 are turned on, the second end of the first capacitor C1 is connected to the first input terminal (i.e., the negative input terminal of OTA) of the error amplifier module 40 through the third switch S3 and the fifth switch S5. The second switch S2 and the fourth switch S4 are turned off.

[0057] In the aforementioned switching state, the first terminal of the second capacitor C2 is grounded, and the second terminal of the second capacitor C2 is short-circuited to ground through the conducting sixth switch S6, forming a short circuit. According to capacitor characteristics, the voltage across the second capacitor C2 cannot change abruptly. However, at the instant the sixth switch S6 is turned on, the second capacitor C2 discharges rapidly through the sixth switch S6, forcibly pulling the voltage at its second terminal to ground potential. The discharge time is extremely short (depending on the on-resistance of S6 and the capacitance of C2), and it can be considered that at the beginning of the second operating phase, the second capacitor C2 completes its discharge instantaneously, and the voltage drops to 0V. Thereafter, throughout the entire second operating phase, the second capacitor C2 remains at 0V.

[0058] At the instant the second operating phase begins, the voltage at the first terminal of the first capacitor C1 switches from the second reference voltage VBE2 to the first reference voltage VBE1. Based on the principle that the voltage across a capacitor cannot change abruptly, this transition is coupled to the second terminal of the first capacitor C1 via the capacitor, causing the detection voltage at the second terminal of the first capacitor C1 to decrease synchronously by ΔVBE = VBE2 - VBE1. The conducting third switch S3, fifth switch S5, error amplification module 40, current output module 50, and the conducting sixth switch S6 form a conducting discharge path to ground. The first capacitor C1 discharges through this path, and its second terminal voltage gradually decreases. The error amplification module 40 detects the difference between its first input voltage and the reference voltage VREF in real time and adjusts the output current IOUT accordingly. The negative feedback loop ensures that, in steady state, at the end of the second operating phase, the detection voltage received at the first input of the error amplification module 40 is equal to VREF, at which point the discharge amount of the first capacitor C1 is balanced with the charging amount during the first operating phase.

[0059] Please see Figure 5 This is another circuit diagram of the temperature coefficient current generating circuit provided in the embodiments of this application.

[0060] In some embodiments, capacitor unit 32 further includes a third capacitor C3; The switching unit 31 is also used for: In the first working stage, the first terminal of the third capacitor C3 is connected to a reference voltage VREF, and the second reference voltage VBE2 is connected to the second terminal of the third capacitor C3, so that the third capacitor C3 is biased between the reference voltage VREF and the second reference voltage VBE2. In the second working stage, the first reference voltage VBE1 is connected to the second terminal of the third capacitor C3, and the first terminal of the third capacitor C3 is connected to the input terminal of the error amplification module 40, so that the first capacitor C1 and the third capacitor C3 discharge together to form the detection voltage at the input terminal of the error amplification module 40.

[0061] In one specific embodiment, the switching unit 31 further includes a seventh switch S7, an eighth switch S8, and a ninth switch S9.

[0062] The first terminal of the seventh switch S7 is used to receive the reference voltage VREF. The second terminal is connected to the second terminal of the third switch S3, the first terminal of the fifth switch S5, and the first terminal of the third capacitor C3. The control terminal is connected to the clock signal generation module 20 to receive the delay signal CLK1P of the first clock signal.

[0063] The first terminal of the eighth switch S8 is connected to the voltage generation module 10 to receive the first reference voltage VBE1, the second terminal is connected to the second terminal of the third capacitor C3, and the control terminal is connected to the clock signal generation module 20 to receive the second clock signal CLK2.

[0064] The first terminal of the ninth switch S9 is connected to the voltage generation module 10 to receive the second reference voltage VBE2, the second terminal is connected to the second terminal of the third capacitor C3, and the control terminal is connected to the clock signal generation module 20 to receive the first clock signal CLK1.

[0065] In the first and / or second operating phases, the switching unit 31 selectively couples the third capacitor C3 between the second terminal of the first capacitor C1 and the first input terminal of the error amplification module 40 to adjust the charge transfer amount of the switching capacitor module 30.

[0066] Specifically, in the first working stage, the first switch S1, the third switch S3, the fifth switch S5, the sixth switch S6 and the eighth switch S8 are disconnected, while the second switch S2, the fourth switch S4, the seventh switch S7 and the ninth switch S9 are turned on.

[0067] In the aforementioned switching state, the first terminal of the third capacitor C3 receives the reference voltage VREF through the conducting seventh switch S7, and the second terminal is connected to the second reference voltage VBE2 through the conducting ninth switch S9. Since the third switch S3 and the fifth switch S5 are open, the node connected to the first terminal of the third capacitor C3 (i.e., the second terminal of the third switch S3 and the first terminal of the fifth switch S5) is isolated from other parts of the circuit. Therefore, the third capacitor C3 is independently biased, and the voltage across the third capacitor C3 is forcibly set to VC3 = VREF - VBE2, which remains constant throughout the first operating phase. The charge stored in the third capacitor C3 is QC3 = C3·(VREF - VBE2). At this time, the third capacitor C3 is isolated from other parts of the circuit and does not affect the charging process of the first capacitor C1.

[0068] In the second working phase, the first switch S1, the third switch S3, the fifth switch S5, the sixth switch S6 and the eighth switch S8 are turned on, while the second switch S2, the fourth switch S4, the seventh switch S7 and the ninth switch S9 are turned off.

[0069] In the aforementioned switching state, the first terminal of the third capacitor C3 is floating through the open seventh switch S7, but connected to the second terminal of the third switch S3 and the first terminal of the fifth switch S5 through a node (i.e., the second terminal of the third switch S3 and the first terminal of the fifth switch S5). The second terminal of the third capacitor C3 is connected to the first reference voltage VBE1 through the closed eighth switch S8. Since the third switch S3 is closed, the second terminal of the first capacitor C1 is connected to this node; the fifth switch S5 is closed, and this node is connected to the first input terminal (i.e., the negative input terminal of the OTA) of the error amplification module 40. Therefore, in the second operating phase, the third capacitor C3 and the first capacitor C1 are connected to the same node, and the second terminal of the third capacitor C3 is connected to the first reference voltage VBE1, and the first terminal of the first capacitor C1 is also connected to the first reference voltage VBE1. The charge on the node is redistributed, and the third capacitor C3 participates in the discharge process.

[0070] Let the node voltage be VN at the start (instantaneous) of the second operating phase. According to the law of charge conservation, the total charge on the node remains constant before and after the switch switching. The charges on the first capacitor C1, the third capacitor C3, and the parasitic capacitances need to be considered.

[0071] At the end of the first operating phase, the charge stored in the third capacitor C3 is QC3 = C3·(VREF - VBE2). Upon entering the second operating phase, the second terminal of the third capacitor C3 is forcibly connected to VBE1. If the node voltage changes to VN, the charge on the third capacitor C3 becomes QC3 = C3·(VN - VBE1). This charge change in the third capacitor C3 will affect the discharge process of the first capacitor C1 through the node.

[0072] In effect, the addition of the third capacitor C3 is equivalent to adding a capacitor branch between the node and VBE1, altering the node's equivalent capacitance to ground and the discharge time constant. By selecting an appropriate value for the third capacitor C3, the charge transfer amount in the second operating phase can be finely adjusted, thereby optimizing the charge-discharge balance. Specifically, if the value of the third capacitor C3 is large, the node's equivalent capacitance increases, the discharge rate slows down, and the node voltage drop is smaller at the end of the second operating phase; conversely, if the value of the third capacitor C3 is small, the node's equivalent capacitance decreases, the discharge rate accelerates, and the node voltage drop is larger.

[0073] By adjusting the third capacitor C3, the node voltage can reach the target value (compared to VREF) at the end of the second operating phase, thereby affecting the regulation of the feedback loop.

[0074] This embodiment, by adding a third capacitor C3 and its associated switches (S7, S8, S9), provides additional charge transfer regulation capability while maintaining the positive temperature coefficient current generation characteristic independent of resistance. The third capacitor C3 is pre-charged in the first operating phase and connected in parallel in the second operating phase, changing the equivalent capacitance of the discharge circuit, thereby achieving fine adjustment of the charge-discharge balance. This helps improve the accuracy and stability of the output current, reduce ripple, and enhance the circuit's robustness to process variations.

[0075] It should be noted that those skilled in the art can choose whether to use a third capacitor C3 based on actual design requirements, and obtain the desired circuit performance by adjusting its capacitance value.

[0076] In some embodiments, the capacitor unit 32 further includes a fourth capacitor C4, the first end of which is connected to the input terminal of the error amplification module 40, and the second end of which is connected to the output terminal of the error amplification module 40.

[0077] The fourth capacitor, C4, forms a feedback path between the input and output of the OTA, effectively reducing the high-frequency gain of the loop, improving the phase margin, and ensuring the stability of the negative feedback loop. By appropriately selecting the capacitance value of the fourth capacitor C4, the transient response speed of the circuit can be optimized while ensuring stability, avoiding oscillations or overshoots in the output current IOUT. Those skilled in the art can determine the optimal value of the fourth capacitor C4 through simulation or calculation based on the system bandwidth and phase margin requirements.

[0078] The working principle of the circuit in this embodiment will be explained in detail below.

[0079] This circuit controls the switching capacitor module to turn on and off via a clock signal, enabling the circuit to alternate between the first operating stage (charging stage) and the second operating stage (discharging stage), and utilizes a negative feedback loop to achieve automatic adjustment and stabilization of the output current.

[0080] The following is combined Figure 5 The preferred embodiments of the present invention will be described in detail below.

[0081] In the first operating phase (e.g., CLK1 and CLK1P are active): S2, S4, S7, and S9 are turned on, while the others are turned off. VBE2 is applied to the first terminal of C1 via S2, and IOUT charges C1 via S4; simultaneously, C2 is connected in parallel with C1 and is charged together, with an equivalent capacitance of C1 + C2; C3 is biased between VREF and VBE2 via S7 and S9, with a voltage of VREF - VBE2 across it, isolating it from the circuit. At the end of this phase, the voltage at the second terminal of C1 and C2 rises to a value related to IOUT, the total capacitance, and the clock cycle.

[0082] Second operating phase (CLK2, CLK2P active): S1, S3, S5, S6, and S8 are on, the rest are off. S1 connects VBE1 to the first terminal of C1, causing an instantaneous drop in the voltage at the second terminal of C1 by ΔVBE, which is transmitted to the negative terminal of OTA via S3 and S5. Subsequently, C1 discharges through S3 and S5, and its second terminal voltage continues to drop. S6 conducts, causing C2 to short-circuit and discharge to zero, isolating it from C1. S8 connects VBE1 to the second terminal of C3. The first terminal of C3 is connected to the negative terminal of OTA through node N, thus C3 and C1 discharge in parallel, changing the equivalent capacitance of the node and finely adjusting the discharge process. OTA compares the negative terminal voltage with VREF in real time, and outputs an error current to control VCCS to adjust IOUT. After several cycles, the loop reaches a steady state. At the end of the second operating phase, the voltage at the negative terminal of OTA equals VREF, and the charging and discharging are balanced.

[0083] In this embodiment, the output current IOUT is only related to ΔVBE, the clock frequency F, and the capacitance value, and is independent of the resistance. Therefore, the temperature characteristics depend only on ΔVBE. C2, C3, and C4 are optional components, providing charging equivalent capacitance adjustment, fine-tuning of discharge balance, and frequency compensation, respectively. They can be selected or omitted according to design requirements without affecting the basic function of the circuit.

[0084] This application also provides a chip, such as... Figure 6As shown, the chip 200 includes the aforementioned temperature coefficient current generation circuit 100. A chip (integrated circuit, IC) can be, but is not limited to, a system-on-chip (SoC) chip or a system-in-package (SIP) chip. The chip 200 integrates a voltage generation module, a clock signal generation module, a switched capacitor module, an error amplification module, and a current output module onto the same semiconductor substrate, utilizing switched capacitor technology to replace traditional resistive elements to generate a positive temperature coefficient current. Specifically, through a non-overlapping clock-controlled switching network, the capacitor is connected to a reference voltage with a positive temperature coefficient difference at different operating stages, transferring charge to the input of the error amplification module. After adjustment by a negative feedback loop, a stable current proportional to temperature is output. This solves the technical problems of traditional positive temperature coefficient current generation circuits, such as reliance on resistive elements, inaccurate current-temperature characteristics due to resistor temperature drift, low design freedom, and difficulty in flexibly adjusting the current magnitude. Simultaneously, since the circuit contains no resistors, it effectively saves chip area, reduces the impact of process variations on performance, and improves product consistency and reliability. The chip 200 can be widely used in electronic devices that require temperature compensation or temperature detection functions, such as wearable devices, IoT terminals, and portable medical devices.

[0085] This application also provides an electronic device, such as... Figure 7As shown, the electronic device 300 includes a device body and the chip 200 described above disposed within the device body. The electronic device can be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (universal serial bus) docking station, stylus, true wireless earphones, car infotainment screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights. The electronic device 300, by employing the chip 200 containing the aforementioned temperature coefficient current generation circuit, provides a high-precision, resistance-independent positive temperature coefficient bias current or reference current to the analog modules (such as sensor front-ends, amplifiers, analog-to-digital converters, etc.) inside the device. The temperature characteristics of this current are determined solely by the ΔVBE of the bipolar transistor, unaffected by on-chip resistor temperature drift, thus significantly improving the measurement accuracy and stability of electronic devices over a wide temperature range. For example, in infrared electronic thermometers, this chip can provide precise bias current for thermopile sensors, minimizing temperature measurement errors; in the heart rate monitoring module of smart bracelets, it can optimize the drive current of photodiodes, improving signal quality; and in fast chargers, it can be used in temperature compensation circuits to ensure charging safety. Therefore, this electronic device 300 can solve the performance fluctuation problem caused by current source temperature drift in traditional devices, achieving higher reliability, longer lifespan, and a better user experience.

[0086] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A temperature coefficient current generating circuit, characterized in that, include: A voltage generation module is used to provide a first reference voltage and a second reference voltage; wherein the difference between the second reference voltage and the first reference voltage has a positive temperature coefficient; A clock signal generation module is used to generate at least one set of clock control signals that do not overlap. A switched capacitor module is connected to both the voltage generation module and the clock signal generation module. The switched capacitor module is configured to respond to the clock control signal by receiving the second reference voltage in a first operating phase to charge its internal capacitor; and by receiving the first reference voltage in a second operating phase to discharge its internal capacitor, thereby generating a detection voltage at the output terminal of the switched capacitor module. An error amplification module, connected to the switched capacitor module, is used to generate an error control signal based on the detected voltage; and A current output module is provided, wherein the control terminal of the current output module is connected to the error amplification module, and the output terminal of the current output module is connected to the switched capacitor module. The current output module is used to provide output current according to the error control signal.

2. The circuit according to claim 1, characterized in that, The switched capacitor module includes: The switching unit includes multiple switching elements, and the control terminals of the multiple switching elements are respectively used to receive the clock control signal; A capacitor unit is connected to the switching unit. The capacitor unit includes a first capacitor and a second capacitor, and the first terminal of the second capacitor is grounded. The switching unit is used for: During the first working phase, the second reference voltage is connected to the first terminal of the first capacitor, and the current output module is connected to the second terminal of the first capacitor and the second terminal of the second capacitor, so that the first capacitor and the second capacitor are charged together. In the second operating phase, the first reference voltage is connected to the first terminal of the first capacitor, the second terminal of the first capacitor is connected to the input terminal of the error amplification module, and the second capacitor is shorted to ground, so that the first capacitor forms a discharge circuit through the error amplification module and the current output module, thereby generating the detection voltage at the input terminal of the error amplification module.

3. The circuit according to claim 2, characterized in that, The clock control signal includes a first clock signal, a second clock signal, a delay signal of the first clock signal, and a delay signal of the second clock signal; wherein the first clock signal and the second clock signal are non-overlapping clock signals, and the delay signal of the first clock signal and the delay signal of the second clock signal are non-overlapping clock signals.

4. The circuit according to claim 3, characterized in that, The switching unit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch; The first terminal of the first switch is connected to the voltage generation module to receive the first reference voltage, the second terminal is connected to the first terminal of the first capacitor, and the control terminal is connected to the clock signal generation module to receive the second clock signal. The first end of the second switch is connected to the voltage generation module to receive the second reference voltage, the second end is connected to the first end of the first capacitor, and the control end is connected to the clock signal generation module to receive the first clock signal. The first terminal of the third switch is connected to the second terminal of the first capacitor, the second terminal is connected to the first terminal of the fifth switch, and the control terminal is connected to the clock signal generation module to receive the second clock signal. The first terminal of the fourth switch is connected to the second terminal of the first capacitor, the second terminal is connected to the current output module and the second terminal of the second capacitor, and the control terminal is connected to the clock signal generation module to receive the delay signal of the first clock signal; The second terminal of the fifth switch is connected to the input terminal of the error amplification module, and the control terminal is connected to the clock signal generation module to receive the delayed signal of the second clock signal; The first terminal of the sixth switch is connected to the first terminal of the second capacitor, the second terminal is connected to the second terminal of the second capacitor, and the control terminal is connected to the clock signal generation module to receive the second clock signal.

5. The circuit according to claim 4, characterized in that, The capacitor unit also includes a third capacitor; The switching unit is further used for: In the first working stage, the first terminal of the third capacitor is connected to a reference voltage, and the second reference voltage is connected to the second terminal of the third capacitor, so that the third capacitor is biased between the reference voltage and the second reference voltage. In the second operating phase, the first reference voltage is connected to the second terminal of the third capacitor, and the first terminal of the third capacitor is connected to the input terminal of the error amplification module, so that the first capacitor and the third capacitor discharge together to form the detection voltage at the input terminal of the error amplification module.

6. The circuit according to claim 5, characterized in that, The switching unit also includes a seventh switch, an eighth switch, and a ninth switch; The first terminal of the seventh switch is used to receive a reference voltage, the second terminal is connected to the second terminal of the third switch and the first terminal of the fifth switch, and the control terminal is connected to the clock signal generation module to receive the delay signal of the first clock signal. The first end of the eighth switch is connected to the voltage generation module to receive the first reference voltage, the second end is connected to the second end of the third capacitor, and the control end is connected to the clock signal generation module to receive the second clock signal. The first terminal of the ninth switch is connected to the voltage generation module to receive the second reference voltage, the second terminal is connected to the second terminal of the third capacitor, and the control terminal is connected to the clock signal generation module to receive the first clock signal. The first terminal of the third capacitor is connected to the second terminal of the seventh switch.

7. The circuit according to claim 2, characterized in that, The capacitance value of the first capacitor is configured to balance the amount of charge transfer in the first operating phase and the second operating phase.

8. The circuit according to claim 1, characterized in that, The error amplification module includes a first input terminal, a second input terminal, and an output terminal; wherein, the first input terminal is connected to the output terminal of the switched capacitor module, and the second input terminal is used to receive a reference voltage; The error amplification module is used to output the error control signal at the output terminal based on the difference between the detected voltage and the reference voltage.

9. The circuit according to claim 8, characterized in that, The error amplification module is an operational transconductance amplifier, and the error control signal is a current signal.

10. The circuit according to claim 1, characterized in that, The voltage generation module includes a first bipolar transistor and a second bipolar transistor; wherein the first reference voltage is the base-emitter voltage of the first bipolar transistor, and the second reference voltage is the base-emitter voltage of the second bipolar transistor.

11. A chip, characterized in that, Includes a temperature coefficient current generating circuit as described in any one of claims 1 to 10.

12. An electronic device, characterized in that, It includes a device body and a chip as described in claim 11 disposed within the device body.

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