Ecc fault-tolerant structure covering full communication path and memory fault-tolerant design method

Abstract

This invention discloses an ECC fault-tolerant structure and memory fault-tolerant design method covering the entire communication path, relating to the field of on-chip memory technology. It addresses the technical problem that existing on-chip memory EDAC technology's protection scope is limited to the on-chip memory cell itself, and introduces additional errors during data transmission, making it difficult to guarantee data integrity. The ECC fault-tolerant structure covering the entire communication path includes a host module, an interconnect bus, and storage components. The host module is configured with an ECC codec. The host module is used to implement access control of the storage components. The interconnect bus is used to implement access routing between the host module and the storage components and establish a connection between them. The host module initiates a data write access, encodes the pre-written data using ECC, and then initiates a write access to the storage component. The interconnect bus routes the access to the corresponding storage component based on the access address.

Description

Technical Field

[0001] This invention relates to the field of on-chip memory technology, and more specifically, to an ECC fault-tolerant structure covering the entire communication path and a memory fault-tolerant design method. Background Technology

[0002] With the continuous advancement of integrated circuit manufacturing processes and the increasing capacity of on-chip memory, memory cell errors have become more severe. Error Detection and Correction (EDAC) technology improves the reliability and fault tolerance of system chips by introducing additional check bits to detect and correct errors in memory.

[0003] In traditional on-chip memory EDAC technology, the ECC (Error Correcting Code) encoder and decoder are both implemented in the memory controller. During the data writing phase, the memory controller first performs ECC encoding on the data to generate error correction codes, and then writes the data and ECC codes together into the on-chip memory. During the data reading phase, the memory controller reads the original data and the corresponding error correction codes from the on-chip memory, then performs error detection and correction through the ECC decoder, and finally outputs the corrected data to the bus. This memory EDAC technology achieves the detection and repair of soft errors within the memory array, but this approach has significant limitations: the protection scope is limited to the on-chip memory cells themselves, and it cannot cover the complete data transmission path from the processor to the bus to the memory. Additional errors are introduced during data transmission, and these errors cannot be detected and corrected by traditional EDAC technology, making it difficult to fully guarantee data integrity. Summary of the Invention

[0004] The purpose of this invention is to provide an ECC fault-tolerant structure and memory fault-tolerant design method covering the entire communication path, to solve the technical problem that the protection scope of existing on-chip memory EDAC technology is limited to the on-chip memory cell itself, and additional errors are introduced during data transmission, making it difficult to guarantee data integrity. In view of this, this invention is achieved through the following solution.

[0005] In a first aspect, the present invention provides an ECC fault-tolerant structure covering the entire communication path, including a host module, an interconnect bus, and a storage component; the host module is configured with an ECC codec. The host module is used to implement access control to the storage component; The interconnect bus is used to implement access routing between the host module and the storage component, and to establish the connection between the host module and the storage component according to the system address mapping relationship; The host module initiates a data write access, encodes the pre-written data using ECC, and then initiates a write access to the storage unit to transmit the written data and the ECC encoding. After receiving the write access, the interconnect bus routes the access to the corresponding storage unit according to the access address.

[0006] Compared with existing technologies, the ECC fault-tolerant structure of this invention, covering the entire communication path, includes a host module equipped with an ECC codec for controlling access to storage components. The interconnect bus facilitates access routing between the host module and storage components and establishes a connection between them based on system address mapping. After the host module initiates a write access, it encodes the pre-written data using ECC and then initiates a write access to the storage component to transmit the written data and the ECC encoding. Upon receiving the write access, the interconnect bus routes the access to the corresponding storage component based on the access address. Based on this technical solution, this invention achieves end-to-end protection from the host module and interconnect bus to the storage component by performing ECC encoding at the data generation source and performing verification and error correction at each critical node of data transmission. This effectively detects and repairs errors during transmission, significantly improving data integrity and reliability. The most critical difference between this invention and existing technologies lies in the fact that, through the above technical solution, the ECC codec can transmit data and parity bits together via the bus, and through Hsiao encoding, it can achieve efficient protection of data bits and address bits. This solves the technical problem that the protection scope of existing on-chip memory EDAC technology is limited to the data bits of the on-chip memory unit itself, and additional errors are introduced during data transmission, making it difficult to guarantee data integrity. At the same time, the parity bit encoding and decoding logic is moved to the master device side of the request bus, making full use of the host's time window, optimizing the timing of the system bus, and improving the performance of the system chip to a certain extent.

[0007] Furthermore, in the ECC fault-tolerant structure covering the entire communication path of the present invention, after the host module initiates a data write access, it includes: The host module encodes the pre-written data using ECC and initiates write access to the storage unit according to the system bus timing to transmit the written data and ECC encoding. After receiving a write access initiated by the host module, the interconnect bus routes the access to the storage component according to the access address. After receiving the write access from the interconnect bus, the storage component stores the data and ECC encoding in the internal storage unit.

[0008] Furthermore, in the ECC fault-tolerant structure covering the entire communication path of the present invention, the host module includes a processor, a peripheral host, and a direct memory access controller.

[0009] Furthermore, in the ECC fault-tolerant structure covering the entire communication path of the present invention, when the host module initiates a data read access, the host module initiates a read access to the storage component according to the system bus timing.

[0010] Furthermore, in the ECC fault-tolerant structure covering the entire communication path of the present invention, after the host module initiates a data read access, the interconnect bus receives the read access initiated by the host module and routes the read access to the corresponding storage component according to the access address.

[0011] Furthermore, in the ECC fault-tolerant structure covering the entire communication path of the present invention, after the storage component receives a read access from the interconnect bus, it transmits the read data and ECC code to the corresponding host module through the interconnect bus. When the storage component detects that it has received a read access smaller than the bus data bit width, it triggers the read-modify-write strategy.

[0012] Furthermore, in the ECC fault-tolerant structure covering the entire communication path of the present invention, for the read-modify-write strategy, when the storage component continuously writes data smaller than the bus data bit width, the clock cycle required for each write is shortened from 3 cycles to 2 cycles by pipelining the read original data stage and the write modified data stage.

[0013] Furthermore, in the ECC fault-tolerant structure covering the entire communication path of the present invention, during read access and write access, the host module configured with an ECC codec detects and corrects transmission path errors, interconnect bus errors, and internal data or ECC encoding errors of the storage component through Hsiao encoding.

[0014] Furthermore, in the ECC fault-tolerant structure covering the entire communication path of the present invention, the storage component includes static random access memory and / or flash memory.

[0015] Secondly, the present invention provides a memory fault-tolerant design method, applied to the aforementioned ECC fault-tolerant structure covering the entire communication path, comprising: By splicing together two 36-bit data width static random access memories, a 72-bit data width storage structure is obtained, and 64-bit data and the corresponding 8-bit check code are combined and written into the static random access memory.

[0016] Compared with the prior art, the static random access memory structure obtained in the memory fault-tolerant design method of the present invention is based on a partitioned block power consumption control architecture. By splicing two 36-bit data width static random access memories (SRAM), a 72-bit data width storage structure is realized, and 64-bit data and the corresponding 8-bit check code are merged and written into the SRAM memory. This structure not only protects the integrity during storage and transmission, but also optimizes the access timing. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of an ECC fault-tolerant structure covering the entire communication path according to the present invention; Figure 2 A schematic diagram illustrating the workflows of traditional ECC and end-to-end ECC; Figure 3 A schematic diagram of the structure after fault-tolerant design covering the entire communication path for static random access memory; Figure 4 This is a schematic diagram of the H matrix encoded by Hsiao in Embodiment 2 of the present invention; Figure 5 This is a schematic diagram illustrating a read-modify-write operation example in Embodiment 2 of the present invention; Figure 6 This is a diagram illustrating the existing read-modify-write strategy; Figure 7 This is a schematic diagram of the read-modify-write strategy after pipeline optimization in Embodiment 2 of the present invention; Figure 8 This is a schematic diagram of traditional on-chip memory EDAC technology.

[0018] Figure label: exist Figure 6 and Figure 7 In this diagram, CLK represents the memory clock input, RE represents the read enable signal, DOUT represents the read data output, WE represents the write enable signal, DIN represents the write data input, D1 represents the write data 1 of the existing read-modify-write strategy, D2 represents the write data 2 of the existing read-modify-write strategy, D1` represents the write data 1 of the read-modify-write strategy in Embodiment 2 of the present invention, and D2` represents the write data 2 of the read-modify-write strategy in Embodiment 2 of the present invention. Detailed Implementation

[0019] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0020] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0022] The core of EDAC technology is the use of hardware-implemented encoders and decoders to perform error detection and correction. The design of these two modules directly affects the reliability of stored data and memory performance, while also placing high demands on the efficiency of hardware resource utilization. During the write phase, the encoder generates check bits for the original data, while during the read phase, the decoder detects errors in the data and locates and corrects them according to the check algorithm, thereby ensuring stable system operation.

[0023] Please see Figure 8 In traditional on-chip memory EDAC technology, the ECC (Error Correcting Code) encoder and decoder are both implemented in the memory controller. During the data writing phase, the memory controller first performs ECC encoding on the data to generate error correction codes, and then writes the data and ECC codes together into the on-chip memory. During the data reading phase, the memory controller reads the original data and corresponding error correction codes from the on-chip memory, then performs error detection and correction through the ECC decoder, and finally outputs the corrected data to the bus. This memory EDAC technology achieves the detection and repair of soft errors within the memory array, but this approach has significant limitations: the protection scope is limited to the on-chip memory cells themselves, and it cannot cover the complete data transmission path from the processor to the bus to the memory. Additional errors are introduced during data transmission, and these errors cannot be detected and corrected by traditional EDAC technology, making it difficult to fully guarantee data integrity.

[0024] To address the above technical problems, this invention provides an ECC fault-tolerant structure covering the entire communication path, including a host module, an interconnect bus, and a storage component. The host module is configured with an ECC codec. The host module is used to implement access control of the storage component. The interconnect bus is used to implement access routing between the host module and the storage component, and establishes a connection between the host module and the storage component according to the system address mapping relationship. The host module initiates a data write access, encodes the pre-written data using ECC, and then initiates a write access to the storage component to transmit the written data and the ECC encoding. Upon receiving the write access, the interconnect bus routes the access to the corresponding storage component according to the access address.

[0025] With the above technical solution, in the ECC fault-tolerant structure covering the entire communication path of the present invention, the host module is configured with an ECC codec and is used to implement access control of the storage unit; the interconnect bus is used to implement access routing between the host module and the storage unit, and establishes a connection between the host module and the storage unit according to the system address mapping relationship; after the host module initiates a data write access, it initiates a write access to the storage unit by ECC encoding the pre-written data to transmit the written data and ECC encoding; after receiving the write access, the interconnect bus routes the access to the corresponding storage unit according to the access address. Based on the above technical solution, the present invention achieves full-path protection from the host module, interconnect bus to storage unit by performing ECC encoding at the data generation source and performing verification and error correction at each key node of data transmission, which can effectively detect and repair errors in the transmission process, and significantly improve data integrity and reliability. The most critical difference between this invention and existing technologies lies in the fact that, through the above technical solution, the ECC codec can transmit data and parity bits together via the bus, and through Hsiao encoding, it can achieve efficient protection of data bits and address bits. This solves the technical problem that the protection scope of existing on-chip memory EDAC technology is limited to the data bits of the on-chip memory unit itself, and additional errors are introduced during data transmission, making it difficult to guarantee data integrity. At the same time, the parity bit encoding and decoding logic is moved to the master device side of the request bus, making full use of the host's time window, optimizing the timing of the system bus, and improving the performance of the system chip to a certain extent.

[0026] To better understand the present invention, the following specific embodiments further illustrate the content of the present invention, but the content of the present invention is not limited to the following embodiments.

[0027] Example 1 This embodiment provides an ECC fault-tolerant architecture covering the entire communication path, including a host module, an interconnect bus, and storage components; the host module includes a processor, a peripheral host, and a DMA (Direct Memory Access) controller; the storage components include SRAM memory and FLASH memory; wherein: The host module is configured with an ECC codec; the host module is used to implement access control to the storage component; the interconnect bus is used to implement access routing between the host module and the storage component, and to establish a connection between the host module and the storage component according to the system address mapping relationship; The host module encodes the pre-written data using ECC and initiates a write access to the storage unit according to the system bus timing to transmit the written data and ECC encoding. After receiving the write access initiated by the host module, the interconnect bus routes the access to the storage unit according to the access address. After receiving the write access from the interconnect bus, the storage unit stores the data and ECC encoding in its internal storage unit.

[0028] Furthermore, when the host module initiates a data read access, it initiates a read access to the storage component according to the system bus timing. After the host module initiates the data read access, the interconnect bus receives the read access initiated by the host module and routes the read access to the corresponding storage component according to the access address. After the storage component receives the read access from the interconnect bus, it transmits the read data and ECC encoding to the corresponding host module through the interconnect bus. When it detects that the storage component has received a read access smaller than the bus data width, it triggers a read-modify-write strategy. For the read-modify-write strategy, when the storage component continuously writes data smaller than the bus data width, the clock cycles required for each write are shortened from 3 cycles to 2 cycles by pipelining the original data reading stage and the modified data writing stage.

[0029] Furthermore, in the ECC fault-tolerant structure, during read and write accesses, the host module configured with an ECC codec uses Hsiao encoding to detect and correct transmission path errors, interconnect bus errors, and internal data or ECC encoding errors of the storage component.

[0030] Example 2 Firstly, please refer to Figure 1This embodiment provides an ECC fault-tolerant structure covering the entire communication path. The ECC fault-tolerant structure consists of a host module, an interconnect bus, and an SRAM / FLASH storage component. The host module includes a processor, a peripheral host, and a DMA controller. The host module is used to implement access control of the storage component. The interconnect bus is used to implement access routing between the host module and the storage component and to establish a connection between the host module and the storage component according to the system address mapping relationship. The storage component is responsible for storing system data.

[0031] When any host module (processor, peripheral host, or DMA controller) initiates a data write access, it encodes the pre-written data using ECC and initiates a write access to the storage unit according to the system bus timing to transmit the written data and ECC encoding. Upon receiving the write access from the host module, the interconnect bus routes the write access to the corresponding storage unit based on the access address. Upon receiving the write access from the interconnect bus, the storage unit stores the data and ECC encoding in its internal memory.

[0032] When any host module (processor, peripheral host, or DMA controller) initiates a data read access, it initiates a read access to the storage unit according to the system bus timing. Upon receiving the read access from the host module, the interconnect bus routes the read access to the corresponding storage unit based on the access address. Upon receiving the read access from the interconnect bus, the storage unit transmits the read data and ECC encoding to the corresponding host module via the interconnect bus. The host module, upon receiving the data and ECC encoding, decodes the data and checks for errors in the data and encoding.

[0033] During read / write access, any error that occurs in any transmission path, interconnect bus, or internal data or ECC encoding of the storage component can be detected by the host.

[0034] Further, please refer to Figure 2 , Figure 2 The workflows of conventional ECC and end-to-end ECC (i.e., the ECC in this invention) are demonstrated, based on... Figure 2The traditional ECC workflow is as follows: the bus master initiates a data write access, the access is routed to the memory, the memory controller generates an ECC check bit and stores the data along with the check bit in the memory, the bus master initiates a read request for the previously stored data and the access is routed to the memory, the memory controller performs ECC check bit decoding, performs error detection and correction, and sends the corrected data to the bus, the bus master receives the read data and continues to execute the task. It can be seen that traditional ECC only completes data error detection and repair within the memory controller, limiting the error correction scope to within the storage array, and cannot cover errors introduced during data transmission, affecting the system's data integrity. Unlike traditional ECC, the ECC fault-tolerant structure of this invention, which covers the entire communication path, provides ECC coverage across the entire communication path (i.e.,...). Figure 2 The end-to-end ECC in this system achieves end-to-end protection from the processor and interconnect bus to the memory by performing ECC encoding at the data generation source and verification and error correction at each critical node of data transmission. This effectively detects and repairs errors during transmission, significantly improving data integrity and reliability. Specifically, this ECC covering the entire communication path (i.e., Figure 2 The end-to-end ECC workflow in this system can be as follows: The bus master initiates a data write access and generates an ECC check bit. The access is routed to the memory (including the check bit). The memory controller stores the data and check bit together in the memory. The bus master initiates a read request for the previously stored data. The access is routed to the memory. The memory controller sends the read data and ECC check bit together to the bus. The bus master performs ECC check bit decoding, performs error detection and correction, and finally reads the correct data and continues to execute the task. The memory controller includes an SRAM controller and a FLASH controller.

[0035] Secondly, this embodiment provides a memory fault-tolerant design method, applied to the aforementioned ECC fault-tolerant structure covering the entire communication path, including: By splicing two 36-bit SRAM memories, a 72-bit data width storage structure is obtained, and 64-bit data and the corresponding 8-bit check code are merged and written into the SRAM memory.

[0036] Furthermore, due to the limitations of FLASH memory's erase and programmability, its fault-tolerance design struggles to achieve error correction, typically only enabling error detection. When an error occurs, an interrupt is triggered to notify the processor to handle the error and ensure data integrity. Unlike FLASH memory, SRAM memory offers greater flexibility in its fault-tolerance design, enabling automatic error correction and data recovery based on error detection. For details, please refer to [link to relevant documentation]. Figure 3 , Figure 3This is a schematic diagram of the fault-tolerant structure of a static random access memory (SRAM) covering the entire communication path. Based on a segmented, block-based power control architecture, this structure achieves a 72-bit data width by concatenating two 36-bit SRAM memories. 64 bits of data are then combined with the corresponding 8-bit checksum and written into the SRAM. This structure not only protects the integrity of the storage and transmission process but also optimizes access timing. Traditional memory EDAC methods bundle checksum encoding, decoding logic, and error indication states together, which affects the transmission timing of the system bus. System bus transmission may be blocked when correcting single-bit errors or reporting uncorrectable errors; however, transmission can be completed normally in error-free situations. This design makes the ECC logic a critical path in the system chip's timing, often limiting the maximum operating frequency of the memory controller. With a fault-tolerant structure covering the entire communication path, the checksum encoding and decoding logic is moved to the master device requesting the bus, making the ECC logic more flexible. Error state judgment can be separated from the system bus cycle termination logic, thereby optimizing data transmission timing. Errors during transmission typically manifest as errors in address, data writing, or data reading between the master and slave devices. Errors in memory typically manifest as the requester returning corrupted data or parity bits. On-chip memory's fault-tolerant structure covering the entire communication path can effectively detect both types of errors and, by fully utilizing the host's time window, optimize system bus timing, thereby improving system chip performance to some extent.

[0037] Furthermore, to improve the reliability of system data transmission and storage, this embodiment employs Hsiao coding to achieve dual protection for data and addresses. Hsiao coding, with a Hamming distance of 4, implements single error correction and double error detection functions. Please refer to [link to relevant documentation]. Figure 4 The H-matrix of Hsiao encoding demonstrates how data bits and address bits participate in the calculation of check bits, ensuring the reliability of data and address transmission and storage. In the design of the H-matrix, 64 data bits and 29 address bits (the high 29 bits of a 32-bit address, minus the low 3 bits corresponding to the 64 data bits) are used, forming a (101, 93) encoding structure, where 93 is the total number of data bits, and 8 check bits are used to generate the final check result. The matrix contains… The symbol indicates that the corresponding data bit or address bit is associated with a specific parity bit via XOR logic. This design further optimizes the parity structure, thereby achieving efficient protection for data and addresses.

[0038] Furthermore, since the ECC encoding scheme uses a 64-bit granularity, when a write operation smaller than 64 bits is performed, a Read-Modify-Write (RMW) operation is triggered, such as... Figure 5 As shown, Figure 5 This section details the process of handling a 16-bit write request using the read-modify-write strategy. First, the master device initiates a 16-bit write request to address 0x4000_0000, writing data as 0x0000_0000_0000_BABE, accompanied by a checksum of 0xC5 covering the entire communication path. Since a 64-bit encoding granularity is used, and this operation only involves 16 bits of data, the memory needs to first read the complete 64 bits of data within the address range and the corresponding checksum. The existing data block x2000_1000_1020_4080 with a checksum of 0x52 is read from address 0x4000_0000 of the RAM (Random Access Memory). The SRAM controller then merges the newly written 16-bit data with the read 64-bit data. First, the remaining 48 bits of data not involved in the original data block are filled with zeros. Next, the controller calculates the updated complete data block and the new checksum by performing an XOR operation on the newly written data, the original data, and the zero-filled data. Finally, the controller writes the updated 64-bit data block and checksum back to the memory target address 0x4000_0000, completing the read-modify-write operation. Furthermore, the read-modify-write strategy typically requires 3 clock cycles to complete one complete operation, such as... Figure 6 As shown, this leads to reduced access efficiency. To improve performance, this embodiment optimizes the read-modify-write process using a pipeline, as follows: Figure 7 As shown in the optimized timing diagram, when continuously writing data less than 64 bits, the clock cycles required for each write are reduced from 3 cycles to 2 cycles by pipelining the original data reading stage and the modified data writing stage. This effectively improves the performance in scenarios involving continuous writing of data less than 64 bits and increases write access efficiency.

[0039] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0040] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An ECC fault-tolerant structure covering the entire communication path, characterized in that, It includes a host module, an interconnect bus, and storage components; the host module is configured with an ECC codec. The host module is used to implement access control to the storage component; The interconnect bus is used to implement access routing between the host module and the storage component, and to establish the connection between the host module and the storage component according to the system address mapping relationship; The host module initiates a data write access, encodes the pre-written data using ECC, and then initiates a write access to the storage unit to transmit the written data and the ECC encoding; after receiving the write access, the interconnect bus routes the access to the corresponding storage unit according to the access address. ECC stands for Error Correction Code.

2. The ECC fault-tolerant structure covering the entire communication path according to claim 1, characterized in that, After the host module initiates a data write access, it includes: The host module encodes the pre-written data using ECC and initiates write access to the storage unit according to the system bus timing to transmit the written data and ECC encoding. After receiving a write access initiated by the host module, the interconnect bus routes the access to the storage component according to the access address. After receiving the write access from the interconnect bus, the storage component stores the data and ECC encoding in the internal storage unit.

3. The ECC fault-tolerant structure covering the entire communication path according to claim 1 or 2, characterized in that, The host module includes a processor, a peripheral host, and a direct memory access controller.

4. The ECC fault-tolerant structure covering the entire communication path according to claim 3, characterized in that, When the host module initiates a data read access, the host module initiates a read access to the storage component according to the system bus timing.

5. The ECC fault-tolerant structure covering the entire communication path according to claim 4, characterized in that, After the host module initiates a data read access, the interconnect bus receives the read access initiated by the host module and routes the read access to the corresponding storage component according to the access address.

6. The ECC fault-tolerant structure covering the entire communication path according to claim 5, characterized in that, After receiving a read access from the interconnect bus, the storage component transmits the read data and ECC encoding to the corresponding host module through the interconnect bus. When the storage component detects that it has received a read access that is less than the bus data bit width, it triggers the read-modify-write strategy.

7. The ECC fault-tolerant structure covering the entire communication path according to claim 6, characterized in that, For the read-modify-write strategy, when the storage component continuously writes data smaller than the bus data width, the clock cycle required for each write is shortened from 3 cycles to 2 cycles by pipelining the read original data stage and the write modified data stage.

8. The ECC fault-tolerant structure covering the entire communication path according to claim 7, characterized in that, In the ECC fault-tolerant structure, during read and write accesses, the host module equipped with an ECC codec uses Hsiao encoding to detect and correct transmission path errors, interconnect bus errors, and internal data or ECC encoding errors of the storage component.

9. The ECC fault-tolerant structure covering the entire communication path according to claim 8, characterized in that, The storage components include static random access memory and / or flash memory.

10. A memory fault-tolerant design method, characterized in that, The ECC fault-tolerant structure covering the entire communication path as described in claim 9 includes: By splicing together two 36-bit data width static random access memories, a 72-bit data width storage structure is obtained, and 64-bit data and the corresponding 8-bit check code are combined and written into the static random access memory.

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