Multi-core FPGA (Field Programmable Gate Array)-oriented logic structure division and netlist optimization collaboration method

By introducing macroscopic physical partitioning constraints into the logic synthesis of multi-core FPGAs, the problem of excessive cross-core interconnects is solved, the system frequency and data throughput are improved, and the performance requirements of high-speed interfaces are met.

CN122287508APending Publication Date: 2026-06-2658TH RES INST OF CETC
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Patent Information

Application Number
CN202610412320.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-03-31
Publication Date
2026-06-26

AI Technical Summary

Technical Problem

Existing multi-chip FPGA systems suffer from excessive cross-chip interconnects due to the separation of logic synthesis and physical partitioning, resulting in low system frequency and inability to meet the timing and performance requirements of high-speed interfaces such as DDR and PCIe.

Method used

In the micro-optimization process of logic synthesis, macro-physical partitioning constraints are introduced. The logic node regions are pre-partitioned using a hypergraph partitioning algorithm. The evaluation criteria of the logic synthesis optimization operator are redefined. Interconnection costs are introduced. An active structural reorganization strategy and a dynamic interconnection penalty mechanism are adopted. The total number of cross-core interconnections is monitored in real time, and the penalty coefficient is dynamically adjusted to prevent constraint failure and achieve closed-loop iteration of partitioning and optimization.

Benefits of technology

It significantly reduces the reliance of multi-core FPGA systems on time-division multiplexing technology, improves operating frequency and data throughput, optimizes resource utilization, and meets the timing and performance requirements of high-speed interfaces.

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Abstract

The invention discloses a logic structure division and netlist optimization collaboration method for a multi-chip FPGA (Field Programmable Gate Array), and belongs to the field of electronic design automation and integrated circuits. According to the method, physical division constraints are introduced in a logic synthesis stage, an interconnection perception comprehensive cost function is established, and the function fuses the area, the time sequence and the cross-core particle interconnection cost. The method comprises the following steps: pre-dividing a netlist by using a hypergraph division algorithm, and anchoring the position of the netlist; in the logical transformation process, screening optimization operators in real time based on the dynamically adjusted interconnection penalty coefficient; a suppression mechanism is executed for a high interconnection cost operation, and active logic cloning and topology reconstruction are executed for a long-distance cross-core path. According to the method, the boundary of traditional logic synthesis and physical division is broken through, through closed-loop iteration of microscopic optimization and macroscopic constraint, the cross-core particle interconnection number is effectively reduced at the source, the wiring congestion risk is remarkably reduced, and the operation frequency and performance of a multi-core particle FPGA system are improved.
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