Parallel implementation method and system of hardware acceleration-based quantum-resistant digital signature algorithm

Abstract

This invention relates to the field of quantum-resistant computing and cryptography, and discloses a hardware-accelerated parallel implementation method and system for quantum-resistant digital signature algorithms. The method includes: mapping a private key matrix to the conductance states of a resistive-switched non-volatile memory array; converting the message to be signed into an input vector and loading it into a row-driven circuit; performing matrix-vector multiplication in situ using the memory array, with the operational current obtained by a column-sensing circuit; performing analog-to-digital conversion, post-processing, and rejection sampling judgment on the current, and outputting the signature result. The system includes a central control module, a resistive-switched memory computing core array, a row-driven circuit module, a column-sensing and conversion module, and a post-processing operator cluster. By adopting the above technical solution, this invention can achieve high-performance, low-power, and low-latency parallel processing of quantum-resistant digital signatures, improving throughput and enhancing deployment feasibility in edge and mobile devices.

Description

Technical Field

[0001] This invention belongs to the field of quantum-resistant computing and cryptography, specifically relating to a hardware-accelerated parallel implementation method and system for quantum-resistant digital signature algorithms. Background Technology

[0002] With the rapid development of quantum computing technology, traditional public-key encryption systems based on large integer factorization and discrete logarithm problems are facing security threats. Quantum-resistant cryptography has become a key area for ensuring future information security. Lattice-based cryptosystems, with their extremely high security strength and relatively superior algorithm performance, have become the mainstream direction of international post-quantum cryptography standardization. They play an irreplaceable role in protecting cloud data privacy and ensuring the security of large-scale network communications.

[0003] Hardware-accelerated quantum-resistant algorithm implementation technology is the core approach to improving the efficiency of digital signatures. It mainly uses application-specific integrated circuits or programmable logic arrays to construct parallel operator processing arrays, thereby accelerating the processing of complex number theory transformations and polynomial multiplication operations in lattice cryptography algorithms. The aim is to improve the throughput of quantum-resistant signature generation and reduce computational latency through customized computing architecture.

[0004] Traditional hardware acceleration techniques for quantum-resistant signature algorithms suffer from several drawbacks: Firstly, the systems often employ a von Neumann architecture with separate computation and storage. When processing massive polynomial coefficient matrices and complex operations in lattice cryptography, frequent data exchange between computation and storage units leads to the memory wall effect, resulting in low hardware resource utilization and system response latency. Secondly, the limited bandwidth of the physical interconnect bus restricts the full release of the hardware system's parallel processing capabilities, causing a mismatch between massive data throughput and bus load. Thirdly, repeated data movement between different storage levels generates significant dynamic power consumption, hindering the efficient application of quantum-resistant cryptographic algorithms in low-power mobile devices. Fourthly, the fixed architecture's computational mode lacks deep coupling with the mathematical structure of lattice cryptography algorithms, failing to resolve access conflicts in matrix-vector multiplication at the physical implementation level. Therefore, this invention proposes a hardware-accelerated parallel implementation method and system for quantum-resistant digital signature algorithms, addressing the shortcomings of traditional hardware acceleration architectures such as high data movement latency, significant memory wall limitations, low energy efficiency, and limited parallelism. Summary of the Invention

[0005] The purpose of this invention is to provide a hardware-accelerated parallel implementation method and system for quantum-resistant digital signature algorithms, which can solve the problems mentioned in the background. Addressing the core structural problems faced by quantum-resistant signature algorithms in hardware implementation, such as storage bandwidth limitations due to the physical separation of computing and storage units, high energy consumption caused by data transfer, and the limitation of parallel processing speed to bus frequency, this invention breaks through the storage wall limitation at the underlying hardware architecture and algorithm mapping mechanism level by deeply coupling the in-memory computing architecture with the lattice-based signature algorithm, achieving high energy efficiency acceleration of quantum-resistant digital signatures.

[0006] To achieve the above objectives, this invention proposes a hardware-accelerated parallel implementation method for quantum-resistant digital signature algorithms, comprising the following steps: S1. Initialize the quantum-resistant signature environment and generate a private key matrix, and map the elements of the private key matrix to the conductance states in the resistive non-volatile memory array. S2. Obtain the message data to be signed, convert it into an input vector through hash operation and polynomial transformation, and load it into the row drive circuit of the resistive non-volatile memory array; S3. Perform in-situ matrix-vector multiplication using the physical characteristics of the resistive non-volatile memory array, and obtain the current result containing the fault-tolerant learning problem by the column sensing circuit. S4. Perform analog-to-digital conversion and post-processing on the current result of the operation, execute the rejection sampling judgment, and finally output the quantum-resistant digital signature result.

[0007] Preferably, step S1 specifically includes the following steps: S11. Configure the parameters for the fault-tolerant learning problem based on lattice theory, and determine the dimension and polynomial coefficient range of the private key matrix; S12. Perform bit-plane splitting on the private key matrix, transforming the high-bit-width coefficients into multiple low-bit-width submatrices; S13. Adjust the resistance value of each storage cell in the resistive variable non-volatile memory array according to the element values ​​of the sub-matrix to realize the hardware solidification of private key data.

[0008] Preferably, step S2 specifically includes the following steps: S21. Perform a hash mapping on the input message to be signed to generate a fixed-length message digest; S22. Map the message digest to a preset lattice space and construct a polynomial coefficient vector that meets the algorithm distribution requirements; S23. Based on the accuracy requirements of the input vector, convert it into multiple sets of corresponding level excitation signals and send them into the resistive non-volatile memory array according to the timing sequence.

[0009] Preferably, step S3 specifically includes the following steps: S31. Apply the voltage signal corresponding to the input vector in parallel to the word lines of the resistive non-volatile memory array; S32. Based on Ohm's law, the voltage of each word line is multiplied with the conductance of the corresponding memory cell, and the current is accumulated on the bit line. S33. Obtain the analog current signal representing the matrix-vector product at the end of the array using Kirchhoff's current law.

[0010] Preferably, step S4 specifically includes the following steps: S41. The analog current signal is converted into a digital quantity using an analog-to-digital converter integrated on the periphery of the array; S42. Perform shift and accumulation compensation on the digital quantity to restore it to a high-precision polynomial result; S43. Combine the preset random noise vector and public key parameters to calculate the candidate signature value and determine whether it meets the threshold condition for rejecting sampling; S44. If it meets the condition, output the signature; if it does not meet the condition, return to step S2 to update the random parameters and recalculate.

[0011] Preferably, the mapping process of the private key matrix specifically includes: splitting each coefficient in the private key matrix into multiple numerical segments of a preset bit width, the preset bit width matching the bit precision that a single resistive variable memory cell can stably express; for each numerical segment, using a differential storage structure, storing it in two adjacent resistive variable memory cells, with one cell representing a positive weight and the other representing a negative weight, and using the conductance difference between the two cells to achieve a unified representation of the sign bit and the numerical value; and performing multiple pulse programming on the array using a preset write verification algorithm to ensure that the conductance deviation of each memory cell is within a specific preset error range.

[0012] Preferably, the level excitation signal conversion process of the input vector specifically includes: adopting a multi-clock-cycle serial input strategy to map each bit of the input vector to a voltage pulse of a specific pulse width or a specific amplitude; driving all rows of the resistive non-volatile memory array in parallel through a row driving circuit in each clock cycle; setting a preset reference voltage branch to compensate for input bias errors caused by device aging or temperature fluctuations, and ensuring that the voltage signal injected into the array maintains a linear proportional relationship with the logic value.

[0013] Preferably, the execution process of the in-situ matrix-vector multiplication operation specifically includes: utilizing the cross-point structure of the resistive non-volatile memory array to achieve parallel arrangement of weights in space, so that the calculation process occurs entirely within the memory cell without moving the private key matrix to the processor cache; during the operation, all memory cells participating in the calculation are in a parallel enabled state, realizing massive multiplication and addition operations within a single cycle; by configuring different turn-on voltages of the selectors, the computation enable control of specific regions in the array is realized, supporting the scheduling of various lattice cryptographic tasks of different scales.

[0014] Preferably, the processing procedure of the column sensing circuit specifically includes: using a low-input-impedance transimpedance amplifier to capture the total current on the bit line in real time; guiding the total current to the sample-and-hold circuit to capture a stable analog current value at a specific sampling moment; and using a dynamic range adaptive algorithm to automatically adjust the gain coefficient of the transimpedance amplifier according to the amplitude of the current to prevent signal saturation or signal-to-noise ratio degradation due to insufficient current during large-scale parallel computing.

[0015] Preferably, the analog-to-digital conversion and post-processing process specifically includes: A high-parallel successive approximation analog-to-digital converter array is used to synchronously convert the current signals output from all bit lines. The converted digital signal is sent to the digital signal processing unit to perform polynomial modular arithmetic and rounding. To address the quantum security requirements in lattice-based signature algorithms, a perturbation vector conforming to a discrete Gaussian or uniform distribution is added to the digital domain. This perturbation vector is generated in real time using a hardware true random number generator to ensure the signature process's resistance to side-channel attacks.

[0016] Preferably, the execution process of the rejection sampling determination specifically includes: based on the security limits in lattice theory, a series of discrimination criteria are preset to detect whether the generated signature candidate value will leak the distribution information of the private key; Calculate the norm of the candidate signature vector and compare it with a preset security threshold; If the candidate signature vector falls within the preset exclusion region, a retry mechanism is triggered, and the system is forced to return to the random number generation stage through control logic.

[0017] Preferably, the hardware-accelerated parallel implementation system for quantum-resistant digital signature algorithms includes: a central control module for coordinating the logical timing and instruction distribution of the entire signature process; a resistive switching memory computing core array, serving as the physical carrier for storing the private key matrix and performing matrix-vector multiplication, comprising a cross-point network composed of multiple resistive switching memory units; a row drive circuit module connected between the central control module and the core array for converting digital input signals into analog voltage pulses; a column sensing and conversion module deployed at the output of the core array for capturing current signals and restoring them to the digital domain calculation results; and a post-processing operator cluster for performing modulo operations, rejection sampling determination, and final signature format packaging.

[0018] Preferably, the resistive variable storage computing core array adopts a modular architecture, where each array block is configured to store a sub-matrix of a specific dimension, and multiple array blocks are cascaded through an interconnect bus to support higher-dimensional lattice polynomial operations.

[0019] Preferably, the post-processing operator cluster integrates a dedicated modular arithmetic unit and a true random number injection interface. Through pipelined parallel design, the post-processing process and the in-memory computation process overlap in the time dimension, further improving the overall throughput.

[0020] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention constructs an in-memory computing architecture based on resistive non-volatile memory, deeply integrating the matrix operation requirements of quantum-resistant signature algorithms with the physical computational characteristics of the storage medium. 2. By embedding the private key matrix in the resistive memory array, massive matrix-vector multiplication operations are completed at the storage location, eliminating frequent data exchanges between the processor and memory in traditional computing architectures, solving the memory wall problem, and reducing system latency and data transfer power consumption by several orders of magnitude. 3. The inherent parallelism of the resistive memory array allows tens of thousands of storage units to participate in computation simultaneously, improving the computational throughput during the generation of quantum-resistant signature algorithms. 4. Through the synergistic effect of the in-memory computing architecture and the lattice cryptography mapping mechanism, this invention achieves high-performance, low-power, and low-latency parallel signature implementation while ensuring strong quantum security, enhancing the deployment feasibility of quantum-resistant algorithms in edge computing and mobile devices. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the overall technical solution architecture proposed in this invention; Figure 2 This is a schematic diagram of the core principle framework of in-situ matrix-vector multiplication based on resistive variable memory array in this invention; Figure 3This is a schematic diagram of the multi-level interaction relationship and data flow between the central control module, the storage and computing core array, and the post-processing operator cluster in this invention; Figure 4 This is a flowchart illustrating the logical flow of the hardware mapping of the private key matrix and the transformation of the input vector stimulus in this invention. Figure 5 This is a flowchart illustrating the logical flow of the current sensing, analog-to-digital conversion, and rejection sampling determination of the calculation results in this invention. Detailed Implementation

[0022] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following description is provided in conjunction with the appendix. Figure 1 To be continued Figure 5 The following is a detailed description of the specific implementation methods, structures, features, and effects of the present invention, as well as preferred embodiments.

[0023] Example 1: This example discloses a hardware-accelerated parallel implementation method for quantum-resistant digital signature algorithms. This method deeply integrates the algorithm logic of fault-tolerant learning problems based on lattice theory with the physical computation characteristics of novel resistive non-volatile memory.

[0024] During step S1, the system enters the initialization phase of the quantum-resistant signature environment. The core task of this phase is to configure the parameters for the fault-tolerant learning problem based on lattice theory, according to a preset security level. The system needs to determine the dimensional information of the private key matrix, including the number of rows and columns. In lattice-based digital signature algorithms, the private key matrix typically consists of polynomial coefficients conforming to a specific distribution. To accommodate the physical constraints of the hardware storage array, this embodiment pre-determines the range of values ​​for the polynomial coefficients, restricting them to a specific integer domain. The system generates a private key matrix, where each element corresponds to a specific polynomial coefficient.

[0025] Steps S11 to S13 are executed during the mapping of the private key matrix to the conductance states in the resistive randomized nonvolatile memory array. To accurately represent the high-bit-width polynomial coefficients at the physical level, the system employs a bit-plane splitting technique. Each high-bit-width coefficient is split into 4 or 8 low-bit-width numerical segments. For example, an 8-bit-width coefficient can be split into four 2-bit numerical segments. Each numerical segment corresponds to the bit precision that the resistive randomized memory cell can stably represent. Through this splitting, the system transforms the large-scale high-bit-width matrix into multiple logically low-bit-width submatrices.

[0026] Based on the element values ​​of these sub-matrices, the system sends a specific programming pulse sequence to the resistive switching non-volatile memory array via row drive circuitry. The resistance value of the resistive switching memory cell changes non-volatilely as the injected charge accumulates. This embodiment uses a multi-iteration write verification algorithm to accurately map the values ​​in the sub-matrices to the conductance values ​​of the corresponding cells. To address the issue of the ± sign of polynomial coefficients, this embodiment introduces a differential memory structure. In the physical array, each set of data is carried by two adjacent resistive switching memory cells. One cell is programmed to represent the conductance of a positive weight, and the other cell is programmed to represent the conductance of a negative weight. The final logical weight is determined by the difference in conductance between the two memory cells. This design not only unifies the representation of positive and negative values ​​but also utilizes the common-mode rejection characteristics of the differential structure to offset conductance drift caused by temperature fluctuations or device aging, ensuring the hardware-level precision of the private key data.

[0027] In step S2, the system begins processing the message data to be signed. Step S21 utilizes a hardware-integrated hash accelerator to extract the message digest of the message to be signed. This process employs a quantum-safe hash algorithm, such as Secure Hash Algorithm Type 3. The input original message undergoes padding, permutation, and absorption processes to ultimately generate a fixed-length message digest. In step S22, the system maps this digest to a preset lattice space. This mapping process involves converting a stream of binary bits into a polynomial coefficient vector that conforms to the algorithm's distribution requirements. To ensure the security of the signature, the constructed polynomial coefficient vector must satisfy specific statistical characteristics; for example, the sum of the absolute values ​​of its coefficients must be within a preset threshold range.

[0028] In step S23, the system converts the input vector into multiple sets of corresponding level excitation signals according to the accuracy requirements. Since the input terminals of the resistive switching memory array are driven by voltage, the system needs to convert the polynomial coefficients in the digital domain into voltage pulses in the analog domain. This embodiment adopts a multi-clock-cycle serial input strategy. For example, if each dimension of the input vector is 4 bits, the system splits it into 4 consecutive clock cycles, each cycle representing 1 bit. Within each cycle, the row drive circuit determines whether to apply a voltage pulse of a preset amplitude to the corresponding word line based on whether the bit is logic 1 or logic 0. To improve linearity, the system also sets up a reference voltage branch, which uses real-time sensing of the output current of the reference cell to adjust the amplitude of the input voltage, ensuring that the voltage signal injected into the array maintains a linear proportional relationship with the logic value.

[0029] In step S3, the system enters the in-situ matrix-vector multiplication stage, which is the core physical calculation step of this invention. In step S31, the modulated voltage signal sequence is applied in parallel to all word lines of the resistive non-volatile memory array. The entire array is no longer just a storage cell, but evolves into a huge analog computing network. In step S32, based on the physical principle of Ohm's law, the voltage excitation on each word line is multiplied by the conductance at the corresponding storage cell. At each intersection, the tiny current flowing through it represents the product of the weight and the input at that point.

[0030] In step S33, according to Kirchhoff's current law, the currents generated by all memory cells on the same bit line are linearly accumulated at the end of the bit line. This process achieves fully parallel addition operations in space. In this way, matrix-vector multiplication, which would normally require thousands of fetch, decode, and execute cycles in a traditional processor, can be completed in just one or a few discharge cycles in a resistive array. All operations occur within the memory cells, and the private key matrix can be computed without leaving the array, physically eliminating the energy consumption and latency caused by data transport. The column sensing circuit captures these analog current signals representing the matrix-vector multiplication results at the end of the array. To prevent signal saturation during large-scale parallel computing, the system employs a low-input-impedance transimpedance amplifier and combines it with a dynamic range adaptive algorithm to adjust the amplification gain in real time according to the amplitude of the current total current, ensuring signal integrity during transmission.

[0031] In step S4, the system performs post-processing and final signature output of the results. In step S41, the high-parallel successive approximation analog-to-digital converter array integrated on the periphery of the array begins operation. This array contains multiple independent analog-to-digital conversion units, capable of synchronously quantizing the analog current output from all bit lines. The quantized digital signal is sent to the post-processing operator cluster. In step S42, for the bit-plane splitting mapping strategy previously used, the digital signal processing unit performs shift-accumulation compensation operations. The system shifts the quantization results corresponding to different bit weights to the left by a preset number of bits, sums them, and restores the high-precision polynomial calculation result.

[0032] In step S43, the system combines a preset random noise vector with public key parameters to calculate candidate signature values ​​using digital logic units. The system must perform a critical rejection sampling decision. This step is to prevent the signature result from leaking the distribution information of the private key. The system calculates the norm of the candidate signature vector, i.e., the square root of the sum of squares of each element in the vector, and compares it with a preset security threshold. It also checks whether the coefficients of the candidate vector fall within a preset rejection region. In step S44, if the decision meets the security criteria, the system packages and outputs the candidate value as the final quantum-resistant digital signature result. If the decision does not meet the requirements, the central control module issues a control command to trigger a retry mechanism. The system instructs the hardware true random number generator to generate a new random seed and returns to step S2 to update the random parameters before restarting the entire calculation process.

[0033] Example 2: This example focuses on describing a hardware-accelerated parallel implementation system for quantum-resistant digital signature algorithms. This system, as the physical carrier for executing the above method, has highly integrated architectural features.

[0034] The system mainly includes a central control module, a resistive variable memory computing core array, a row drive circuit module, a column sensing and conversion module, and a post-processing operator cluster.

[0035] The central control module, serving as the command center of the entire system, consists of a high-performance microprogrammed controller and a timing generator. It is responsible for parsing signature instructions from the upper-level bus and coordinating the logical timing between various submodules. The central control module integrates an instruction queue, enabling pipelined scheduling of multiple tasks and ensuring that while processing the post-processing stage of the current signature, the resistive variable memory array can begin executing the matrix operation for the next signature.

[0036] The resistive-switched memory (RSM) computing core array is the computational core of the system. In this embodiment, the array adopts a modular architecture design. The entire large array is divided into 16 or 32 independent sub-array blocks. Each sub-array block contains 256 rows and 256 columns of RSM cells. This modular design brings flexibility: on the one hand, by shutting down array blocks that do not participate in the computation, standby power consumption can be further reduced; on the other hand, multiple array blocks can be cascaded through an on-chip interconnect bus. For example, when processing higher-dimensional lattice polynomial operations, the system can split the private key matrix and store it in multiple sub-arrays, achieving large-scale computing power expansion through parallel driving and result aggregation. The RSM cells are made of metal oxide materials and have multi-value storage capabilities, capable of expressing 2 to 4 bits of information within a single cell.

[0037] The row driver circuit module is deployed between the central control module and the core array. It includes a high-precision digital-to-analog converter and a signal buffer. The row driver circuit receives the digital excitation signal from the central control module and converts it into a high-frequency voltage signal injected into the word lines according to a preset pulse width modulation or pulse amplitude modulation protocol. To suppress crosstalk between rows, the row driver circuit integrates an isolating switch to ensure that the word lines are fully grounded in the non-selected state.

[0038] The column sensing and conversion module is deployed at the output of the core array. Its core components are an integrated array of sensing amplifiers and a group of analog-to-digital converters. The sensing amplifiers employ a differential topology, enabling them to capture minute current changes on the bit lines in real time. To accommodate the computational accuracy requirements of different algorithms, the analog-to-digital converters are designed with adjustable resolution, supporting dynamic switching between 4 bits and 12 bits. When performing high-security signatures, the system automatically increases the sampling frequency and quantization accuracy.

[0039] The post-processing operator cluster is a hardware acceleration unit specifically optimized for lattice cryptography. It integrates a dedicated modulo operator, capable of high-speed modulo operations over large prime number domains. The cluster also includes a true random number generator based on a physical entropy source. This generator amplifies thermal noise from resistive switching devices or random telegraph noise to generate high-quality random sequences, providing physical security for perturbation vector generation during the signature process. The post-processing operator cluster also includes a norm calculation unit and a logic comparator for executing complex rejection sampling decisions. Through pipelined parallelization, the shift accumulation, modulo operation, and rejection sampling decisions in the post-processing process can overlap in time. The post-processing unit can begin computation as soon as the analog-to-digital converter outputs the first batch of data, without waiting for all bit line conversions to complete; this temporal parallelism further improves the overall system throughput.

[0040] The system's interconnect architecture employs a high-bandwidth crossbar switch design. The central control module can flexibly schedule data between the storage array and the post-processing cluster by configuring a routing table. To improve reliability, the system is also equipped with an error checking and correction module, capable of automatically detecting and correcting bit errors caused by read / write fatigue of the resistive switching memory cells.

[0041] Example 3: This example provides details of a quantum-resistant digital signature implementation optimized for edge computing scenarios, focusing on how to achieve a balance between high performance and low power consumption using the parallel architecture of this invention in a resource-constrained environment.

[0042] In edge computing devices, due to limited energy supply, the system has stringent requirements on power consumption during the computation process. In step S1, the mapping process of the private key matrix employs an asymmetric differential storage strategy. The system does not use two-cell differential storage for all private key coefficients; instead, by analyzing the statistical distribution of the private key coefficients, it only uses a differential structure for sensitive bits with large values ​​that are susceptible to noise interference. For smaller coefficients, a single-cell storage combined with reference current compensation is used. This hybrid storage strategy increases storage density while maintaining computational accuracy and reduces the array's static leakage power consumption.

[0043] To further conserve energy during the execution of step S3, this embodiment introduces a dynamic voltage scaling mechanism. The central control module dynamically adjusts the word line drive voltage based on the urgency of the message to be signed. In non-real-time tasks, the system reduces the word line voltage amplitude to perform weak current calculations within the subthreshold region. Although this slightly increases the integration time of the sensing circuit, it reduces the ohmic losses of the resistive switching unit during the operation. When processing real-time high-priority security verification requests, the system automatically increases the drive level to achieve extremely fast response within a single cycle.

[0044] For the column sensing process, this embodiment employs a charge domain accumulation technique. The bit line current no longer generates a voltage drop through a resistor, but is instead injected into a high-precision integrating capacitor. Within a preset sampling period, the voltage change across the capacitor reflects the result of the multiplication-accumulation operation. This method filters out high-frequency thermal noise and avoids the nonlinear distortion of traditional transimpedance amplifiers under high current conditions.

[0045] In the post-processing stage, to address potential physical side-channel attacks on edge devices, this embodiment introduces masking technology in step S43. A hardware true random number generator generates two complementary mask vectors to randomize intermediate computation results in the digital domain. This prevents external attackers from obtaining any useful information about the private key distribution by monitoring the chip's dynamic power consumption curve. The logic for rejecting sampling is designed to execute in constant time, meaning that the clock cycles consumed are exactly the same regardless of whether the decision is successful or not, eliminating the possibility of timing attacks.

[0046] The system architecture of this embodiment also supports algorithm reconfigurability. By modifying the register configuration in the central control module, the system can flexibly switch between different sets of quantum-resistant signature algorithm parameters. For example, in communication links requiring a higher level of security, the system expands the lattice dimension from 512 to 1024 by cascading multiple resistive array blocks without changing any underlying physical circuitry. This flexibility in hardware and software collaboration enables the present invention to adapt to future evolving quantum-resistant cryptography standards.

[0047] Example 4: This example further details the cascading expansion mechanism and data flow optimization scheme of the present invention when processing ultra-high dimensional lattice vector operations.

[0048] When the size of the private key matrix required by the quantum-resistant signature algorithm exceeds the physical capacity of a single resistive variable memory core array, the system initiates a block-based parallel scheduling scheme. The private key matrix is ​​split into two or more sub-matrix blocks and loaded into different physical array slices. During the initialization phase, the central control module establishes a mapping table between physical addresses and logical coefficients to ensure that each polynomial parameter is accurately allocated to the specified memory unit.

[0049] During the operation triggering phase, the system employs a broadcast triggering mechanism. The row driver circuit module synchronously distributes the digital signal of the input vector to all participating cascaded array slices. Each array slice independently performs local matrix-vector multiplication for its assigned portion. To achieve rapid aggregation of global results, a dedicated analog current addition bus is designed between the outputs of different array slices. The bit line outputs of each slice are connected to the global adder node via controlled interconnect switches, utilizing the inherent physical superposition properties of current to achieve cross-array result fusion without the need for additional digital adders.

[0050] To alleviate the backend processing pressure caused by high parallelism during the data conversion phase, this embodiment introduces a distributed ADC architecture. Each array slice is equipped with local analog-to-digital conversion logic. These local ADCs employ pipelined interleaved sampling technology during the conversion process. While the first slice is making the final decisions on the last few bits of the conversion, the second slice has already begun the front-end sampling and holding. This timing-staggered design smooths out the system's demand on instantaneous power supply current and reduces the interference of power supply ripple on computational accuracy.

[0051] The post-processing operator cluster employs a modular arithmetic strategy based on the divide-and-conquer approach when processing cascaded data. The digital signal processing unit performs preliminary modulo remainder extraction on the multiplication and addition results of each local unit, controlling the numerical range within a small range, before performing global accumulation and secondary remainder calculation. This method reduces the bit width requirement of the digital multiplier-accumulator, thereby reducing the number of logic gates and chip area.

[0052] To address potential process variations in resistive switching memory devices, this embodiment incorporates an adaptive compensation step in step S13. During each power-on initialization, the system automatically invokes a built-in test vector sequence to perform a full scan of the array, measuring the current response curve of each memory cell at a preset voltage. The central control module calculates the gain correction factor for each cell based on the measurement results and stores these factors in a specific configuration register. In subsequent calculations, the digital post-processing unit applies these correction factors in real time, compensating for physical inconsistencies in the devices through digital compensation. This deeply integrated hardware and software calibration mechanism enables resistive switching arrays manufactured using low-cost processes to achieve the numerical accuracy requirements for high-security digital signatures.

[0053] Example 5: This example focuses on describing the logical breakdown and hardware implementation details of the present invention when performing rejection sampling decision, aiming to demonstrate how to describe the complex probability decision process using pure engineering language without using any mathematical formulas.

[0054] In step S43, the generated signature candidate value consists of a set of discrete polynomial coefficients. To ensure that the signature does not contain any sensitive statistical features related to the private key, the system must verify that the candidate vector is consistent with a preset target distribution in terms of mathematical distribution. In hardware implementation, the system initiates a vector norm detection process. Each polynomial coefficient is fed into a squaring unit, which obtains the square value of the coefficient through a lookup table or fast multiplication logic. All square values ​​are summed sequentially or in parallel in an accumulation chain. The resulting sum represents a measure of the vector length.

[0055] The system feeds this sum into a large-bit-width digital comparator. The other end of the comparator is connected to a read-only register storing a security threshold. If the sum exceeds this threshold, it indicates that the signature vector deviates from the preset secure distribution area, posing a risk of leaking private key information. The comparator will immediately output a rejection signal to the central control module.

[0056] The system also executes coefficient range monitoring logic in parallel. The absolute value of each coefficient is extracted and compared in real time with a preset maximum offset. If any coefficient exceeds this allowed range, the logic gate will trigger a failure flag. To enhance quantum security, the system also performs frequency statistical analysis on the signature vector. Using a hardware histogram calculation unit, the system calculates the frequency of each value in the polynomial and matches it with a preset distribution template. If the statistical distribution exhibits non-uniformity or an unexpected discrete Gaussian shape, the decision unit will also issue a retry instruction.

[0057] The central control module will only release the lock on the signature output interface when norm detection, range monitoring, and frequency statistics all pass. During this process, to prevent computational problems caused by the complexity of the decision logic, all decision submodules are implemented using hard-wired logic gates, achieving processing speeds of hundreds of megahertz. This fast decision mechanism based on hardware logic arrays ensures that even in extreme cases where multiple consecutive rejections require recalculation, the system can maintain a stable signature generation throughput.

[0058] When finally outputting the signature, the system will also call the hash operator to perform a final integrity check on the signature content, and encapsulate the check code and signature data in a standard format, and send them to the host system through a universal asynchronous receiver or high-speed peripheral expansion bus.

[0059] Example 6: This example describes the hardware redundancy and self-healing mechanism of the present invention in improving the reliability of quantum-resistant digital signature systems.

[0060] Considering the potential degradation of the tolerance of resistive non-volatile memory under frequent read and write operations, this embodiment incorporates a dynamic weight migration mechanism. The central control module has a built-in write counter that records the number of programming operations for each array shard. When the cumulative number of operations for a subarray block reaches a preset warning threshold, the system automatically initiates a private key migration procedure. This procedure reprograms the currently fixed private key matrix to another backup array block with a better physical state and simultaneously updates the routing table. The entire migration process is completed silently in the background, without affecting ongoing signing tasks.

[0061] In step S3, to prevent calculation errors caused by transient electromagnetic interference, a check column design is introduced in the resistive variable array. During each matrix-vector multiplication cycle, the system calculates a check value reflecting the characteristics of the current row vector using a dedicated check column and compares it with the expected check value calculated in the digital domain. If a logical mismatch is found between the analog calculation result and the check value, the system automatically discards the current calculation result and triggers a local resampling or a full recalculation.

[0062] In environments with unstable power supply, this system also features a state snapshot function. Because the resistive random access memory (RRAM) is non-volatile, the private key data and intermediate computation states stored in the array will not be lost even in the event of a sudden power outage. Once power is restored, the central control module can quickly restore the computation state by reading the breakpoint information stored in the non-volatile state register, avoiding the repeated execution of large-scale complex calculations and improving the reliability of applications in the field or on mobile devices.

[0063] In summary, this invention constructs an in-memory computing architecture based on resistive random access memory arrays and designs a deep hardware mapping and post-processing optimization scheme to address the mathematical characteristics of quantum-resistant signature algorithms. This not only solves the memory wall problem under the von Neumann architecture but also achieves computational efficiency and system robustness while ensuring strong quantum security through multi-level parallelization and redundancy design. This purely hardware-driven acceleration scheme provides solid technical support for the application of quantum-resistant cryptography in the fields of IoT, edge computing, and large-scale secure communication.

[0064] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to obtain equivalent embodiments with equivalent changes without departing from the scope of the technical solution of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the technical solution of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. A hardware-accelerated parallel implementation method for a quantum-resistant digital signature algorithm, characterized in that, Includes the following steps: Step S1: Initialize the quantum-resistant signature environment and generate a private key matrix. The polynomial coefficients in the private key matrix are converted into multiple numerical fragments through a bit-plane splitting strategy, and the numerical fragments are mapped to the physical conductance states in the resistive non-volatile memory array. A differential storage structure is used to store each set of numerical fragments in two adjacent resistive memory cells. The conductance difference between the two resistive memory cells is used to characterize the corresponding logical weights. The resistive memory cells are pulse-programmed using a write verification algorithm to solidify the private key data. Step S2: Obtain the message data to be signed, generate a message digest through hash operation and convert it into a polynomial coefficient vector that conforms to the lattice theory distribution requirements as an input vector. Then, the input vector is converted into multiple sets of corresponding level excitation signal sequences through the row driving circuit and loaded onto the word lines of the resistive non-volatile memory array according to a preset timing sequence. Step S3: Perform in-situ matrix-vector multiplication using the physical characteristics of the resistive non-volatile memory array. Based on Ohm's law, multiply the voltage of each word line with the conductance of the corresponding memory cell. Based on Kirchhoff's current law, accumulate the current at the end of the bit line. Capture the analog current signal representing the matrix-vector multiplication result in real time through the column sensing circuit. Step S4: Use an analog-to-digital converter to convert the analog current signal into a digital signal, and perform shift accumulation compensation on the digital signal according to the bit plane splitting strategy to restore the polynomial calculation result. Combine the preset random parameters to calculate the signature candidate value, and perform a rejection sampling judgment based on a security threshold on the signature candidate value. When the judgment result indicates that the private key distribution information is not disclosed, output the quantum-resistant digital signature result.

2. The method for parallelizing a hardware-accelerated quantum-resistant digital signature algorithm according to claim 1, characterized in that, The process of initializing the quantum-resistant signature environment in S1 includes: Configure parameters for the fault-tolerant learning problem based on lattice theory, determine the dimensional information of the private key matrix and the range of values ​​for the polynomial coefficients, and restrict each element of the private key matrix to the integer field; The bit-plane splitting strategy specifically includes: splitting each high-bit-width coefficient into multiple low-bit-width numerical segments, wherein the bit width of each numerical segment matches the preset bit expression precision of a single resistive variable memory cell, thereby transforming a large-scale high-bit-width matrix into multiple logically low-bit-width sub-matrices.

3. The method for parallelizing a hardware-accelerated quantum-resistant digital signature algorithm according to claim 2, characterized in that, The process of mapping to conductance state in step S1 further includes: In the differential memory structure, one resistive switching memory cell is programmed to represent the conductance of a positive weight, and the other resistive switching memory cell is programmed to represent the conductance of a negative weight. The common-mode rejection characteristics of the differential structure are used to offset the conductance drift caused by temperature fluctuations or device aging. The pulse programming process sends a controlled programming pulse sequence to the resistive variable non-volatile memory array through the row driving circuit, and combines iterative write verification logic to ensure that the final conductance deviation of each resistive variable memory cell is within a preset error range.

4. The method for parallelizing the hardware-accelerated quantum-resistant digital signature algorithm according to claim 3, characterized in that, The process of converting the vector into an input vector in step S2 includes: The message digest is extracted from the message to be signed using a hardware-integrated hash operation accelerator. A fixed-length message digest is generated using a hash algorithm that meets the requirements of quantum security. Based on the mapping relationship between binary bit stream and lattice space coefficients, a polynomial coefficient vector is constructed in which the sum of the absolute values ​​of each coefficient is within a preset threshold range. The loading process of the level excitation signal sequence adopts a multi-clock-cycle serial input strategy, which maps each bit of the input vector to a voltage pulse with a specific pulse width or a specific amplitude, and drives all rows of the resistive non-volatile memory array in parallel through the row driving circuit in each clock cycle.

5. The method for parallelizing a hardware-accelerated quantum-resistant digital signature algorithm according to claim 4, characterized in that, The conversion process of the level excitation signal in step S2 also includes: By setting up a reference voltage branch, the voltage amplitude of the injected word line is adjusted by sensing the output current of the reference cell in real time and feeding back the adjustment; thus, linear proportional compensation between the input voltage signal and the logic value is achieved. The execution process of the in-situ matrix-vector multiplication operation in step S3 includes: using the cross-point structure of the resistive non-volatile memory array to realize the parallel arrangement of weights in space, so that the calculation process occurs entirely within the memory cell. During the operation, all the resistive variable memory cells involved in the calculation are in a parallel on-state, and the calculation enable control of the region in the array is achieved by configuring the turn-on voltage of the selector.

6. The method for parallelizing a hardware-accelerated quantum-resistant digital signature algorithm according to claim 5, characterized in that, The processing procedure of the column sensing circuit in step S3 includes: A low-input-impedance transimpedance amplifier is used to capture the total current on the bit line and guide the total current to a sample-and-hold circuit to capture a stable analog current value at a preset sampling time. The gain coefficient of the transimpedance amplifier is adjusted in real time according to the current bit line current amplitude to prevent signal saturation during large-scale parallel computing and maintain signal integrity during transmission. For edge computing environments, the column sensing circuit uses charge domain accumulation technology to inject bit line current into the integrating capacitor, and the voltage change on the capacitor within a preset sampling period represents the result of the multiplication and addition operation.

7. The method for parallelizing a hardware-accelerated quantum-resistant digital signature algorithm according to claim 6, characterized in that, The analog-to-digital conversion and post-processing process in step S4 includes: A high-parallel successive approximation analog-to-digital converter array is used to synchronously quantize the current signals output from all bit lines. According to the bit plane splitting strategy, the quantization results corresponding to different bit weights are shifted to the left by a preset number of bits and then summed. The process of restoring the polynomial calculation result also includes performing modular arithmetic in the large prime number domain; in order to resist side-channel attacks, a perturbation vector conforming to a discrete Gaussian distribution or a uniform distribution is added to the digital domain. The perturbation vector is generated in real time by a hardware true random number generator, and the intermediate calculation results are randomized by combining masking technology.

8. The method for parallelizing a hardware-accelerated quantum-resistant digital signature algorithm according to claim 7, characterized in that, The execution process of the rejection sampling determination in step S4 includes: The vector norm detection is performed using hardware logic units. The square value of each coefficient is obtained through the square operation unit and then summed in parallel to obtain a metric representing the length of the vector. The metric value is fed into a digital comparator and compared with the security threshold stored in a read-only register; At the same time, the execution coefficient range monitoring logic extracts the absolute value of each coefficient and compares it with the preset maximum offset in real time, and uses the hardware histogram calculation unit to count the frequency of numerical distribution. If any detection item does not meet the preset security limit, a retry mechanism is triggered, instructing the hardware true random number generator to generate a new random seed and return to step S2.

9. A hardware-accelerated parallel implementation system for a quantum-resistant digital signature algorithm, characterized in that, include: The central control module, consisting of a microprogram controller and a timing generator, is used to parse signed instructions and coordinate the system logic timing. The resistive variable storage computing core array, as the physical carrier for storing the private key matrix and performing in-situ matrix-vector multiplication, includes a cross-point network composed of multiple resistive variable storage units, and the resistive variable storage units adopt a differential storage structure to represent the private key weights. The line drive circuit module, connected between the central control module and the core array, includes a digital-to-analog converter circuit and a signal buffer, used to convert digital input vectors into analog level excitation signals; The column sensing and conversion module, deployed at the output of the core array, includes a transimpedance amplifier array and an analog-to-digital converter group, and is responsible for capturing the bit line current signal and restoring it to the digital domain operation result; The post-processing operator cluster includes a modulus arithmetic unit, a shift-accumulate unit, a norm calculation unit, and a hardware true random number generator, used to perform modulus compensation, rejection sampling determination, and perturbation injection.

10. A hardware-accelerated parallel implementation method for a quantum-resistant digital signature algorithm, characterized in that... The system implements the parallelization of the quantum-resistant digital signature algorithm based on hardware acceleration as described in any one of claims 1-9.

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