A memory, a method of operating a memory, and a method of manufacturing a memory

Abstract

This application discloses a memory, a method for operating the memory, and a method for fabricating the memory, belonging to the field of semiconductor devices. The memory includes: a memory array, which includes multiple memory cells; each memory cell includes a substrate, in which a source region, a channel region, and a drain region are sequentially disposed along a first direction; a first gate structure, a spacer layer, and a second gate structure are sequentially disposed on the surface of the channel region along the first direction; both the source and drain regions are in ohmic contact with the channel region; the first gate structure, source region, drain region, and channel region constitute a logic transistor; the second gate structure, source region, drain region, and channel region constitute a storage transistor; the storage transistor and the logic transistor share the source region, drain region, and channel region, and are connected in series through the channel region. By sharing the source region, drain region, and channel region, and isolating them through the spacer layer, crosstalk suppression is ensured while area reduction and power consumption reduction are achieved.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and in particular to a memory, a method for operating the memory, and a method for fabricating the memory. Background Technology

[0002] Ferroelectric field-effect transistors (FeFETs) can form basic memory cells and hold great promise in memory architectures. Memory arrays built on FeFETs require precise selection of target memory cells during read and write operations, while ensuring that unselected non-target memory cells are not interfered with. To reduce crosstalk, existing technologies have proposed memory cell structures containing multiple transistors, such as 1T (Single-Transistor) and 2T (Two-Transistor) structures. The 2T structure typically uses additional logic transistors to assist selection and reduce crosstalk risk. However, achieving both miniaturization of memory cell area and reduction of power consumption while maintaining crosstalk suppression remains a significant challenge for current technology. Summary of the Invention

[0003] The purpose of this application is to provide a memory, a method for operating the memory, and a method for fabricating the memory, thereby achieving both miniaturization of the memory cell area and reduction of power consumption while ensuring crosstalk suppression.

[0004] To achieve the above objectives, this application provides a memory, including: a memory array, the memory array including a plurality of memory cells;

[0005] The memory cell includes a substrate in which a source region, a channel region, and a drain region are sequentially disposed along a first direction. A first gate structure, a spacer layer, and a second gate structure are sequentially disposed on the surface of the channel region along the first direction. The source region and the drain region are both in ohmic contact with the channel region.

[0006] The first gate structure, the source region, the drain region, and the channel region constitute a logic transistor;

[0007] The second gate structure, the source region, the drain region, and the channel region constitute a storage transistor;

[0008] The storage transistor and the logic transistor share the source region, the drain region, and the channel region, and are connected in series through the channel region.

[0009] Optionally, the memory includes: a plurality of signal lines; the signal lines include a first word line, a second word line, a source line, and a bit line;

[0010] The first gate structure of all the memory cells in the same row shares the same first word line;

[0011] The second gate structure of all memory cells in the same row shares the same second word line; the first word line and the second word line are arranged in parallel and both extend along the row direction;

[0012] The source regions of all the memory cells in the same column share the same source line;

[0013] The drain regions of all the memory cells in the same column share the same bit line; the bit line is arranged parallel to the source line and extends along the column direction.

[0014] Optionally, the channel region is made of a semiconductor material;

[0015] And / or, the spacer layer is made of an insulating material.

[0016] Optionally, the logic transistor is a MOSFET; the first gate structure includes a first gate oxide layer and a first gate disposed sequentially along a second direction;

[0017] And / or, the storage transistor is a FeFET; the second gate structure includes a second gate oxide layer, a ferroelectric layer and a second gate sequentially disposed along the second direction.

[0018] To achieve the above objectives, this application also provides a method for operating a memory, applied to the aforementioned memory, characterized in that it includes:

[0019] When performing a target operation on a target memory cell in the memory, a current path is formed between the logic transistor and the storage transistor in the target memory cell through a shared channel region, and the current path between the logic transistor and the storage transistor in all non-target memory cells is blocked.

[0020] Optionally, the target operation is a write operation; when performing the target operation on the target memory cell, a current path is formed between the logic transistor and the storage transistor in the target memory cell through a shared channel region, and the current path between the logic transistor and the storage transistor in all non-target memory cells is blocked, including:

[0021] An enable voltage is applied to the first word line of the target row, a programming voltage is applied to the second word line of the target row, and a first source bias voltage and a first drain bias voltage are applied to the source line and bit line of the target column, respectively, so that the logic transistor and the storage transistor in the target memory cell form the current path through the shared channel region, so that the storage transistor in the target memory cell undergoes polarization flipping to complete the data writing;

[0022] Apply a shutdown voltage to the first word line of the non-target row, place the source line and the bit line of the non-target column at a floating potential, and block the current path between the logic transistor and the memory transistor in all the non-target memory cells;

[0023] Maintain all signal lines at their current voltage for a preset time until the target memory cell completes the write operation.

[0024] Optionally, the target operation is a read operation; when performing the target operation on the target memory cell, a current path is formed between the logic transistor and the storage transistor in the target memory cell through a shared channel region, and the current path between the logic transistor and the storage transistor in all non-target memory cells is blocked, including:

[0025] An enable voltage is applied to the first word line of the target row, a read voltage is applied to the second word line of the target row, and a second source bias voltage and a second drain bias voltage are applied to the source line and bit line of the target column, respectively, so that the logic transistor and the storage transistor in the target memory cell form the current path through the shared channel region to read the data stored in the target memory cell.

[0026] A shutdown voltage is applied to the first word line of the non-target row, and a third source bias voltage and a third drain bias voltage are applied to the source line and the bit line of the non-target column, respectively, to block the current path between the logic transistor and the memory transistor in all the non-target memory cells.

[0027] By detecting the current value on the bit line of the target column, the type of stored data is determined. After the detection is completed, the target storage unit completes the read operation.

[0028] Optionally, before performing the target operation on the target memory cell in the memory, and before forming a current path between the logic transistor and the storage transistor in the target memory cell through a shared channel region, and blocking the current path between the logic transistor and the storage transistor in all non-target memory cells, the method further includes:

[0029] Initialize the potentials of the first gate structure, the second gate structure, the source region, and the drain region in all memory cells of the memory.

[0030] Optionally, when performing the target operation on the target memory cell in the memory, after forming a current path between the logic transistor and the storage transistor in the target memory cell through a shared channel region and blocking the current path between the logic transistor and the storage transistor in all non-target memory cells, the method further includes:

[0031] The potentials of the first gate structure, the second gate structure, the source region, and the drain region in all memory cells of the memory are reset to their initial states.

[0032] To achieve the above objectives, this application also provides a method for fabricating a memory, comprising:

[0033] At least one channel region is formed in the substrate;

[0034] A source region and a drain region are formed in the substrate on both sides of each channel region along the first direction, respectively;

[0035] A first gate structure, a spacer layer, and a second gate structure are formed sequentially along the first direction on the surface of each channel region to obtain the memory.

[0036] Obviously, the memory provided in this application achieves isolation between storage transistors and logic transistors by using a spacer layer to replace the shallow trench isolation structure, rather than physically separating device regions. By sharing the source region, drain region, and channel region, the redundant structure of the device is reduced, thereby significantly reducing the size of the memory cell. This solves the problem of large space occupation by the shallow trench isolation structure in the prior art. Compared with the 2T structure in the prior art, the area of ​​a single memory cell is reduced by about 30%, which significantly improves the integration density of the memory array.

[0037] Meanwhile, the storage transistor and the logic transistor are directly connected in series through a shared channel region. On the one hand, the logic transistor assists the storage transistor in selection, ensuring the effect of suppressing crosstalk. On the other hand, since no additional metal wires are needed for connection, the current transmission path is shortened, thereby reducing the path resistance, reducing the power consumption of read and write operations, and improving the response speed.

[0038] This application also provides a method for operating a memory and a method for fabricating a memory, which have the aforementioned beneficial effects. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the storage unit structure in a traditional 2T architecture;

[0041] Figure 2 This is a schematic diagram of the structure of a storage unit provided in an embodiment of this application;

[0042] Figure 3 This is a schematic diagram of the structure of a storage array provided in an embodiment of this application;

[0043] Figure 4 A schematic flowchart of a write operation of a memory provided in an embodiment of this application;

[0044] Figure 5 This is a schematic flowchart of a read operation of a memory provided in an embodiment of this application.

[0045] The annotations in the attached figures are explained as follows:

[0046] 1-Substrate; 2-Logic transistor; 3-Memory transistor; 31-FeFET; 4-Source region; 5-Drain region; 6-Gate structure; 61-First gate structure; 611-First gate oxide layer; 612-First gate; 62-Second gate structure; 621-Second gate oxide layer; 622-Ferroelectric layer; 623-Second gate; 7-Shallow trench isolation; 8-Channel region; 9-Spacer layer; 10-First contact hole; 11-Second contact hole. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0048] In the field of semiconductor memory, ferroelectric field-effect transistors (FeFETs) have become a research hotspot in embedded memory due to their advantages such as non-volatility, high density, high speed, low power consumption, and compatibility with complementary metal-oxide-semiconductor (CMOS) processes. FeFETs realize data storage through the polarization state of the gate ferroelectric layer, and a single transistor can constitute a basic memory cell, showing significant potential in memory architecture design.

[0049] In existing memory technologies, memory arrays require signal lines such as word lines (WL), bit lines (BL), and source lines (SL) to perform addressing and read / write operations on memory cells. For FeFET memory arrays, when performing read / write operations on a target memory cell, the voltage state of each signal line needs to be controlled to cause the FeFET of the target cell to undergo polarization switching (write operation) or present a specific conductivity state (read operation), while non-target memory cells need to remain in their original state undisturbed.

[0050] To improve the stability and reliability of memory arrays and reduce crosstalk during read and write operations, existing technologies have proposed memory cell structures containing multiple transistors, such as 1T (single transistor) and 2T (dual transistor) structures. The 2T structure typically uses additional logic transistors to assist in selection, thereby reducing the risk of crosstalk. Specific technical solutions are as follows... Figure 1 As shown: FeFET31 and logic transistor2 have independent source regions 4, drain regions 5 and gate structures 6, and are isolated from each other by shallow trench isolation 7 (STI), and the source region 4 of FeFET31 and the drain region 5 of logic transistor2 are connected in series by metal wires or additional contact holes.

[0051] Although the 2T structure can guarantee crosstalk suppression, it still has the following problems:

[0052] (1) Large memory cell area: The existing technology uses STI7 structure to isolate FeFET31 and logic transistor2. STI7 structure requires a certain space of substrate1, and the source, drain and channel regions8 of the two transistors need to be fabricated separately, resulting in a large lateral size of a single memory cell, which is not conducive to high-density integration and area miniaturization of memory array.

[0053] (2) Large current path loss: Since FeFET31 and logic transistor 2 are isolated by STI7, their series connection needs to be achieved through metal wires or additional contact holes, which increases the resistance of the current transmission path, resulting in increased power consumption during read and write operations, and may affect the signal transmission speed.

[0054] Therefore, this application provides a memory that, by changing the device isolation method and signal connection relationship, significantly reduces the area of ​​the memory cell and increases the integration density of the memory array while ensuring the suppression of read / write crosstalk; at the same time, it optimizes the current transmission path of the memory cell, reduces the path resistance, reduces read / write power consumption, and improves the response speed of memory operations.

[0055] Please refer to Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of the structure of a storage unit provided in an embodiment of this application. Figure 3 This application provides a schematic diagram of the structure of a storage array according to an embodiment of the present application. The memory provided in this application embodiment may include: a storage array, the storage array comprising multiple storage cells;

[0056] The memory cell includes a substrate 1, in which a source region 4, a channel region 8 and a drain region 5 are sequentially disposed along a first direction. A first gate structure 61, a spacer layer 9 and a second gate structure 62 are sequentially disposed on the surface of the channel region 8 along the first direction. The source region 4 and the drain region 5 are both in ohmic contact with the channel region 8.

[0057] The first gate structure 61, the source region 4, the drain region 5, and the channel region 8 constitute the logic transistor 2;

[0058] The second gate structure 62, the source region 4, the drain region 5, and the channel region 8 constitute the storage transistor 3;

[0059] Storage transistor 3 and logic transistor 2 share source region 4, drain region 5 and channel region 8, and are connected in series through channel region 8.

[0060] This embodiment does not limit the specific type of substrate 1, and it can be determined according to the actual situation. In one possible implementation, substrate 1 can be a P-type silicon substrate 1 or an N-type silicon substrate 1.

[0061] It should be noted that in this embodiment, the first direction refers to the direction parallel to the surface of substrate 1, and the second direction refers to the direction away from the surface of substrate 1.

[0062] In one possible embodiment, the source region 4, the channel region 8, and the drain region 5 can all be located on the top of the substrate 1, and the surfaces of the source region 4, the channel region 8, and the drain region 5 can all be flush with the surface of the substrate 1 on the same side.

[0063] In this embodiment, the channel region 8 is located between the source region 4 and the drain region 5. It should be noted that in this embodiment, a single channel region 8 is provided between each group of source regions 4 and drain regions 5. This channel region 8 is shared by the storage transistor 3 and the logic transistor 2 and does not need to be fabricated separately. This embodiment does not limit the specific type of channel region 8, as long as it can ensure that carriers can be conducted under the voltage control applied by the gate structure 6. In one possible implementation, the channel region 8 can be made of a semiconductor material.

[0064] In this embodiment, source region 4 is located on one side of channel region 8 along a direction parallel to the surface of substrate 1, and drain region 5 is located on the other side of channel region 8 along a direction parallel to the surface of substrate 1. This embodiment does not limit the specific types of source region 4 and drain region 5, and they can be determined according to actual conditions. In one possible implementation, both source region 4 and drain region 5 can be highly doped regions.

[0065] In this embodiment, the first gate structure 61, the spacer layer 9, and the second gate structure 62 are all located on the surface of the channel region 8, and the spacer layer 9 is located between the first gate structure 61 and the second gate structure 62. This embodiment does not limit the specific type of spacer layer 9, as long as it can replace the traditional STI structure and achieve electrical isolation between the first gate structure 61 and the second gate structure 62. In one possible implementation, the spacer layer 9 can be made of an insulating material. This embodiment does not limit the specific height of the spacer layer 9, as long as it can cover the overlapping area of ​​the storage transistor 3 and the logic transistor 2. In one possible implementation, the height of the spacer layer 9 can be equal to the maximum height of the storage transistor 3 and the logic transistor 2.

[0066] This embodiment does not limit the specific type of logic transistor 2, as long as it can achieve gating control. In one possible implementation, the logic transistor 2 can be a MOSFET; the first gate structure 61 includes a first gate oxide layer 611 and a first gate 612 sequentially disposed along the second direction. The first gate oxide layer 611 can be made of SiO2 material, and the first gate 612 can include a polysilicon gate or a metal gate.

[0067] This embodiment does not limit the specific type of storage transistor 3, as long as it can store data. In one possible implementation, the storage transistor 3 can be a FeFET 31; the second gate structure 62 includes a second gate oxide layer 621, a ferroelectric layer 622, and a second gate 623 sequentially disposed along a second direction. The second gate oxide layer 621 can be made of SiO2 material or a high-k (dielectric constant) dielectric material, the ferroelectric layer 622 can be made of HfO2-based ferroelectric material, and the second gate 623 can include a polysilicon gate or a metal gate.

[0068] In this embodiment, the first gate structure 61 is located on one side of the spacer layer 9 along the direction parallel to the surface of the substrate 1. The first gate oxide layer and the first gate in the first gate structure 61 are sequentially arranged along the direction away from the surface of the substrate 1. The second gate structure 62 is located on the other side of the spacer layer 9 along the direction parallel to the surface of the substrate 1, and is symmetrically distributed on both sides of the spacer layer 9 with the first gate structure 61. The second gate oxide layer 621, the ferroelectric layer 622 and the second gate 623 in the second gate structure 62 are sequentially arranged along the direction away from the surface of the substrate 1.

[0069] This embodiment does not limit the specific control method of the memory cell, as long as the selection and operation of the target memory cell can be achieved. In one possible implementation, the memory may include: multiple signal lines; the signal lines include a first word line, a second word line, a source line, and a bit line;

[0070] All memory cells in the same row share the same first word line;

[0071] The second gate structure 62 of all memory cells in the same row shares the same second word line; the first word line and the second word line are arranged in parallel and both extend along the row direction;

[0072] All memory cells in the same column share the same source line in their source region 4.

[0073] The drain regions 5 of all memory cells in the same column share the same bit line; the bit line is arranged parallel to the source line and extends along the column direction.

[0074] It should be noted that this embodiment designs a corresponding read / write voltage control strategy based on this structure to effectively suppress read / write crosstalk of non-target memory cells. For details, please refer to the following embodiments, which will not be repeated here.

[0075] In one possible implementation, the source region 4 can be connected to the source line through the first contact hole 10; the drain region 5 can be connected to the bit line through the second contact hole 11.

[0076] Based on the above embodiments, this application achieves isolation between storage transistors and logic transistors by replacing shallow trench isolation structures with spacer layer isolation, rather than physically separating device regions. By sharing the source region, drain region, and channel region, the redundant structure of the device is reduced, thereby significantly reducing the size of the storage cell. This solves the problem of large space occupation by shallow trench isolation structures in the prior art. Compared with the 2T structure in the prior art, the area of ​​a single storage cell is reduced by about 30%, significantly improving the integration density of the storage array.

[0077] Meanwhile, the storage transistor and the logic transistor are directly connected in series through a shared channel region. On the one hand, the logic transistor assists the storage transistor in selection, ensuring the effect of suppressing crosstalk. On the other hand, since no additional metal wires are needed for connection, the current transmission path is shortened, thereby reducing the path resistance, reducing the power consumption of read and write operations, and improving the response speed.

[0078] This application also provides a method for operating a memory, applied to the aforementioned memory, which may include:

[0079] When performing a target operation on a target memory cell, a current path is formed between the logic transistor and the storage transistor in the target memory cell through a shared channel region, and the current path between the logic transistor and the storage transistor in all non-target memory cells is blocked.

[0080] It should be noted that, in this embodiment, the target storage unit refers to the storage unit in which the target operation is to be performed among all storage units, and the non-target storage unit refers to the storage unit in which the target storage unit is located. The row in which the target storage unit is located is the target row, and the rows in which the target storage unit is located are non-target rows. The row in which the target storage unit is located is the target column, and the columns in which the target column is located are non-target columns.

[0081] In one possible implementation, before performing a target operation on a target memory cell in the memory, and before forming a current path between the logic transistors and storage transistors in the target memory cell through a shared channel region and blocking the current path between the logic transistors and storage transistors in all non-target memory cells, the process may further include: initializing the potentials of the first gate structure, second gate structure, source region, and drain region in all memory cells of the memory. It should be noted that in this embodiment, by initializing the potentials of all memory cells before performing the target operation, the entire memory array is placed in a stable initial state, which ensures the stability of subsequent target operations.

[0082] This embodiment does not limit the specific initialization method, as long as it ensures that the entire memory array is in a stable initial state. In one possible implementation, a first initial voltage can be applied to all first word lines, a second initial voltage can be applied to all second word lines, a source initial voltage can be applied to all source lines, and a drain initial voltage can be applied to all bit lines, so that the potential of all signal lines is in the initial state. This embodiment does not limit the specific values ​​of the first initial voltage, second initial voltage, source initial voltage, and drain initial voltage, as long as it ensures that the entire memory array is in a stable initial state, and the specific values ​​can be determined according to the actual situation.

[0083] In one possible implementation, when performing a target operation on a target memory cell, after forming a current path between the logic transistor and the storage transistor in the target memory cell through a shared channel region and blocking the current path between the logic transistor and the storage transistor in all non-target memory cells, the process may further include: resetting the potentials of the first gate structure, the second gate structure, the source region, and the drain region in all memory cells to their initial states. It should be noted that by resetting the potentials of all memory cells to their initial states after performing the target operation, this embodiment provides a unified initial condition for the next target operation, thereby improving the overall operational stability and repeatability of the memory.

[0084] It should be noted that the reset operation in this embodiment refers to resetting the potential of the signal line to its initial state, rather than resetting the storage state. This embodiment does not limit the specific reset method, as long as it ensures that the potential of all storage cells can be reset to the initial state. The specific method can be determined based on the actual initial state.

[0085] This embodiment does not limit the specific type of the target operation, which can be determined according to the actual situation. In one possible implementation, the target operation may include a write operation or a read operation. It should be noted that different operations require different control methods.

[0086] In one possible implementation, when the target operation is a write operation, the control method may include:

[0087] An enable voltage is applied to the first word line of the target row, a programming voltage is applied to the second word line of the target row, and a first source bias voltage and a first drain bias voltage are applied to the source line and bit line of the target column, respectively, so that the logic transistors and storage transistors in the target memory cell form a current path through a shared channel region, so that the storage transistors in the target memory cell undergo polarization switching, and data writing is completed.

[0088] Apply a shutdown voltage to the first word line of the non-target row, place the source line and bit line of the non-target column at a floating potential, and block the current path between the logic transistor and the storage transistor in all non-target memory cells.

[0089] Maintain all signal lines at the current voltage for a preset time until the target memory cell completes the write operation.

[0090] In this embodiment, the logic transistors of the target row are connected to the same first word line. Applying a turn-on voltage to this first word line controls the voltage of the first gate of the logic transistors to the turn-on voltage, thereby turning on the logic transistors of the target row. This embodiment does not limit the specific value of the turn-on voltage, as long as it ensures that the logic transistors can be turned on. The specific value can be determined according to the actual situation.

[0091] In this embodiment, the storage transistors of the target row are connected to the same second word line. Applying a programming voltage to the second word line can control the voltage of the second gate of the storage transistor at the programming voltage. The source regions of the target column are connected to the same source line. Applying a first source bias voltage to the source line can control the voltage of the source region of the target column at the first source bias voltage. The drain regions of the target column are connected to the same bit line. Applying a first drain bias voltage to the bit line can control the voltage of the drain region of the target column at the first drain bias voltage.

[0092] It should be noted that, in this embodiment, based on the conduction of the logic transistors of the target memory cell, by applying a programming voltage, a first source bias voltage, and a first drain bias voltage to the target memory cell, the functional layer (such as the ferroelectric layer) used for storing data in the target memory cell can maintain a large voltage, so that the storage transistors (specifically the functional layer used for storing data) in the target memory cell will undergo polarization flipping, complete the data writing, and store the data in the target memory cell.

[0093] This embodiment does not limit the specific values ​​of the programming voltage, the first source bias voltage, and the first drain bias voltage, as long as they can ensure that the polarization of the storage transistor can be flipped. The specific values ​​can be determined according to the actual situation.

[0094] It should be noted that the applied programming voltage varies depending on the data being written. In one possible implementation, when writing a 0 to the target memory cell, a first programming voltage, which is positive, can be applied to the second word line of the target row. In another possible implementation, when writing a 1 to the target memory cell, a second programming voltage, which is negative, can be applied to the second word line of the target row.

[0095] In this embodiment, the logic transistors in non-target rows are connected to the same first word line. Applying a turn-off voltage to this first word line controls the voltage of the first gate of the logic transistors to the turn-off voltage, thereby turning off the logic transistors in non-target rows. This embodiment does not limit the specific value of the turn-off voltage, as long as it ensures that the logic transistors are turned off. The specific value can be determined according to the actual situation.

[0096] It should be noted that in this embodiment, the logic transistors of non-target rows are turned off, and the storage transistors of non-target rows have no programming voltage, which can ensure that the storage transistors of non-target rows do not undergo polarization switching.

[0097] In this embodiment, the source regions of non-target columns are connected to the same source line, and the drain regions of non-target columns are connected to the same bit line. Placing the source line and bit line at a floating potential allows a depletion layer to form in the channel region. It should be noted that for memory cells in non-target columns that are in the same row as the target row, although a programming voltage is applied to the memory transistor, the formed depletion layer capacitance diverts most of the voltage, preventing polarization reversal in the functional layers used for data storage (such as ferroelectric layers), thus effectively suppressing write crosstalk.

[0098] It should be noted that in this embodiment, all signal lines are kept at the current voltage for a preset time to ensure the polarization of the storage transistor is stable. This embodiment does not limit the specific value of the preset time, as long as it ensures that polarization switching can be completed, and can be determined according to the actual situation.

[0099] In one possible implementation, when the target operation is a read operation, the control method may include:

[0100] An enable voltage is applied to the first word line of the target row, a read voltage is applied to the second word line of the target row, and a second source bias voltage and a second drain bias voltage are applied to the source line and bit line of the target column, respectively, so that the logic transistors and storage transistors in the target memory cell form a current path through a shared channel region to read the data stored in the target memory cell.

[0101] A turn-off voltage is applied to the first word line of the non-target row, and a third source bias voltage and a third drain bias voltage are applied to the source line and bit line of the non-target column, respectively, to block the current path between the logic transistors and the storage transistors in all non-target memory cells.

[0102] The type of stored data is determined by detecting the current value on the bit lines of the target column. After the detection is completed, the target storage unit completes the read operation.

[0103] In this embodiment, the read voltage applied to the second word line of the target row must be sufficient to not change the polarization state of the functional layer (such as the ferroelectric layer) used for storing data. The specific value can be determined according to the actual situation.

[0104] In this embodiment, applying an enable voltage to the first word line of the target row can turn on the logic transistor of the target row; applying a read voltage to the second word line of the target row can control the voltage of the second gate of the storage transistor at the read voltage; applying a second source bias voltage and a second drain bias voltage to the source line and bit line of the target column respectively can control the voltage of the source region and the drain region of the target column at the second source bias voltage and the second drain bias voltage respectively.

[0105] It should be noted that, in this embodiment, based on the conduction of the logic transistor of the target memory cell, a current path can be formed by applying a read voltage, a second source bias voltage, and a second drain bias voltage to the target memory cell. The magnitude of the current is determined by the threshold voltage of the memory transistor (different polarization states result in different threshold voltages).

[0106] This embodiment does not limit the specific values ​​of the second source bias voltage and the second drain bias voltage, as long as a current path can be formed. The specific values ​​can be determined according to the actual situation.

[0107] In this embodiment, applying a turn-off voltage to the first word line of a non-target row can turn off the logic transistors in that row. It should be noted that when the logic transistors in a non-target row are turned off in this embodiment, there is no current path for the storage transistors, and the detection of bit line current is not affected.

[0108] In this embodiment, a third source bias voltage and a third drain bias voltage are applied to the source lines and bit lines of the non-target column, respectively. This allows the voltages in the source and drain regions of the target column to be controlled at the third source bias voltage and the third drain bias voltage, respectively. The applied third source bias voltage and third drain bias voltage in this embodiment must ensure that no current path is created to avoid crosstalk; the specific values ​​can be determined based on actual conditions.

[0109] This embodiment does not limit the specific method of detecting the current value on the bit line of the target column, as long as the current value can be obtained. In one possible implementation, the detection method may include: detecting the current value on the bit line using a current sensor on the bit line.

[0110] This embodiment does not limit the specific method for determining the type of stored data; it can be determined based on the specific type of stored data. In one possible implementation, the determination method may include:

[0111] If the current value is higher than the preset threshold, the stored data is determined to be 1; if the current value is lower than the preset threshold, the stored data is determined to be 0.

[0112] It should be noted that the read / write voltage control strategy designed based on the above memory structure in this embodiment effectively suppresses read / write crosstalk of non-target cells through the floating potential and depletion layer capacitor voltage division mechanism, thus ensuring the stability and reliability of stored data.

[0113] Based on the above embodiments, this application can be applied to the above-mentioned memory and has the same beneficial effects.

[0114] This application also provides a method for fabricating a memory, characterized in that it includes:

[0115] Step 1: Form at least one channel region in the substrate;

[0116] Step 2: Form source and drain regions in the substrate on both sides of each channel region along the first direction, respectively;

[0117] Step 3: Form a first gate structure, a spacer layer, and a second gate structure sequentially arranged along a first direction on the surface of each channel region to obtain the memory.

[0118] In one possible implementation, step 1 may include: forming a single semiconductor channel region on the substrate surface.

[0119] In one possible implementation, step 2 may include: forming highly doped regions in the substrate on both sides of each channel region along the first direction using an ion implantation process to obtain source and drain regions.

[0120] In one possible implementation, step 3 may include:

[0121] A first gate structure is formed on the surface of each channel region;

[0122] A spacer layer is formed on the surface of each channel region;

[0123] A second gate structure is formed on the surface of each channel region.

[0124] It should be noted that this embodiment does not limit the specific order in which the first gate structure, the spacer layer and the second gate structure are formed, as long as the arrangement of the first gate structure, the spacer layer and the second gate structure in each channel region is arranged sequentially along the first direction.

[0125] In one possible implementation, forming a first gate structure on the surface of each channel region may include: sequentially forming a first gate oxide layer and a first gate on the surface of the channel region on one side of each spacer layer along a first direction along a second direction to obtain a first gate structure;

[0126] In one possible implementation, forming a spacer layer on the surface of each trench region may include: using an insulating material to form the spacer layer on the surface of each trench region.

[0127] In one possible implementation, forming a second gate structure on the surface of each channel region may include: sequentially forming a second gate oxide layer, a ferroelectric layer, and a second gate on the surface of the channel region on the other side of each spacer layer along a second direction to obtain a second gate structure.

[0128] Based on the above embodiments, this application is able to prepare the above-described memory, which also has the above-described beneficial effects.

[0129] The operation process of the memory described above is illustrated below with a specific example. In this embodiment, MOSFETs are used for logic transistors, FeFETs are used for storage transistors, and signal lines are... Figure 3 The arrangement shown is as follows.

[0130] Figure 4 The following is a flowchart illustrating a write operation of a memory according to an embodiment of this application. The specific process of the write operation is as follows:

[0131] 1. Initialize the potential of all signal lines:

[0132] Apply a 0V shutdown voltage to all first word lines (WL) and second word lines (WLF) in the memory array; apply a first bias voltage of 0V to all source lines (SL) and bit lines (BL) to bring the entire memory array into an initial stable state.

[0133] 2. Select the target row and target column, and apply the write operation voltage:

[0134] Target row: Apply the turn-on voltage V to the WL of the target row. W This turns on the MOSFET;

[0135] When writing "0", apply the first programming voltage +V to the WLF of the target row. WF ,

[0136] When writing "1", a second programming voltage -V is applied to the WLF of the target row. WF ;

[0137] Target column: Apply a first bias voltage of 0V to SL and BL of the target column;

[0138] At this time, the MOSFET of the target memory cell is turned on, the second gate structure of the FeFET applies the programming voltage through WL, the source region and drain region apply 0V voltage through SL and BL, the ferroelectric layer voltage is large, polarization reversal will occur, data writing is completed, and data is stored.

[0139] 3. Apply crosstalk suppression voltage to non-target rows and non-target columns:

[0140] Non-target rows: Apply a 0V turn-off voltage to the WL of all non-target rows and apply a 0V turn-off voltage to the WLF of non-target rows to turn off the MOSFETs of non-target rows. The second gate structure of the FeFET has no programming voltage and does not undergo polarization switching.

[0141] Non-target columns: Set the SL and BL of all non-target columns to floating potential;

[0142] For non-target column memory cells in the same row as the target (non-target memory cells on the same WL), although a programming voltage is applied to the second gate structure of the FeFET, the source and drain regions are floating, and a depletion layer is formed in the channel region. The depletion layer capacitance diverts most of the voltage, so that the ferroelectric layer does not undergo polarization reversal, which can effectively suppress write crosstalk.

[0143] 4. Maintain the voltage for the preset time to complete the FeFET polarization reversal:

[0144] Maintain the above voltage state to ensure FeFET polarization stability;

[0145] 5. All signal lines are reset to their initial state; the write operation is complete.

[0146] Reset all signal lines to 0V. Write operation complete.

[0147] Figure 5 The present application provides a schematic flowchart of a read operation of a memory, the specific process of which is as follows:

[0148] 1. Initialize the potential of all signal lines:

[0149] Apply 0V to all WL and WLF rows, and 0V to all SL and BL rows to bring the entire storage array to an initial stable state; 2. Select the target row and target column, and apply the read operation voltage:

[0150] Target row: Apply the turn-on voltage V to the WL of the target row. W This turns on the MOSFET;

[0151] Apply a read voltage of 0V or a small voltage V0 to the WLF of the target row, which is insufficient to change the polarization state of the ferroelectric layer.

[0152] Target column: Apply a second bias voltage V to the BL of the target column. R Apply 0V to the target column's SL;

[0153] At this time, the MOSFET of the target memory cell is turned on, the second gate structure of the FeFET applies a read voltage, the source region is grounded through SL, and the drain region is applied a second bias voltage V through BL. R This will create a current path, and the magnitude of the current is determined by the threshold voltage of the FeFET (different polarization states result in different threshold voltages).

[0154] 3. Apply crosstalk suppression voltage to non-target rows and non-target columns:

[0155] Non-target row: Both WLF and WL in the non-target row are applied with 0V, the MOSFET is cut off, the FeFET has no current path, and it does not affect the BL current detection;

[0156] Non-target column: SL and BL of the non-target column are both applied 0V, no current is generated, and crosstalk can be avoided;

[0157] 4. Detect the current value of the target column BL to determine the stored data:

[0158] The current value is detected by the current sensor on BL;

[0159] If the current value is higher than the preset threshold, the stored data is determined to be "1";

[0160] If the current value is lower than the preset threshold, it is determined that the stored data is "0";

[0161] 5. All signal lines are reset to their initial state; the read operation is complete.

[0162] The voltage settings for the signal lines during the above read / write operations are shown in Table 1.

[0163] Table 1. Voltage setting method for signal lines

[0164]

[0165] This document uses specific examples to illustrate the principles and implementation methods of this application. The various embodiments are progressive, with each embodiment focusing on its differences from others. Similar or identical parts between embodiments can be referred to interchangeably. The descriptions of the embodiments above are merely illustrative of the method and core ideas of this application. For those skilled in the art, various improvements and modifications can be made to this application without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this application.

[0166] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A memory, characterized in that, include: A storage array, the storage array comprising multiple storage units; The memory cell includes a substrate in which a source region, a channel region, and a drain region are sequentially disposed along a first direction. A first gate structure, a spacer layer, and a second gate structure are sequentially disposed on the surface of the channel region along the first direction. The source region and the drain region are both in ohmic contact with the channel region. The first gate structure, the source region, the drain region, and the channel region constitute a logic transistor; The second gate structure, the source region, the drain region, and the channel region constitute a storage transistor; The storage transistor and the logic transistor share the source region, the drain region, and the channel region, and are connected in series through the channel region.

2. The memory according to claim 1, characterized in that, include: Multiple signal lines; the signal lines include a first word line, a second word line, a source line, and a bit line; The first gate structure of all the memory cells in the same row shares the same first word line; The second gate structure of all the memory cells in the same row shares the same second word line; The first character line and the second character line are arranged in parallel and both extend along the line direction; The source regions of all the memory cells in the same column share the same source line; The drain regions of all the memory cells in the same column share the same bit line; the bit line is arranged parallel to the source line and extends along the column direction.

3. The memory according to claim 1, characterized in that, The channel region is made of semiconductor material; And / or, the spacer layer is made of an insulating material.

4. The memory according to claim 1, characterized in that, The logic transistor is a MOSFET; the first gate structure includes a first gate oxide layer and a first gate sequentially disposed along a second direction; And / or, the storage transistor is a FeFET; the second gate structure includes a second gate oxide layer, a ferroelectric layer and a second gate sequentially disposed along the second direction.

5. A method for operating a memory, applied to the memory according to any one of claims 1 to 4, characterized in that, include: When performing a target operation on a target memory cell in the memory, a current path is formed between the logic transistor and the storage transistor in the target memory cell through a shared channel region, and the current path between the logic transistor and the storage transistor in all non-target memory cells is blocked.

6. The method of operating the memory according to claim 5, characterized in that, The target operation is a write operation; when performing the target operation on the target memory cell, a current path is formed between the logic transistor and the storage transistor in the target memory cell through a shared channel region, and the current path between the logic transistor and the storage transistor in all non-target memory cells is blocked, including: An enable voltage is applied to the first word line of the target row, a programming voltage is applied to the second word line of the target row, and a first source bias voltage and a first drain bias voltage are applied to the source line and bit line of the target column, respectively, so that the logic transistor and the storage transistor in the target memory cell form the current path through the shared channel region, so that the storage transistor in the target memory cell undergoes polarization flipping to complete the data writing; Apply a shutdown voltage to the first word line of the non-target row, place the source line and the bit line of the non-target column at a floating potential, and block the current path between the logic transistor and the memory transistor in all the non-target memory cells; Maintain all signal lines at their current voltage for a preset time until the target memory cell completes the write operation.

7. The method of operating the memory according to claim 5, characterized in that, The target operation is a read operation; when performing the target operation on the target memory cell, a current path is formed between the logic transistor and the storage transistor in the target memory cell through a shared channel region, and the current path between the logic transistor and the storage transistor in all non-target memory cells is blocked, including: An enable voltage is applied to the first word line of the target row, a read voltage is applied to the second word line of the target row, and a second source bias voltage and a second drain bias voltage are applied to the source line and bit line of the target column, respectively, so that the logic transistor and the storage transistor in the target memory cell form the current path through the shared channel region to read the data stored in the target memory cell. A shutdown voltage is applied to the first word line of the non-target row, and a third source bias voltage and a third drain bias voltage are applied to the source line and the bit line of the non-target column, respectively, to block the current path between the logic transistor and the memory transistor in all the non-target memory cells. By detecting the current value on the bit line of the target column, the type of stored data is determined. After the detection is completed, the target storage unit completes the read operation.

8. The method of operating the memory according to claim 5, characterized in that, Before performing a target operation on a target memory cell in the memory, and before forming a current path between the logic transistors and storage transistors in the target memory cell through a shared channel region, and blocking the current path between the logic transistors and storage transistors in all non-target memory cells, the method further includes: Initialize the potentials of the first gate structure, the second gate structure, the source region, and the drain region in all memory cells of the memory.

9. The method of operating the memory according to claim 5, characterized in that, When performing a target operation on a target memory cell in the memory, after establishing a current path between the logic transistors and storage transistors in the target memory cell through a shared channel region and blocking the current path between the logic transistors and storage transistors in all non-target memory cells, the method further includes: The potentials of the first gate structure, the second gate structure, the source region, and the drain region in all memory cells of the memory are reset to their initial states.

10. A method for fabricating a memory, used to fabricate the memory according to any one of claims 1 to 4, characterized in that, include: At least one channel region is formed in the substrate; A source region and a drain region are formed in the substrate on both sides of each channel region along the first direction, respectively; A first gate structure, a spacer layer, and a second gate structure are formed sequentially along the first direction on the surface of each channel region to obtain the memory.

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