Instruction pipeline processing methods and apparatus, electronic equipment

Abstract

This disclosure provides a method, apparatus, and electronic device for instruction pipeline processing. The method includes: fetching a loop body, where the loop body contains multiple instructions, including an end-branch instruction. The end-branch instruction indicates the end of the loop body and includes a back-branch path. In response to the loop body being passed through the instruction fetch pipeline and stored in a buffer, the method flushes the currently passed instruction in the instruction fetch pipeline and fetches subsequent passed instructions into the instruction fetch pipeline. The subsequent passed instructions are those executed after the loop body exits the loop, and the currently passed instructions are different from the subsequent passed instructions. This instruction pipeline processing method reduces instruction fetch bubbles generated after exiting a loop, improving instruction fetch efficiency and processor performance.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and specifically to an instruction pipeline processing method and apparatus, and electronic equipment. Background Technology

[0002] Instruction pipelining is a core technology used by modern processors to improve execution efficiency. It breaks down the complete execution process of a machine instruction into multiple independent steps such as instruction fetch, decode, data fetch, execution, and write-back. Different stages of different instructions can run concurrently, rather than waiting for one instruction to be completely completed before starting the next, thereby executing more instructions per unit of time and significantly improving the processor's throughput and processing speed.

[0003] The instruction fetch stage can be considered the first step in the instruction pipeline, responsible for reading the next instruction to be executed from memory or cache and handing it over to the processor for further processing. However, there is still room for improvement in how to enhance instruction fetch efficiency. Summary of the Invention

[0004] At least one embodiment of this disclosure also provides a method for processing an instruction pipeline. The method includes: obtaining a loop body, wherein the loop body contains multiple instructions including an end-branch instruction, wherein the end-branch instruction is used to indicate the end of the loop body and includes a jump-back branch path; in response to the loop body being passed to a buffer via an instruction fetch pipeline, flushing the current instruction passed to the instruction fetch pipeline and obtaining subsequent instruction passed to the instruction fetch pipeline; wherein the subsequent instruction is the instruction executed after the loop body exits the loop, and the current instruction passed is different from the subsequent instruction passed.

[0005] At least one embodiment of this disclosure provides an instruction pipeline processing apparatus, which includes an instruction fetch control circuit and an instruction prefetch circuit. The instruction fetch control circuit is configured to acquire a loop body, wherein the loop body includes an end branch instruction among multiple instructions, wherein the end branch instruction is used to indicate the end of the loop body, and the end branch instruction includes a jump branch path. The instruction prefetch circuit is configured to, in response to the loop body being passed through the instruction fetch pipeline and stored in a buffer, flush the current transmission instruction of the instruction fetch pipeline and acquire subsequent transmission instructions into the instruction fetch pipeline. The subsequent transmission instructions are the instructions executed after the loop body exits the loop, and the current transmission instructions are different from the subsequent transmission instructions.

[0006] At least one embodiment of this disclosure provides an electronic device including at least one memory and at least one processor: the at least one memory is configured to store computer-executable instructions; and the at least one processor is configured to execute the computer-executable instructions, wherein when the computer-executable instructions are executed by at least one processing unit, they implement the processing method of the instruction pipeline provided according to any embodiment of this disclosure. Attached Figure Description

[0007] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0008] Figure 1 A schematic diagram of a processor core pipeline is shown.

[0009] Figure 2 A schematic diagram of the loop body fetching during the fetching phase is shown.

[0010] Figure 3 An exemplary flowchart of a processing method provided in at least one embodiment of the present disclosure is shown.

[0011] Figure 4 The present disclosure illustrates a processing method provided by at least one embodiment for... Figure 2 An exemplary schematic diagram of the process after the intermediate circulation body is processed.

[0012] Figure 5 The present disclosure illustrates a processing method provided by at least one embodiment for... Figure 2 An exemplary schematic diagram of the process after the intermediate circulation body is processed.

[0013] Figure 6 An exemplary circuit framework diagram of an instruction pipeline processing method provided in at least one embodiment of the present disclosure is shown.

[0014] Figure 7 A block diagram of a processing apparatus for an instruction pipeline provided in at least one embodiment of the present disclosure is shown.

[0015] Figure 8 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0016] Figure 9 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0018] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0019] The terminology used in this disclosure is that which is currently widely used in the art in consideration of the functionality of this disclosure; however, these terms may vary depending on the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this disclosure. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this disclosure.

[0020] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0021] With the ever-increasing demands for processor performance, instruction pipeline technology has become a core pillar of modern processor design. Pipeline technology divides the instruction execution process into multiple independent stages such as fetch, decode, execute, memory access, and write-back, enabling multiple instructions to be executed concurrently, thereby significantly improving instruction-level parallelism.

[0022] For example, a processor can be a scalar processor or a superscalar processor. In a scalar processor, the scalar pipeline executes an average of less than or equal to one instruction per clock cycle, meaning its instruction-level parallelism is less than or equal to 1. A superscalar processor adds extra resources to a typical scalar processor, creating multiple pipelines, each executing the instructions assigned to it, thereby achieving parallelism.

[0023] For example, the processor can be a single-core processor or a multi-core processor.

[0024] Figure 1 This diagram illustrates a processor core pipeline, where dashed lines with arrows represent redirected instruction flows. As shown, processor cores in single-core or multi-core processors (such as CPU cores) improve instruction-level parallelism through pipeline technology. The processor core internally includes multiple pipeline stages. For example, after program counters from various sources are fed into the pipeline and the next program counter (PC) is selected by a multiplexer (Mux), the instruction corresponding to that PC undergoes processing through stages such as branch prediction, instruction fetch, instruction decoding, instruction dispatch and rename, instruction execution, and instruction retire. Between each pipeline stage, waiting queues are set as needed; these queues are typically first-in-first-out (FIFO) queues. For example, after the branch prediction unit, a branch prediction (BP) FIFO queue is set up to store the branch prediction results; after the instruction fetch unit, an instruction buffer (IB) FIFO is set up to buffer the fetched instructions; after the instruction decode unit, a decode (DE) FIFO is set up to temporarily store the decoded instructions; and after the instruction dispatch and rename unit, a finish (RT) FIFO is set up to temporarily store instructions waiting for confirmation of completion after execution. The processor core pipeline also includes an instruction queue to temporarily store instructions waiting for execution by the instruction execution unit after instruction dispatch and rename. To support high operating frequencies, each pipeline stage may contain multiple pipeline stages (clock cycles). Although each pipeline stage performs a limited number of operations, this minimizes the time per clock cycle, thereby improving processor core performance by increasing the processor core's operating frequency. Each pipeline stage can also further improve processor core performance by accommodating more instructions (i.e., superscalar technology).

[0025] For example, the instruction buffer (IB) is located after the instruction fetch unit, which is used to perform the instruction fetching stage and fetch instructions from the instruction cache (IC) or the bus.

[0026] For example, in the instruction fetch stage, the instruction fetched from the instruction cache needs to pass through the fetch pipeline and be stored in the instruction buffer. The fetch pipeline is a preceding pipeline located before the instruction buffer, and it can include at least one fetch stage. This fetch pipeline delivers instructions based on clock cycles. For example, the fetch stage can be implemented using registers.

[0027] A clock cycle is the most basic unit of time in a processor, referring to the time required for a clock signal to oscillate once, that is, the time interval between two consecutive rising (or falling) edges, usually measured in nanoseconds (ns) or picoseconds (ps). The reciprocal of the clock cycle is the clock frequency, which determines the number of cycles a processor can complete per second.

[0028] For instructions that are not executed in a loop, the instruction buffer can compensate for the speed difference between the fetch stage and the subsequent decode stage.

[0029] For instructions executed in a loop (loop body), in addition to buffering the processing speed difference between the two stages mentioned above, the subsequent decoding stage does not need to fetch instructions from the IC during instruction fetching, but can issue instructions from the IB, thereby improving instruction fetching efficiency.

[0030] In a processor's instruction pipeline, bubbles during the instruction fetch stage can significantly impact overall performance. When bubbles appear during the fetch stage, subsequent stages such as decoding and execution will face instruction interruptions, resulting in idle cycles in the pipeline. This idle cycle directly leads to the waste of hardware resources, and functional units cannot be effectively utilized.

[0031] Figure 2 A schematic diagram of the loop body fetching during the fetching phase is shown.

[0032] like Figure 2As shown in the diagram, the schematic may include an instruction cache IC, an instruction fetch pipeline with, for example, three fetch stages, and an instruction buffer IB, which may include multiple buffer entries. The loop body may include instruction 1, instruction 2, instruction 3, and instruction 4, where instruction 1 is the starting instruction of the loop body, and instruction 4 is the ending branch instruction of the loop body. For example, the instructions in this loop body can be executed cyclically as instruction 1, instruction 2, instruction 3, and instruction 4, then returning to instruction 1.

[0033] In clock cycle i, the start instruction (instruction 1) of the cycle body is fetched from the IC to the first fetch stage (the fetch stage closest to the IC) in the fetch pipeline. In each subsequent clock cycle, the previous fetch stage in the fetch pipeline passes the instruction to the next fetch stage, until it reaches the last fetch stage (the fetch stage closest to the IB) in the fetch pipeline. The last fetch stage then passes the instruction from the fetch stage to the IB.

[0034] For example, at clock cycle i+3, that is, after 3 clock cycles, instruction 1 is stored in IB through the instruction fetch pipeline.

[0035] For example, in the clock cycle Cycle i+6, all instructions in the entire loop are stored in IB.

[0036] For example, instruction 4, as the ending branch instruction of this loop, will jump backward to instruction 1. After instruction 4, instruction 1 needs to be fetched from the IC to continue transmission. That is, after the loop completes the instruction input into the IB, the instruction fetch pipeline can be paused to stop the instruction fetch pipeline from continuing to input instructions into the IB. For example, this instruction fetch pipeline pause can be implemented by setting the IB state. When the IB is in the accepting state (refill state), it means that it is normally receiving and buffering instructions from the IC; when the IB enters the back-pressure state (stall state), it means that the buffer is full, and instruction fetching is paused and waiting for downstream consumption.

[0037] See also Figure 2 Because after the loop body is stored in the Instruction Block (IB), each fetch stage in the instruction fetch pipeline contains the instructions belonging to that loop body, after the loop body in the IB exits the loop (i.e., no longer loops), the currently passed instructions in the instruction fetch pipeline (i.e., instructions 1, 2, and 3) are invalid instructions in the instruction stream. This results in at least one pipeline bubble between exiting the loop body and obtaining the subsequent instructions (also referred to as subsequent passed instructions or valid instructions) that need to be executed after exiting the loop body. For example... Figure 2 The delay of at least 3 clock cycles corresponding to instructions 1, 2 and 3 in the instruction fetch process affects the fetch efficiency.

[0038] In addition, if the valid instruction after exiting the loop cannot be obtained from the IC, that is, when the valid instruction is in a cache miss state in the IC, it is necessary to request the instruction from the bus. In this case, pipeline bubbles will increase sharply, which will seriously affect instruction fetching efficiency and processor performance.

[0039] At least one embodiment of this disclosure provides a method for processing an instruction pipeline. The method includes: obtaining a loop body, wherein the loop body contains multiple instructions including an end-branch instruction, wherein the end-branch instruction is used to indicate the end of the loop body and includes a jump-back branch path; in response to the loop body being passed to a buffer via an instruction fetch pipeline, flushing the current instruction passed to the instruction fetch pipeline and obtaining subsequent instruction passed to the instruction fetch pipeline; wherein the subsequent instruction passed is the instruction executed after the loop body exits the loop, and the current instruction passed is different from the subsequent instruction passed.

[0040] In the instruction pipeline processing method of the above embodiments of this disclosure, after storing the loop body in the buffer device, the current instruction to be passed in the instruction fetch pipeline is flushed, and the subsequent instruction to be passed after the loop body exits the loop is obtained and passed to the instruction fetch pipeline. This allows the subsequent instruction to be obtained directly from the instruction fetch pipeline after the loop body exits the loop, reducing the instruction fetch bubble generated after exiting the loop and improving instruction fetch efficiency and processor performance.

[0041] At least one embodiment of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals will be used to refer to the same parts described in different drawings.

[0042] Figure 3 An exemplary flowchart of an instruction pipeline processing method provided in at least one embodiment of the present disclosure is shown.

[0043] like Figure 3 As shown, the processing method of this instruction pipeline can be executed by the processor, including the following steps S10 and S20.

[0044] Step S10: Obtain the loop body, which includes a branch termination instruction among its multiple instructions.

[0045] Step S20: In response to the loop body passing the instruction stored in the buffer device through the instruction fetch pipeline, flush the current instruction passing in the instruction fetch pipeline and obtain the subsequent instruction passing in the instruction fetch pipeline.

[0046] The end branch instruction is used to mark the end of the loop body, and the end branch instruction includes the jump branch path; the subsequent pass instruction is the instruction executed after the loop body jumps out of the loop, and the current pass instruction is different from the subsequent pass instruction.

[0047] For example, the buffer device can be Figure 2 The instruction buffer (IB) is shown. The instruction fetch pipeline may include at least one instruction fetch stage, for example, it may be... Figure 2 The instruction fetch pipeline is configured to deliver instructions through at least one instruction fetch stage according to the clock cycle.

[0048] For example, the current instruction pass is the instruction fetch from the pipeline within the clock cycle after the loop body is stored in the buffer; the clock cycle after the loop body is stored in the buffer can be, for example,... Figure 2 The clock cycle in Cycle i+6 indicates that the currently transmitted instruction can be... Figure 2 Instructions 1, 2, and 3.

[0049] For example, the branch termination instruction can be a conditional branch instruction. This conditional branch instruction is not a composite conditional branch instruction; for the processor hardware, it is a branch path selection. For example, this branch termination instruction includes both back-edge and forward-edge branch paths.

[0050] Backslip branches are used to form loop bodies, which can include multiple instructions executed in a loop. A backslip branch can be a backward branch, meaning the program counter (PC) of the target instruction determined by the backslip branch is less than the PC of the current instruction. For conditional branch instructions with backslip branches, the program counter can be rolled back, allowing the already executed instruction sequence to re-enter the pipeline and achieve a loop.

[0051] A forward branch path is a branch path that exits the loop and continues execution downwards. For example, in a forward branch path, during instruction execution, the PC value always points to the location of the instruction to be fetched from the instruction cache in the next clock cycle. The PC value automatically increments after each instruction fetch; for example, this forward branch path can point sequentially to the next instruction (PC value + 1), or it can point to the m-th instruction after it (PC value + m, where m is an integer greater than or equal to 2).

[0052] It should be noted that not all branch instructions that cause a backtrack (with a backtrack branch path) can be used as termination branch instructions. For example, since direct and indirect jump instructions always result in a jump, a backtrack would cause the program to enter an infinite loop; therefore, direct and indirect jump instructions cannot be used as termination branch instructions. Furthermore, since direct and indirect jump instructions always result in a jump and do not involve two branches, they are not branch instructions disclosed in this document.

[0053] For example, flushing the current instruction in the instruction fetch pipeline can be performed immediately within a clock cycle after the loop body is stored in the buffer, and subsequent instruction fetches can be performed immediately after the instruction fetch pipeline is flushed. Of course, the embodiments of this disclosure are not limited to this. For example, the flushing and prefetching of subsequent instruction fetches can be performed several clock cycles after the loop body is stored in the buffer, as long as as many subsequent instruction fetches as possible into the instruction fetch pipeline before the loop body ends. More generally, the flushing and prefetching of subsequent instruction fetches can occur before the loop body exits the loop in the buffer.

[0054] For example, after the current instruction is flushed, the next instruction can be retrieved from the instruction cache (IC). If the instruction cache is hit, the next instruction is retrieved from the IC; if the instruction cache is missed, the bus is requested again to retrieve the next instruction.

[0055] For example, the subsequent production line is Figure 2 The pipeline stages following IB (not shown) include, for example, issue units and execution units. Execution units include, for instance, branch jump units (BJUs) and floating-point and graphics units (FGUs). BJUs are used for conditional branch checks and jump address calculations.

[0056] It should be noted that this publication does not limit the number of instruction fetch stages in the instruction fetch pipeline, nor does it limit the number of instructions currently being passed.

[0057] For example, subsequent instruction passing can be obtained from the IC or bus based on prefetch instruction information. For instance, the prefetch instruction information is the instruction information of the target instruction pointed to when a branch path of a certain branch instruction exits the loop.

[0058] For example, at least one branch instruction in a loop body may include a branch instruction, namely the end branch instruction. In this case, the subsequent instruction passed is the target instruction pointed to by the forward branch path of the end branch instruction.

[0059] For example, a loop body can include multiple branch instructions, such as an end branch instruction and at least one intermediate branch instruction. The intermediate branch instruction can be a conditional branch instruction. This intermediate branch instruction does not indicate the end of the loop body. For example, the subsequent pass instruction can be the target instruction pointed to by the forward branch path or the back jump branch path of the intermediate branch instruction.

[0060] The following description, in conjunction with the accompanying drawings, exemplarily illustrates a method for instruction pipeline processing provided in at least one embodiment of this disclosure, which reduces the aforementioned... Figure 2 The finger-taking bubble after exiting the loop.

[0061] Figure 4 The present disclosure illustrates a processing method provided by at least one embodiment for... Figure 2 An exemplary schematic diagram of the process after the intermediate circulation body is processed.

[0062] For example, for a loop body that includes instructions 1, 2, 3 and 4, if the loop body contains only the ending branch instruction (instruction 4), and the forward branch path of the ending branch instruction is instruction 5, then the instruction executed after the loop body exits the loop is instruction 5. If instruction 5 is followed by instructions 6 and 7 in sequence, then the loop body will execute instructions 6 and 7.

[0063] like Figure 4 As shown, after flushing the currently passed instructions (instruction 1, instruction 2, and instruction 3) in the instruction fetch pipeline, the subsequent passed instructions, instruction 5, and then instructions 6 and 7, can be prefetched into the instruction fetch pipeline according to clock cycles. For example, after some clock cycles, at clock cycle i+6+N, the last stage of the instruction fetch pipeline, instruction 5, instruction 6, and instruction 7 are in instruction fetch stage P3, instruction 6, and instruction 7, respectively, where N is a positive integer greater than 3.

[0064] For example, in a loop body containing instructions 1, 2, 3, and 4, if the loop body contains intermediate branch instructions (such as instruction 3) in addition to the ending branch instruction (instruction 4), instruction 3 can be a conditional branch instruction with two different forward branch paths, such as one forward branch path pointing to instruction 4 and the other forward branch path pointing to instruction 9. Instruction 3 can also be a conditional branch instruction with one forward branch path pointing to instruction 4 and one back branch path pointing to instruction 0.

[0065] The subsequent transmission of instructions at this point will result in the following situation:

[0066] In the first case, the loop is exited by ending the branch instruction, and the target instruction (instruction 5) pointed to by the forward branch path of the ending branch instruction is prefetched as the subsequent instruction and stored in the instruction fetch pipeline (as described above). Figure 4 same);

[0067] In the second case, the loop is exited through an intermediate branch instruction, and the target instruction (instruction 9 or instruction 0) pointed to by the corresponding branch used to exit the loop in the intermediate branch instruction is prefetched as the subsequent instruction to be passed and stored in the instruction fetch pipeline.

[0068] Figure 5 The present disclosure illustrates a processing method provided by at least one embodiment for... Figure 2 An exemplary schematic diagram of the process after the intermediate circulation body is processed.

[0069] like Figure 5 As shown, after flushing the current instruction passed to the instruction fetch pipeline (instruction 1, instruction 2, and instruction 3), instruction 9, which is pointed to by another forward branch path of instruction 3, as well as the subsequently executed instructions 10 and 11, can be prefetched into the instruction fetch pipeline according to clock cycles. For example, after some clock cycles, at clock cycle i+6+N, the last stage of the instruction fetch pipeline, instruction 9, instruction 10, and instruction 11 are in instruction fetch stage P3, instruction 10, and instruction 11, where N is a positive integer greater than 3.

[0070] For example, the steps of flushing the current instruction in the instruction fetch pipeline and fetching subsequent instructions into the instruction fetch pipeline occur before the loop body in the buffer exits the loop, thus prefetching subsequent instructions while the buffer provides instructions for the loop body to the subsequent pipeline as an instruction source.

[0071] The instruction pipeline processing method described above can reduce fetch bubbles during the instruction fetch stage. For example, before exiting the loop body stored in the buffer, subsequent instruction transmissions have already reached the last fetch stage in the instruction fetch pipeline. At this point, the effect of fetch bubble elimination is greatest, reducing or even eliminating fetch bubbles corresponding to the number of fetch stages in the instruction fetch pipeline, at least during the instruction fetch stage. The reduction or elimination of fetch bubbles is even greater when an IC miss occurs.

[0072] For example, the above Figure 4 or Figure 5 As shown, during the process of providing instructions from the loop body to the subsequent pipeline for processing, whether it is a bubble generated by the loop body jumping out of the loop due to the end of the branch instruction or a bubble generated by the jump of the loop body due to the intermediate branch instruction, the above-mentioned instruction pipeline processing method of this disclosure can reduce, for example, three clock cycles of instruction fetching bubbles, so that after jumping out of the loop body, the subsequent instruction can be directly obtained for processing by the subsequent pipeline, thereby improving processor performance.

[0073] In some embodiments of this disclosure, the above processing method may further include: in response to the loop body being stored in the buffer device, configuring the buffer device to enter a first state; wherein the first state indicates that the buffer device stops receiving the currently passed instruction in the instruction fetch pipeline and serves as an instruction source for subsequent pipeline processing.

[0074] For example, in addition to flushing the finger-fetching line immediately after the circulation body is stored, the finger-fetching line can also be flushed after the buffer device is configured and the line enters the first state.

[0075] This first state is when the buffer stops receiving the currently passed instruction from the instruction fetch pipeline and serves as an instruction source for subsequent pipeline processing. For example, this first state is the aforementioned reverse pressure state, also known as the active state.

[0076] For example, the buffer device includes multiple instruction buffer entries and at least one branch instruction information buffer entry. The multiple instruction buffer entries are used to store multiple instructions, and the at least one branch instruction information buffer entry is used to store information about branch instructions in the multiple instructions.

[0077] For example, multiple instruction buffer entries and at least one branch instruction information buffer entry in the buffer device can be provided by different buffers, or the buffer device can be a buffer, and multiple instruction buffer entries and at least one branch instruction information buffer entry can be provided by dividing the buffer entries in the buffer, that is, multiple instruction buffer entries and at least one branch instruction information buffer entry can be provided by the same buffer, and this disclosure does not limit the specifics.

[0078] For a buffer, a buffer entry is its basic storage unit, and each entry typically corresponds to buffering one instruction or one data item.

[0079] The following example illustrates this, where multiple instruction buffers are provided by an instruction buffer, and at least one branch instruction information buffer is provided by a branch instruction information buffer.

[0080] Figure 6 An exemplary circuit framework diagram of a processing method for an execution instruction pipeline provided in at least one embodiment of the present disclosure is shown.

[0081] like Figure 6 As shown, it includes an instruction cache 12, an instruction fetch pipeline 20, a buffer 30, an instruction fetch control circuit 40, an instruction prefetch circuit 50, a branch prediction module 60, a masking module 70, and a subsequent pipeline 80. The instruction fetch pipeline 20 includes fetch stages 0 to fetch stages n, where n is a positive integer. The buffer 30 includes an instruction buffer 31 and a branch instruction information buffer 32.

[0082] For example, a first decoder can be configured at the last instruction fetch stage of the instruction fetch pipeline. This first decoder is used to decode the instructions in the last instruction fetch stage, which are also called the instructions processed in the current clock cycle.

[0083] For example, the branch prediction module 60 mentioned above is a subsequent branch prediction in the instruction fetching stage. Figure 1 The branch prediction shown is a preceding branch prediction. For example, this branch prediction module 60 differs from the preceding branch prediction in that the preceding branch prediction performs branch prediction based on the instruction's PC value and the Global History Register (GHR); the GHR is used to record the history of jump or non-jump results of the most recently executed branch instructions. For example, a shift register can be used to record global branch patterns and identify the correlation between branches.

[0084] In addition to obtaining PC value and GHR information, the branch prediction module 60 can also accurately predict branches based on the decoded branch instruction information. That is, it can determine the instruction jump type (direct jump, indirect jump or conditional jump), operand source and jump direction (back branch path or forward branch path), thereby reducing the uncertainty brought about by relying solely on PC value and GHR for branch prediction and achieving more accurate judgment.

[0085] For example, the prediction result obtained by the branch prediction module 60 for the branch instruction prediction may include the branch path (jump direction) and the target address of the target instruction of the corresponding branch path. The target address may be the sum of the PC value and the offset.

[0086] For example, the branch prediction module 60 is also used to determine the state of the buffer device 30, which is an idle state, a refill state, or a standby state that has not yet been started.

[0087] It should be noted that this disclosure does not limit the specific location of the first decoder that decodes the instruction processed in the current clock cycle, and the purpose of decoding the instruction processed in the current clock cycle is to obtain more instruction information. In addition to the method described above, other methods that can obtain information such as the instruction jump type, operand source and jump direction of the branch instruction can also be used, and this disclosure does not limit them.

[0088] During the instruction fetch stage, each instruction can be fetched into the instruction fetch pipeline 20 via the instruction cache 12, and then passed from the instruction fetch pipeline 20 to the buffer device 30. For the instruction stream passed in the instruction fetch pipeline 20, the instruction fetch control circuit 40 can identify the loop body in the instruction stream and determine whether the identified loop body meets the loop body storage conditions.

[0089] In some embodiments of this disclosure, the above processing method may further include: determining an end branch instruction and determining a start instruction; wherein, the start instruction is used to identify the beginning of the loop body, and the start instruction is the instruction pointed to by the back jump branch in the end branch instruction.

[0090] For example, the instruction fetch control circuit 40 can record the branch instruction A that bounces back during the instruction fetch process. If the branch instruction A bounces back at least once afterward, it can be used as the end branch instruction.

[0091] For example, before using branch instruction A as the end branch instruction, the instruction fetch control circuit 40 also recognizes branch instruction B that has bounced back, and can record branch instruction B at the same time.

[0092] For example, the instruction fetch control circuit 40 is provided with a register array, which is used to record branch instructions that bounce back during the instruction fetch process, so as to use the recorded branch instructions as a candidate end branch instruction set.

[0093] For example, the instruction fetch control circuit 40 can determine whether an instruction is a branch instruction based on the decoding result of the instruction processed in the current clock cycle, and record the target address of the back jump branch in the branch instruction, such as recording the sum of the PC value and the offset.

[0094] In some embodiments of this disclosure, the branch termination instruction is determined from a set of candidate branch termination instructions, which records a first candidate branch instruction and a second candidate branch instruction that bounced back during the instruction fetch process.

[0095] The above processing method may further include: in response to the first candidate branch instruction jumping back before the second candidate branch instruction, using the first candidate branch instruction as the end branch instruction.

[0096] For example, branch instruction A can be considered the first candidate branch instruction, and branch instruction B can be considered the second candidate branch instruction. If it is detected that branch instruction A jumps back before branch instruction B, then branch instruction A can be used as the ending branch instruction. Correspondingly, the instruction pointed to by the jump of branch instruction A is the starting instruction.

[0097] For example, branch instruction B can be considered the first candidate branch instruction, and branch instruction A can be considered the second candidate branch instruction. If branch instruction B is detected to have a back jump before branch instruction A, then branch instruction B can be used as the ending branch instruction. Correspondingly, the instruction pointed to by the back jump of branch instruction B is the starting instruction.

[0098] After determining the end branch instruction and the start branch instruction, that is, the loop body to be stored in the buffer device 30 is determined, the instruction fetch control circuit 40 can determine whether the loop body meets the loop body storage conditions, so as to control the loop body that meets the loop storage conditions to be stored in the buffer device 30.

[0099] In some embodiments of this disclosure, the above processing method may further include: storing the loop body into a buffer device in response to the loop body meeting the loop body storage condition; wherein the loop body storage condition includes at least one of the loop body size condition and the loop body jump condition.

[0100] For example, loop body size conditions include a first number of multiple instructions that is less than or equal to a second number of multiple instruction buffer entries, and a third number of at least one branch instruction that is less than or equal to a fourth number of at least one branch instruction information buffer entry.

[0101] For example, the identified loop body 1 includes 6 instructions: instruction a, instruction b, instruction c, instruction d, instruction e, and branch instruction A; branch instruction A is the end branch instruction, and instruction d is the intermediate branch instruction. Therefore, the first quantity of the multiple instructions in loop body 1 is 6, and the third quantity of at least one branch instruction in loop body 1 is 2. If the second quantity of multiple instruction buffer entries is less than 6, the loop body size condition is not met; if the second quantity of multiple instruction buffer entries is greater than 6, and the fourth quantity of at least one branch instruction information buffer entry is less than 2, the loop body size condition is not met.

[0102] For example, the second number of multiple instruction buffer entries can be determined by the capacity of instruction buffer 31, and the fourth number of at least one branch instruction information buffer entry can be determined by the capacity of branch instruction information buffer 32.

[0103] For example, since not all instructions in a loop are branch instructions, the fourth number of at least one branch instruction information buffer can be set to be less than the second number of multiple instruction buffers. The specific number can be set as needed, and this disclosure does not impose any restrictions.

[0104] For example, when storing each instruction in the loop body, the instruction buffer 31 can also store the instruction information of each instruction in the loop body, such as the instruction type, exception flag, instruction width, etc. This disclosure does not limit this.

[0105] For example, the branch instruction information stored in the branch instruction information buffer 32 may include the branch instruction's own address (PC), the target address of the target instruction pointed to by the branch instruction (such as PC+offset), the type of the branch instruction, and the jump situation when the branch instruction is stored (the first branch prediction result below), etc. This disclosure does not limit this.

[0106] For example, loop body jump conditions include the following: the end branch prediction result of the end branch instruction is a bounce, and the end branch prediction result is the result of the branch prediction of the end branch instruction during the storage of the loop body.

[0107] For example, during the storage of loop body 1, it is predicted whether the ending branch instruction (branch instruction A) will continue to bounce back. If the prediction result of the ending branch is that a bounce will occur, the loop body is stored. If the prediction result of the ending branch is that a bounce will not occur, the buffer device 30 (such as instructions a, b, c, d, and e that have already been stored in the buffer device) can be flushed, that is, there is no need to store loop body 1.

[0108] For example, the prediction result of the ending branch can be determined by the branch prediction module 60. For example, for the intermediate branch instruction in the loop body, the branch prediction module 60 will also perform branch prediction during the storage of the loop body and record the intermediate branch prediction result.

[0109] After the buffer 30 stores the loop body, the prefetch circuit 50 can determine the prefetch instruction information based on the branch instruction information of the first branch instruction stored in the branch instruction information buffer 32 (including the first branch prediction result with the first branch information), and send a prefetch signal to obtain subsequent instruction delivery. For example, the prefetch circuit 50 can send a redirection signal (Change Flow) to the instruction fetch pipeline 20 as a prefetch signal.

[0110] The redirection signal can transmit prefetch instruction information, and use the prefetch address pointed to by the prefetch instruction information as the address for fetching subsequent instruction transmission. At the same time, it can control the refresh of the instruction fetch pipeline 20 to flush the current instruction transmission of the instruction fetch pipeline.

[0111] The prefetch instruction information can be used to determine the branch path that is different from the branch path corresponding to the first branch prediction result. That is, if the first branch prediction result of the first branch instruction is a bounce (corresponding to a bounce branch path), then the prefetch instruction information can be the instruction address of the target instruction of the forward branch path.

[0112] For example, if there is only a termination branch instruction in the loop body, the first branch instruction is the termination branch instruction; if there are both intermediate branch instructions and termination branch instructions in the loop body, the first branch instruction is the intermediate branch instruction. The specific details regarding obtaining subsequent instruction passes through prefetching instruction information and the obtained information are the same as described above, and will not be repeated here.

[0113] When the buffer device 30 serves as the instruction source for subsequent pipeline processing, since the subsequent pipeline will send a redirection signal to the preceding pipeline after exiting the loop stored in the buffer device 30, a shielding module can be used to shield the pre-fetched correct subsequent transmission instructions to prevent them from being overwritten.

[0114] In some embodiments of this disclosure, the above processing method may further include: in response to receiving a first redirection signal from a subsequent pipeline, when the first instruction information of the first instruction pointed to by the first redirection signal matches the prefetch instruction information, shielding the flushing effect of the first redirection signal on the instruction fetch pipeline; and in response to not receiving the first redirection signal and receiving a second redirection signal, when the second instruction information of the second instruction pointed to by the second redirection signal matches the prefetch instruction information, shielding the flushing effect of the second redirection signal on the instruction fetch pipeline.

[0115] The prefetch instruction information is used to obtain subsequent transmission instructions, and the second redirection signal is determined based on the matching result between the first branch prediction result of the object branch instruction in the loop body when it is stored in the buffer device and the second branch prediction result of the object branch instruction when it is supplied to the subsequent pipeline for processing.

[0116] "Object branch instruction" refers to a branch instruction that describes an object. It can refer to either the intermediate branch instruction or the termination branch instruction mentioned above. When the object branch instruction refers to the termination branch instruction, the prediction result of the first branch is the prediction result of the termination branch.

[0117] In some embodiments of this disclosure, the above processing method may further include: issuing a second redirection signal in response to the inconsistency between the first branch prediction result and the second branch prediction result.

[0118] See also Figure 6 When the loop body is processed by the subsequent pipeline, the branch prediction module 60 performs branch prediction on the object branch instruction to obtain the second branch prediction result. The branch prediction module 60 can obtain the first branch prediction result of the object branch instruction information recorded in the branch instruction information buffer 32 and compare the first branch prediction result with the second branch prediction result.

[0119] When the prediction result of the first branch is consistent with the prediction result of the second branch, it is considered that the loop body is still looping and no processing is required. When the prediction result of the first branch is inconsistent with the prediction result of the second branch, it is considered that the loop body has been exited. At this time, the branch prediction module will send a second redirection signal, which includes the address of the prediction execution instruction (second instruction).

[0120] The first branch prediction result can be written into at least one branch instruction information buffer item in the branch instruction information buffer 32 during the process of storing the object branch instruction into the buffer device 30. The first branch prediction result can be obtained from the branch instruction information buffer 32 during comparison.

[0121] For example, when an object branch instruction is supplied to the subsequent pipeline 80 for processing, the subsequent pipeline 80 may issue a first redirection signal in cases such as the second branch prediction result of the branch prediction module 60 being incorrect, the loop body being completed, or the jump target address being abnormal. The first redirection signal includes the address of the actual executed instruction (first instruction).

[0122] When the shielding module 70 receives both the first redirection signal and the second redirection signal, since the first redirection signal issued by the subsequent pipeline 80 includes the address information of the actual executed instruction, that is, the correct address information, the first redirection signal is taken as the standard, and the shielding process is determined based on the matching of the first redirection signal and the prefetched instruction information.

[0123] The first instruction information of the first instruction pointed to by the first redirection signal matches the prefetch instruction information, that is, the address of the actual executed instruction is consistent with the prefetch address in the prefetch instruction information.

[0124] The second instruction information of the second instruction pointed to by the second redirection signal matches the prefetch instruction information, that is, the address of the predicted execution instruction is consistent with the prefetch address in the prefetch instruction information.

[0125] In the matching cases listed above, by shielding the flushing effect of the first redirection signal or the second redirection signal on the instruction fetch pipeline 20, it can be determined that the subsequent transmission instructions obtained in the instruction fetch pipeline 20 are correct, thus avoiding incorrect flushing that could cause instruction fetch bubbles after exiting the loop.

[0126] It should be noted that the shielding module 70 shields the scouring effect on the finger fetching pipeline 20. The first redirection signal or the second redirection signal still has a scouring effect on the buffer device 30 and the transmitting unit included in the subsequent pipeline.

[0127] Figure 7 A block diagram of a processing apparatus for an instruction pipeline provided in at least one embodiment of the present disclosure is shown.

[0128] like Figure 7 As shown, the instruction pipeline processing device 100 includes an instruction fetch control circuit 40 and an instruction prefetch circuit 50.

[0129] The instruction fetch control circuit 40 is configured to fetch the loop body. The loop body includes multiple instructions, including an end branch instruction. The end branch instruction is used to indicate the end of the loop body and includes a jump branch path.

[0130] The prefetch circuit 50 is configured to, in response to the loop body passing the instruction stored in the fetch pipeline through the instruction fetch pipeline, flush the current instruction passed in the instruction fetch pipeline and retrieve the subsequent instruction passed in the instruction fetch pipeline.

[0131] The subsequent pass instruction is the instruction executed after the loop body exits the loop, and the current pass instruction is different from the subsequent pass instruction.

[0132] In some embodiments of this disclosure, the instruction fetch control circuit 40 may also be configured to determine an end branch instruction and a start instruction; wherein, the start instruction is used to identify the beginning of the loop body, and the start instruction is the instruction pointed to by the back jump branch path in the end branch instruction.

[0133] For example, the end branch instruction is determined from the candidate end branch instruction set. The candidate end branch instruction set records the first candidate branch instruction and the second candidate branch instruction that bounced back during the instruction fetch process. The instruction fetch control circuit 40 is also configured to use the first candidate branch instruction as the end branch instruction in response to the first candidate branch instruction bouncing back before the second candidate branch instruction.

[0134] In some embodiments of this disclosure, the instruction fetch control circuit 40 may also be configured to store the loop body into the buffer device in response to the loop body meeting the loop body storage condition; wherein the loop body storage condition includes at least one of the loop body size condition and the loop body jump condition.

[0135] For example, the buffer device may include multiple instruction buffer entries and at least one branch instruction information buffer entry. The multiple instruction buffer entries are used to store multiple instructions, and the at least one branch instruction information buffer entry is used to store information about branch instructions among the multiple instructions. The loop body size condition includes a first number of multiple instructions that is less than or equal to a second number of multiple instruction buffer entries, and a third number of at least one branch instruction that is less than or equal to a fourth number of at least one branch instruction information buffer entry. The loop body jump condition includes a final branch prediction result of the final branch instruction that results in a bounce, and the final branch prediction result is the result of branch prediction performed on the final branch instruction during the storage of the loop body.

[0136] In some embodiments of this disclosure, the processing apparatus 100 of the instruction pipeline may further include a shielding module 70.

[0137] The shielding module 70 is configured to, in response to receiving a first redirection signal from a subsequent pipeline, shield the fetch pipeline from the flushing effect of the first redirection signal when the first instruction information of the first instruction pointed to by the first redirection signal matches the prefetch instruction information; and in response to not receiving the first redirection signal and receiving a second redirection signal, shield the fetch pipeline from the flushing effect of the second redirection signal when the second instruction information of the second instruction pointed to by the second redirection signal matches the prefetch instruction information, wherein the prefetch instruction information is used to obtain subsequent transmission instructions, and the second redirection signal is determined based on the matching result between the first branch prediction result of the object branch instruction in the loop body when it is stored in the buffer device and the second branch prediction result of the object branch instruction when it is processed by the subsequent pipeline.

[0138] In some embodiments of this disclosure, the processing apparatus 100 of the instruction pipeline may further include a branch prediction module 60.

[0139] The branch prediction module 60 can be configured to issue a second redirection signal in response to a discrepancy between the first branch prediction result and the second branch prediction result.

[0140] In some embodiments of this disclosure, the instruction fetch control circuit 40 is further configured to configure the buffer device to enter a first state in response to the loop body being stored in the buffer device; wherein the first state indicates that the buffer device stops receiving the currently transmitted instruction in the instruction fetch pipeline and serves as an instruction source for subsequent pipeline processing.

[0141] Other aspects of the instruction pipeline processing apparatus of the above embodiments of this disclosure can be found in the above instruction pipeline processing method and its additional aspects, which will not be repeated here.

[0142] The technical effects of the instruction pipeline processing apparatus of the above embodiments of this disclosure are the same as the technical effects of the instruction pipeline processing method described above, and therefore will not be repeated.

[0143] At least one embodiment of this disclosure provides a processor as the processing apparatus for an instruction pipeline.

[0144] At least one embodiment of this disclosure also provides a processor, which may be any processing circuit with processing capabilities implemented by hardware or firmware, such as a central processing unit (CPU) or coprocessor, a microcontroller unit (MCU) or digital signal processor (DSP). For example, a coprocessor may be an accelerator, a graphics processing unit (GPU), a programmable logic array or any other processor with instruction execution capabilities.

[0145] The technical effects of the processor in the above embodiments of this disclosure are the same as those of the instruction pipeline processing device described above, and therefore will not be repeated.

[0146] Figure 8 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0147] like Figure 8 As shown, at least one embodiment of the present disclosure provides an electronic device 200 including at least one memory 110 and at least one processor 120.

[0148] The aforementioned memory 110 is configured to store computer-executable instructions.

[0149] The processor 120 described above is configured to execute computer-executable instructions, which, when executed by at least one processor, implement the instruction pipeline processing method provided in any embodiment of this disclosure.

[0150] The aforementioned memory 110 may include, for example, any memory unit with storage function such as a semiconductor memory cell, a register, a storage queue, etc.

[0151] The processor 120 described above can be any processing circuit with processing capabilities implemented in hardware or firmware, such as a programmable logic array or any other processing unit with instruction execution functions. The embodiments of this disclosure do not limit the implementation of at least one memory 110 and at least one processor 120.

[0152] Figure 9 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0153] Figure 9 The illustrated electronic device 1000 is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this disclosure. For example, the electronic device 1000 may include the processor 120 in at least one embodiment of this disclosure.

[0154] The electronic devices in this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 9 The illustrated electronic device 1000 is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0155] For example, refer to Figure 9 In some examples, electronic device 1000 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1001, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded into random access memory (RAM) 1003 from instruction pipeline processing method 1008. For example, processing device 1001 can be a processor as described in any of the above embodiments of this disclosure. Various programs and data required for the operation of the computer system are also stored in RAM 1003. Processing device 1001, ROM 1002, and RAM 1003 are connected via interconnection network 1004. Input / output (I / O) interface 1005 is also connected to interconnection network 1004.

[0156] For example, the following components can be connected to I / O interface 1005: input devices 1006 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1007 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; instruction pipeline processing methods 1008 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009, such as network interface cards including LAN cards, modems, etc. Communication device 1009 allows electronic device 1000 to exchange data wirelessly or wiredly with other devices, performing communication processing via networks such as the Internet. Drive 1010 is also connected to I / O interface 1005 as needed. Removable media 1011, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 1010 as needed so that computer programs read from them can be installed into instruction pipeline processing methods 1008 as needed. Although Figure 9 An electronic device 1000 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0157] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 1009 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0158] For example, the electronic device 1000 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or any combination of data processing device and hardware. The embodiments disclosed herein do not limit this.

[0159] The following points need to be clarified regarding this disclosure:

[0160] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0161] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0162] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for instruction pipeline processing, comprising: Obtain the loop body, wherein the loop body includes a branch termination instruction among its multiple instructions, wherein the branch termination instruction is used to indicate the end of the loop body, and the branch termination instruction includes a jumpback branch path; and In response to the loop body being passed to the buffer device via the finger fetch pipeline, the current transmission instruction of the finger fetch pipeline is flushed, and subsequent transmission instructions are obtained into the finger fetch pipeline; The subsequent pass instruction is the instruction executed after the loop body exits the loop, and the current pass instruction is different from the subsequent pass instruction.

2. The instruction pipeline processing method according to claim 1, wherein, The acquisition loop body further includes: Determine the end branch instruction and determine the start instruction; The start instruction is used to identify the beginning of the loop body, and the start instruction is the instruction pointed to by the back jump branch path in the end branch instruction.

3. The instruction pipeline processing method according to claim 2, wherein, The branch termination instruction is determined from a set of candidate branch termination instructions, which records the first and second candidate branch instructions that bounced back during the instruction fetch process. The step of determining the branch termination instruction includes: In response to the first candidate branch instruction bouncing back before the second candidate branch instruction, the first candidate branch instruction is used as the end branch instruction.

4. The instruction pipeline processing method according to claim 1 further includes: In response to the loop body satisfying the loop body storage condition, the loop body is stored in the buffer device; The loop body storage conditions include at least one of the loop body size conditions and the loop body jump conditions.

5. The instruction pipeline processing method according to claim 4, wherein, The buffer device includes multiple instruction buffer items and at least one branch instruction information buffer item. The multiple instruction buffer items are used to store the multiple instructions, and the at least one branch instruction information buffer item is used to store information about the branch instructions in the multiple instructions. The loop body size condition includes a first number of the plurality of instructions being less than or equal to a second number of the plurality of instruction buffer items, and a third number of the at least one branch instruction being less than or equal to a fourth number of the at least one branch instruction information buffer item. The loop body jump condition includes that the end branch prediction result of the end branch instruction is a bounce, and the end branch prediction result is the result of branch prediction of the end branch instruction during the storage of the loop body.

6. The instruction pipeline processing method according to claim 1 further includes: In response to receiving the first redirection signal from the subsequent pipeline, when the first instruction information of the first instruction pointed to by the first redirection signal matches the prefetch instruction information, the flushing effect of the first redirection signal on the instruction fetch pipeline is shielded. as well as In response to the absence of the first redirection signal and the receipt of the second redirection signal, when the second instruction information of the second instruction pointed to by the second redirection signal matches the prefetch instruction information, the flushing effect of the second redirection signal on the instruction fetch pipeline is blocked. The prefetch instruction information is used to obtain the subsequent transmission instruction, and the second redirection signal is determined based on the matching result between the first branch prediction result of the object branch instruction in the loop body when it is stored in the buffer device and the second branch prediction result of the object branch instruction when it is processed by the subsequent pipeline.

7. The instruction pipeline processing method according to claim 6 further includes: In response to the inconsistency between the first branch prediction result and the second branch prediction result, the second redirection signal is issued.

8. The instruction pipeline processing method according to any one of claims 1-7, further comprising: In response to the loop body being stored in the buffer device, the buffer device is configured to enter a first state; The first state indicates that the buffer device stops receiving the current instruction being passed in the instruction fetch pipeline and uses it as an instruction source for subsequent pipeline processing.

9. A processing apparatus for an instruction pipeline, comprising: The instruction fetch control circuit is configured to fetch a loop body, wherein the loop body includes an end branch instruction among its multiple instructions, and the end branch instruction is used to indicate the end of the loop body, and the end branch instruction includes a jumpback branch path; The prefetch circuit is configured to, in response to the loop body passing the instruction stored in the fetch pipeline through the fetch pipeline to the buffer device, flush the current instruction passed by the fetch pipeline and obtain subsequent instruction passed to the fetch pipeline; The subsequent pass instruction is the instruction executed after the loop body exits the loop, and the current pass instruction is different from the subsequent pass instruction.

10. The processing apparatus for the instruction pipeline according to claim 9, wherein, The instruction fetch control circuit is further configured to store the loop body into the buffer device in response to the loop body meeting the loop body storage condition. The conditions for storing the loop body include the loop body size condition and the loop body jump condition.

11. The instruction pipeline processing apparatus according to claim 10, wherein, The buffer device includes multiple instruction buffer items and at least one branch instruction information buffer item. The multiple instruction buffer items are used to store the multiple instructions, and the at least one branch instruction information buffer item is used to store information of at least one branch instruction among the multiple instructions. The loop body size condition includes a first number of the plurality of instructions being less than or equal to a second number of the plurality of instruction buffer items, and a third number of the at least one branch instruction being less than or equal to a fourth number of the at least one branch instruction information buffer item. The loop body jump condition includes that the end branch prediction result of the end branch instruction is a bounce, and the end branch prediction result is the result of branch prediction of the end branch instruction during the storage of the loop body.

12. The instruction pipeline processing apparatus according to claim 9, further comprising: The shielding module is configured to, in response to receiving a first redirection signal from the subsequent pipeline, shield the flushing effect of the first redirection signal on the instruction fetch pipeline when the first instruction information of the first instruction pointed to by the first redirection signal matches the prefetch instruction information. as well as In response to the absence of the first redirection signal and the receipt of the second redirection signal, when the second instruction information of the second instruction pointed to by the second redirection signal matches the prefetch instruction information, the flushing effect of the second redirection signal on the instruction fetch pipeline is blocked. The prefetch instruction information is used to obtain the subsequent transmission instruction; the second redirection signal is determined based on the matching result between the first branch prediction result of the object branch instruction in the loop body when it is stored in the buffer device and the second branch prediction result of the object branch instruction when it is processed by the subsequent pipeline.

13. The instruction pipeline processing apparatus according to claim 12, further comprising: The branch prediction module is configured to issue the second redirection signal in response to a discrepancy between the first branch prediction result and the second branch prediction result.

14. The processing apparatus for an instruction pipeline according to any one of claims 9-13, wherein, The processing device is a processor.

15. An electronic device comprising: At least one memory is configured to store computer-executable instructions; as well as At least one processor is configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the at least one processor, implement the instruction pipeline processing method according to any one of claims 1-8.

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