A clock data recovery method, system and apparatus

Abstract

This invention discloses a clock data recovery method, system, and apparatus. After the sampling module samples each data point in the data to be sampled based on the clock signal generated by the clock generation module, the phase of the clock signal generated by the clock generation module is adjusted by determining the offset direction of the actual sampling position of each data point in the data to be sampled relative to a preset sampling position. This adjustment continues until the sampling position when the sampling module samples each data point in the data to be sampled based on the clock signal with the adjusted clock phase is the preset sampling position. In this application, adjusting the phase of the clock signal by determining the offset direction of the actual sampling position of the sampled data relative to the preset sampling position ensures that the sampling module samples the data at the preset sampling position of each data point in the data to be sampled, improving the accuracy of data sampling and thus guaranteeing the accuracy of data transmission.

Description

Technical Field

[0001] This invention relates to the field of data transmission, and in particular to a clock data recovery method, system, and apparatus. Background Technology

[0002] During data transmission, when converting serial data into parallel data, it is necessary to sample the serial data. When the serial data transmission rate is slow, the sampling clock skew is not severe, and the serial data can be sampled accurately. However, if the serial data transmission rate is fast, severe sampling clock skew will prevent each data in the serial data from being sampled accurately, resulting in deviations in the sampled data and causing the data receiver to receive incorrect data. Therefore, how to adjust the phase of the clock signal to ensure accurate sampling of serial data based on the recovered clock signal is a problem that urgently needs to be solved in this field. Summary of the Invention

[0003] The purpose of this invention is to provide a clock data recovery method, system, and apparatus. By determining the offset direction of the actual sampling position of the sampled data relative to the preset sampling position, the phase of the clock signal is adjusted so that the sampling module samples the data at the preset sampling position of each data in the data to be sampled, thereby improving the accuracy of data sampling and ensuring the accuracy of data transmission.

[0004] To address the aforementioned technical problems, this invention provides a clock data recovery method applied to a logic unit. The logic unit is connected to a sampling module and a clock generation module. The clock generation module generates a clock signal. The sampling module samples each data point in the data to be sampled based on the clock signal to obtain various sampled data points. The method includes:

[0005] Determine the offset direction of the actual sampling position of each data in the data to be sampled relative to the preset sampling position;

[0006] The phase of the clock signal generated by the clock generation module is adjusted based on the offset direction until the sampling module samples each data in the data to be sampled based on the clock signal with the adjusted clock phase, and the sampling position when obtaining each sampled data is the preset sampling position.

[0007] Preferably, the clock signal generation module includes a phase-locked loop (PLL) and a phase interpolator. The PLL is used to generate a clock signal, and the phase interpolator is used to adjust the phase of the clock signal output by the PLL and transmit it to the sampling module based on the control of the logic unit.

[0008] The phase of the clock signal generated by the clock generation module is adjusted based on the offset direction until the sampling module samples each data point in the data to be sampled based on the clock signal with the adjusted clock phase. The sampling position at which each sampled data point is obtained is the preset sampling position, including:

[0009] The configuration parameters of the phase interpolator are adjusted based on the offset direction so that the phase interpolator transmits the phase of the clock signal output by the phase-locked loop to the sampling module after adjusting the phase of the clock signal. The sampling position when the sampling module samples each data in the data to be sampled based on the clock signal after the clock phase is adjusted by the phase interpolator is the preset sampling position.

[0010] Preferably, the clock generation module is specifically used to generate clock signals with four phases, including a first-phase clock signal, a second-phase clock signal, a third-phase clock signal, and a fourth-phase clock signal in phase order; the sampling module is specifically used to sample each data in the data to be sampled based on each of the clock signals, and output the sampled data obtained based on the first-phase clock signal and the third-phase clock signal as the center position sampled data of each data in the data to be sampled, and output the sampled data obtained based on the second-phase clock signal and the fourth-phase clock signal as the edge position sampled data of each data in the data to be sampled; the sampled data includes the center position sampled data and the edge position sampled data;

[0011] Determining the offset direction of the actual sampling position of each data point in the data to be sampled relative to a preset sampling position includes:

[0012] Acquire the sampling data at each center position and each edge position output by the sampling module;

[0013] The sampled data at each center position and each sampled data at each edge position are arranged at intervals according to the order of the clock signals when the sampled data at each center position and each sampled data at each edge position are collected.

[0014] Based on the size relationship between the sampling data at each edge position and the sampling data at two adjacent center positions, the offset direction of the actual edge sampling position corresponding to each edge sampling data relative to the preset edge sampling position is determined, so as to determine the offset direction of each center sampling data relative to the preset center sampling position; the preset sampling position includes the preset edge sampling position and the preset center sampling position.

[0015] Preferably, the offset direction of the actual edge sampling position corresponding to each edge sampling data relative to a preset edge sampling position is determined based on the magnitude relationship between the sampling data at each edge position and the sampling data at two adjacent center positions, thereby determining the offset direction of each center sampling data relative to a preset center sampling position; the preset sampling position includes the preset edge sampling position and the preset center sampling position, including:

[0016] Set a first reference value and a second reference value, and the initial values ​​of the first reference value and the second reference value are both 0;

[0017] According to the order of the sampled data at each center position and the sampled data at each edge position after being arranged at intervals, the first sampled data at the edge position is set as the current sampled data at the edge position.

[0018] Determine the previous and next center position sampling data adjacent to the current edge position sampling data;

[0019] If the current edge position sampling data is the same as the previous center position sampling data, the first reference value is incremented by one; if the current edge position sampling data is the same as the next center position sampling data, the second reference value is incremented by one.

[0020] The next edge position sampling data of the current edge position sampling data is set as the current edge position sampling data, and the step of determining the previous and next center position sampling data adjacent to the current edge position sampling data is returned until the next center position sampling data of the current edge position sampling data is the last center position sampling data.

[0021] If the first reference value is greater than the second reference value, the parameters of the clock generation module are adjusted to shift the phase of each clock signal output by the clock generation module backward; if the first reference value is less than the second reference value, the parameters of the clock generation module are adjusted to shift the phase of each clock signal output by the clock generation module forward; if the first reference value is equal to the second reference value, the parameters of the clock generation module are kept unchanged to keep the phase of each clock signal output by the clock generation module unchanged.

[0022] Preferably, after acquiring the sampling data at each center position and each edge position output by the sampling module, the method further includes:

[0023] Determine whether the number of the obtained center position sampling data and edge position sampling data are both the first preset number. If so, proceed to the step of arranging the center position sampling data and edge position sampling data at intervals according to the order of the clock signals when collecting each center position sampling data and each edge position sampling data.

[0024] Set the clock adjustment value to an initial value of 0, and proceed to the step of setting the first reference value and the second reference value, where the initial values ​​of the first reference value and the second reference value are both 0;

[0025] If the first reference value is greater than the second reference value, the parameters of the clock generation module are adjusted to shift the phase of each clock signal output by the clock generation module backward; if the first reference value is less than the second reference value, the parameters of the clock generation module are adjusted to shift the phase of each clock signal output by the clock generation module forward; if the first reference value is equal to the second reference value, the parameters of the clock generation module are kept unchanged. After ensuring that the phase of each clock signal output by the clock generation module remains unchanged, the process further includes:

[0026] Increment the value of the clock adjustment value by 1, and determine whether the clock adjustment value is the preset clock adjustment value;

[0027] If not, return to the step of obtaining the sampling data of each center position and each edge position output by the sampling module;

[0028] If so, the phase of each clock signal generated by the clock generation module is locked, and the clock adjustment value is cleared to zero.

[0029] Preferably, the step of setting the next edge position sampling data of the current edge position sampling data as the current edge position sampling data and returning to the step of determining the previous and next center position sampling data adjacent to the current edge position sampling data, until the next center position sampling data of the current edge position sampling data is the last center position sampling data, further includes:

[0030] Determine whether the phase of each clock signal generated by the clock generation module is locked;

[0031] If so, when the absolute value of the difference between the first reference value and the second reference value is not less than a preset difference, the phase of each clock signal generated by the clock generation module is unlocked, and the process proceeds to the following steps: if the first reference value is greater than the second reference value, the parameters of the clock generation module are adjusted to shift the phase of each clock signal output by the clock generation module backward; if the first reference value is less than the second reference value, the parameters of the clock generation module are adjusted to shift the phase of each clock signal output by the clock generation module forward; if the first reference value is equal to the second reference value, the parameters of the clock generation module are kept unchanged to adjust the phase of each clock signal output by the clock generation module.

[0032] When the absolute value of the difference between the first reference value and the second reference value is less than the preset difference, the process returns to the step of obtaining the sampling data of each center position and each edge position output by the sampling module.

[0033] If not, proceed to the step of: if the first reference value is greater than the second reference value, adjust the parameters of the clock generation module to shift the phase of each clock signal output by the clock generation module backward; if the first reference value is less than the second reference value, adjust the parameters of the clock generation module to shift the phase of each clock signal output by the clock generation module forward; if the first reference value is equal to the second reference value, keep the parameters of the clock generation module unchanged so that the phase of each clock signal output by the clock generation module remains unchanged.

[0034] Preferably, before determining the offset direction of the actual sampling position of each data point in the data to be sampled relative to the preset sampling position, the method further includes:

[0035] Determine whether the frequency of the data to be sampled is less than the frequency of the clock signal generated by the clock generation module;

[0036] If not, proceed to the step of determining the offset direction of the actual sampling position of each data in the data to be sampled relative to the preset sampling position;

[0037] If so, then each of the sampled data output by the sampling module is acquired, and after the number of acquired sampled data is a second preset number, the sampled data is arranged according to the order of the clock signals when each of the sampled data is acquired;

[0038] Each of the sampled data is divided into several data groups, and the amount of data in each data group is a first preset number. If the second preset number is not an integer ratio to the first preset number, the sampled data is reused.

[0039] Determine the number of target data points in each of the data groups;

[0040] The data group with the largest number of each of the aforementioned data groups is set as the target data group;

[0041] The sampling clock of each sampled data in the target data group is determined as the target sampling clock;

[0042] Each of the target sampling clocks is set as a clock for sampling at a preset sampling position of each data point of the data to be sampled.

[0043] To address the aforementioned technical problems, this application also provides a clock data recovery system applied to a logic unit. The logic unit is connected to a sampling module and a clock generation module. The clock generation module generates a clock signal. The sampling module samples each data point in the data to be sampled based on the clock signal to obtain various sampled data points. The system includes:

[0044] The first determining unit is used to determine the offset direction of the actual sampling position of each data in the data to be sampled relative to the preset sampling position.

[0045] A phase adjustment unit is used to adjust the phase of the clock signal generated by the clock generation module based on the offset direction, until the sampling position when the sampling module samples each data in the data to be sampled based on the clock signal after the clock phase adjustment is the preset sampling position.

[0046] To address the aforementioned technical problems, this application also provides a clock data recovery device, including a sampling module, a clock generation module, and a logic unit;

[0047] The logic unit is connected to the sampling module and the clock generation module, and is used to perform the steps of the clock data recovery method as described above.

[0048] The clock generation module is used to generate clock signals;

[0049] The sampling module is used to sample each data in the data to be sampled based on the clock signal to obtain each sampled data.

[0050] Preferably, the clock signal generation module includes a phase-locked loop (PLL) and a phase interpolator. The PLL is used to output a clock signal, and the phase interpolator is used to adjust the phase of the clock signal output by the PLL and transmit it to the sampling module based on the control of the logic unit.

[0051] This application provides a clock data recovery method, system, and apparatus. After a sampling module samples each data point in the data to be sampled based on a clock signal generated by a clock generation module, the phase of the clock signal generated by the clock generation module is adjusted by determining the offset direction of the actual sampling position of each data point in the data to be sampled relative to a preset sampling position. This adjustment is made until the sampling position at which the sampling module samples each data point in the data to be sampled based on the clock signal with the adjusted clock phase is the preset sampling position. In this application, adjusting the phase of the clock signal by determining the offset direction of the actual sampling position of the sampled data relative to the preset sampling position ensures that the sampling module samples the data at the preset sampling position of each data point in the data to be sampled, improving the accuracy of data sampling and thus ensuring the accuracy of data transmission. Attached Figure Description

[0052] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 A flowchart illustrating a clock data recovery method provided in this application;

[0054] Figure 2 This application provides a schematic diagram of sampling data based on a four-phase clock signal.

[0055] Figure 3 A simulation diagram provided for this application;

[0056] Figure 4 Another simulation diagram provided for this application;

[0057] Figure 5 A schematic diagram of a clock data recovery device provided in this application;

[0058] Figure 6 This is a schematic diagram of the specific structure of a clock data recovery device provided in this application. Detailed Implementation

[0059] The core of this invention is to provide a clock data recovery method, system, and apparatus. By determining the offset direction of the actual sampling position of the sampled data relative to the preset sampling position, the phase of the clock signal is adjusted so that the sampling module samples the data at the preset sampling position of each data in the data to be sampled, thereby improving the accuracy of data sampling and ensuring the accuracy of data transmission.

[0060] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] Please refer to Figure 1 , Figure 1 This application provides a flowchart illustrating a clock data recovery method. The method is applied to logic unit 3, which is connected to sampling module 1 and clock generation module 2. Clock generation module 2 generates a clock signal. Sampling module 1 samples each data point in the data to be sampled based on the clock signal to obtain various sampled data. The method includes:

[0062] S11: Determine the offset direction of the actual sampling position of each data in the data to be sampled relative to the preset sampling position;

[0063] When sampling high-frequency data, clock skew is a common problem. If the data is sampled based on the skewed clock, incorrect data may be sampled. Therefore, the clock data needs to be restored before data transmission. This ensures that accurate data can be sampled when the data is sampled based on the restored clock, thus enabling the correct data to be transmitted.

[0064] In this embodiment, a preset sampling position is predetermined for correct data sampling. That is, if the sampling module 1 samples from the preset sampling position of each data when sampling data, the obtained sampled data becomes accurate data. Based on this, in this embodiment, the clock generation module 2 generates a clock signal so that the sampling module 1 samples the data to be sampled based on the clock signal generated by the clock generation module 2. Since the clock data has not been recovered at this time, the actual sampling position of the sampling module 1 sampling each data in the data to be sampled based on the clock signal is uncertain. The logic unit 3 determines the actual sampling position corresponding to each sampling position output by the sampling module 1, and determines the offset direction of the actual sampling position of each data relative to the preset sampling position, such as the actual sampling position leading the preset sampling position or the actual sampling position lagging behind the preset sampling position.

[0065] S12: Adjust the phase of the clock signal generated by the clock generation module 2 based on the offset direction until the sampling module 1 samples each data in the data to be sampled based on the clock signal after the clock phase adjustment to obtain each sampled data. The sampling position is the preset sampling position.

[0066] After determining the offset direction of the actual sampling position relative to the preset sampling position, the phase of the clock signal can be adjusted based on the offset direction. If the actual sampling position is ahead of the preset sampling position, the phase of the clock signal generated by the clock generation module 2 is adjusted backward. If the actual sampling position is behind the preset sampling position, the phase of the clock signal generated by the clock generation module 2 is adjusted forward, so that the sampling position of the sampling module 1 when sampling each data in the data to be sampled based on the clock signal after the clock phase adjustment is the preset sampling position.

[0067] Specifically, if after adjusting the phase of the clock signal based on the offset direction, the sampling position of the sampling module 1 when sampling each data in the data to be sampled based on the clock signal with the adjusted clock phase is still not preset, then the offset direction of the actual sampling position of the sampling module 1 when sampling each data in the data to be sampled based on the clock signal with the adjusted clock phase relative to the preset sampling position is determined again, so as to adjust the phase of the clock signal again based on the offset direction, and determine whether the sampling position of the sampling module 1 when sampling each data in the data to be sampled based on the clock signal with the adjusted clock phase is the preset sampling position. This process is repeated until the sampling position of the sampling module 1 when sampling each data in the data to be sampled is the preset sampling position.

[0068] It should be noted that the above method is mainly applied to equalization of high-speed interfaces of chips, and is implemented by connecting logic units with sampling modules and clock generation modules.

[0069] In summary, this application adjusts the phase of the clock signal by determining the offset direction of the actual sampling position of the sampled data relative to the preset sampling position, so that the sampling module 1 samples the data at the preset sampling position of each data in the data to be sampled, thereby improving the accuracy of data sampling and ensuring the accuracy of data transmission.

[0070] Based on the above embodiments:

[0071] In a preferred embodiment, the clock signal generation module includes a phase-locked loop (PLL) and a phase interpolator. The PLL is used to generate a clock signal, and the phase interpolator is used to adjust the phase of the clock signal output by the PLL and transmit it to the sampling module 1 based on the control of the logic unit 3.

[0072] The phase of the clock signal generated by the clock generation module 2 is adjusted based on the offset direction until the sampling module 1 samples each data point in the data to be sampled based on the clock signal with the adjusted clock phase. The sampling position when obtaining each sampled data point is the preset sampling position, including:

[0073] The configuration parameters of the phase interpolator are adjusted based on the offset direction so that the phase interpolator transmits the phase of the clock signal output by the phase-locked loop to the sampling module 1 after adjusting the phase. The sampling module 1 then samples each data in the data to be sampled based on the clock signal after the phase adjustment by the phase interpolator, and the sampling position is the preset sampling position.

[0074] The clock signal generation module in this embodiment specifically includes a phase-locked loop and a phase interpolator. The clock signal is generated by the phase-locked loop and then transmitted to the phase interpolator. The logic unit 3 adjusts the configuration parameters of the phase interpolator to adjust the phase of the clock signal that is finally output to the sampling module 1.

[0075] In a preferred embodiment, the clock generation module 2 is specifically used to generate clock signals with four phases, including a first-phase clock signal, a second-phase clock signal, a third-phase clock signal, and a fourth-phase clock signal in phase order; the sampling module 1 is specifically used to sample each data in the data to be sampled based on each clock signal, and output the sampled data obtained based on the first-phase clock signal and the third-phase clock signal as the center position sampled data of each data in the data to be sampled, and output the sampled data obtained based on the second-phase clock signal and the fourth-phase clock signal as the edge position sampled data of each data in the data to be sampled; the sampled data includes center position sampled data and edge position sampled data;

[0076] Determine the offset direction of the actual sampling position of each data point in the data to be sampled relative to the preset sampling position, including:

[0077] Acquire the sampling data at each center position and each edge position output by sampling module 1;

[0078] The sampled data at each center position and each sampled data at each edge position are arranged at intervals according to the order of the clock signals when collecting sampled data at each center position and each edge position.

[0079] Based on the magnitude relationship between the sampled data at each edge position and the sampled data at the two adjacent center positions, the offset direction of the actual edge sampling position corresponding to each edge sampling data relative to the preset edge sampling position is determined, so as to determine the offset direction of each center sampling data relative to the preset center sampling position; the preset sampling position includes the preset edge sampling position and the preset center sampling position.

[0080] In this embodiment, the clock generation module 2 generates clock signals of four phases, in the following order: first phase clock signal, second phase clock signal, third phase clock signal, and fourth phase clock signal. That is, within the same cycle, the sampling module 1 first samples the data to be sampled based on the first phase clock signal to obtain a center position sample data, then samples based on the second phase clock signal to obtain an edge position sample data, then samples based on the third phase clock signal to obtain a center position sample data, and finally samples based on the fourth phase clock signal to obtain another edge position sample data. The logic unit 3 sorts the center position sample data and edge position sample data obtained by the sampling module 1 in each cycle at intervals, that is, sorts them in the order of one center position sample data, one edge position sample data, and one center position sample data. Each edge position sample data has two sides... For an adjacent center position sampling data, the offset direction of the actual edge sampling position relative to the preset edge sampling position is determined based on the magnitude relationship between each edge position sampling data and the two adjacent center position sampling data. For example, if the actual edge sampling position of the edge position sampling data is closer to the actual center sampling position of the previous center position sampling data based on the magnitude relationship between the edge position sampling data and the two adjacent center position sampling data, then the clock signal phase is determined to be leading, and logic unit 3 adjusts the clock signal phase backward; if the actual edge sampling position of the edge position sampling data is closer to the actual center sampling position of the next center position sampling data based on the magnitude relationship between the edge position sampling data and the two adjacent center position sampling data, then the clock signal phase is determined to be lagging, and logic unit 3 adjusts the clock signal phase forward.

[0081] It should be noted that sampling module 1 may include four samplers and two serial-to-parallel conversion modules. The two serial-to-parallel conversion modules can be 2-to-40-bit or 2-to-128-bit serial-to-parallel conversion modules. In this embodiment, 2-to-40-bit serial-to-parallel conversion modules are used as an example. The four samplers sample based on four phases of clock signals. Specifically, the first sampler samples based on the first phase of the clock signal, the second sampler samples based on the second phase of the clock signal, the third sampler samples based on the third phase of the clock signal, and the fourth sampler samples based on the fourth phase of the clock signal. The first and third samplers are connected to the first serial-to-parallel conversion module, i.e., the first serial-to-parallel conversion module. The 40 serial center position sampled data obtained by the first and third samplers are converted into 40-bit parallel center position sampled data, and these 40-bit parallel center position sampled data are arranged in the sampling order. The second and fourth samplers are connected to the second serial-to-parallel conversion module, that is, the second serial-to-parallel conversion module converts the 40 serial edge position sampled data obtained by the second and fourth samplers into 40-bit parallel edge position sampled data, and these 40-bit parallel edge position sampled data are also arranged in the sampling order. Then, the logic unit 3 arranges the 40 center position sampled data and 40 edge position sampled data output by the two serial-to-parallel conversion modules at intervals according to the sampling order.

[0082] In a preferred embodiment, the offset direction of the actual edge sampling position corresponding to each edge sampling position relative to a preset edge sampling position is determined based on the magnitude relationship between the sampling data at each edge position and the sampling data at two adjacent center positions, thereby determining the offset direction of each center sampling position relative to a preset center sampling position; the preset sampling position includes a preset edge sampling position and a preset center sampling position, including:

[0083] Set a first reference value and a second reference value, and the initial values ​​of both the first reference value and the second reference value are 0;

[0084] According to the order of the sampled data at each center position and each sampled data at each edge position after the interval arrangement, the first sampled data at the edge position is set as the current sampled data at the edge position;

[0085] Determine the previous and next center position sampling data adjacent to the current edge position sampling data;

[0086] If the current edge position sampling data is the same as the previous center position sampling data, the first reference value is incremented by one; if the current edge position sampling data is the same as the next center position sampling data, the second reference value is incremented by one.

[0087] Set the next edge position sampling data of the current edge position sampling data as the current edge position sampling data, and return to the step of determining the previous center position sampling data and the next center position sampling data adjacent to the current edge position sampling data, until the next center position sampling data of the current edge position sampling data is the last center position sampling data;

[0088] If the first reference value is greater than the second reference value, the parameters of the clock generation module 2 are adjusted to shift the phase of each clock signal output by the clock generation module 2 backward; if the first reference value is less than the second reference value, the parameters of the clock generation module 2 are adjusted to shift the phase of each clock signal output by the clock generation module 2 forward; if the first reference value is equal to the second reference value, the parameters of the clock generation module 2 are kept unchanged so that the phase of each clock signal output by the clock generation module 2 remains unchanged.

[0089] In this embodiment, when determining the offset direction, a first reference value and a second reference value with an initial value of 0 are first set. Each edge position sampling data is compared with its two adjacent center position sampling data to determine whether the actual edge sampling position of the edge position sampling data is closer to the actual center sampling position of the previous center position sampling data or closer to the actual center sampling position of the next center position sampling data. When the edge position sampling data is equal to the previous center position sampling data, the actual edge sampling position of the edge position sampling data is closer to the actual center sampling position of the previous center position sampling data, and the first reference value is incremented by one. When the edge position sampling data is equal to the next center position sampling data, the actual edge sampling position of the edge position sampling data is closer to the actual center sampling position of the next center position sampling data, and the second reference value is incremented by one. Ideally, the edge position sampling data is 0 and the center position sampling data is 1. In reality, the current edge position sampling data is 1, the previous center position sampling data is 1, and the next center position sampling data is 0. Then, the actual edge sampling position of the current edge position sampling data is close to the actual center sampling position of the previous center position sampling data. The first reference value is incremented by one until each edge position sampling data is compared with its two adjacent center position sampling data. After updating the first reference value and / or the second reference value, the final first reference value and second reference value are obtained.

[0090] The final first reference value and the second reference value are compared. If the first reference value is greater than the second reference value, it can be determined that the actual edge sampling position of the edge position sampling data is closer to the actual center sampling position of the previous center position sampling data. That is, the phase of the clock signal is ahead, and the logic unit 3 can adjust the clock signal generated by the clock generation module 2 backward. If the first reference value is less than the second reference value, it can be determined that the actual edge sampling position of the edge position sampling data is closer to the actual center sampling position of the next center position sampling data. That is, the phase of the clock signal is lagging, and the logic unit 3 can adjust the clock signal generated by the clock generation module 2 forward. If the first reference value and the second reference value are equal, it can be determined that the actual center sampling position of the center position sampling data is the preset center sampling position, and there is no need to adjust the clock signal generated by the clock generation module 2.

[0091] In a preferred embodiment, after acquiring the sampling data at each center position and each edge position output by sampling module 1, the method further includes:

[0092] Determine whether the number of center position sampling data and edge position sampling data obtained are both the first preset number. If so, proceed to the step of arranging the center position sampling data and edge position sampling data at intervals according to the order of the clock signals when collecting each center position sampling data and each edge position sampling data.

[0093] Set the clock adjustment value to an initial value of 0, and proceed to the step of setting the first reference value and the second reference value, where the initial values ​​of both the first reference value and the second reference value are 0;

[0094] If the first reference value is greater than the second reference value, the parameters of the clock generation module 2 are adjusted to shift the phase of each clock signal output by the clock generation module 2 backward; if the first reference value is less than the second reference value, the parameters of the clock generation module 2 are adjusted to shift the phase of each clock signal output by the clock generation module 2 forward; if the first reference value is equal to the second reference value, the parameters of the clock generation module 2 are kept unchanged. After ensuring that the phase of each clock signal output by the clock generation module 2 remains unchanged, the following steps are also included:

[0095] Increment the clock adjustment value by 1, and check if the clock adjustment value is the preset clock adjustment value;

[0096] If not, return to the steps of obtaining the sampling data of each center position and each edge position output by sampling module 1;

[0097] If so, the phase of each clock signal generated by clock generation module 2 will be locked, and the clock adjustment value will be cleared to zero.

[0098] In this embodiment, after obtaining a first preset number of center position sampling data and edge position sampling data, the first preset number of center position sampling data and the first preset number of edge position sampling data are reordered according to the sampling clock sequence, and a clock adjustment value with an initial value of 0 is set. After each operation of shifting the phase of the clock signal generated by the clock generation module 2 forward, backward, or keeping it unchanged based on the first reference value and the second reference value, the logic unit 3 increments the clock adjustment value by one until the clock adjustment value is the preset clock adjustment value, so that the phase of the clock signal generated by the clock generation module 2 can be locked. The sampling module 1 can then accurately sample the clock signal based on the phase-locked clock signal.

[0099] If the preset clock adjustment value is 5, then after the logic unit 3 performs the operation of shifting the phase of the clock signal generated by the clock generation module 2 forward, backward, or keeping it unchanged 5 times based on the first reference value and the second reference value, it can lock the phase of the clock signal generated by the clock generation module 2. The clock signal generated by the clock generation module 2 after phase locking enables the sampling module 1 to sample data at the preset sampling positions in each data of the data to be sampled, so as to obtain accurate sampled data.

[0100] It should be noted that after the logic unit 3 acquires the first preset number of center position sampling data and edge position sampling data for the first time, it calculates the first reference value and the second reference value, and performs an operation to shift the phase of the clock signal generated by the clock generation module 2 forward, backward, or remain unchanged. Then, it acquires the first preset number of center position sampling data and edge position sampling data again, calculates the first reference value and the second reference value again with the initial value of 0, and performs an operation to shift the phase of the clock signal generated by the clock generation module 2 forward, backward, or remain unchanged. This process continues until the number of times the operation to shift the phase of the clock signal generated by the clock generation module 2 forward, backward, or remain unchanged is the preset clock adjustment value. That is, the first preset number of center position sampling data and edge position sampling data acquired each time the phase of the clock signal generated by the clock generation module 2 is adjusted is different, and they are all the first preset number of center position sampling data and edge position sampling data acquired again.

[0101] When the clock generation module 2 includes a phase-locked loop and a phase interpolator, the phase encoding of the phase interpolator is changed so that the phase interpolator adjusts the phase of the clock signal output by the phase-locked loop.

[0102] If the first preset quantity is 40, the data frequency of the data to be sampled is 16GHz, the frequency of the clock signal output by the phase-locked loop is 8GHz, and the phases are 0°, 90°, 180° and 270° respectively, the logic unit 3 obtains the sampling module 1 based on the clock signal with 0° and 180° phases to sample each data of the data to be sampled, and obtains 40 parallel center position sampling data Dc. <0> Dc <1> ...Dc <38> Dc <39> Sampling module 1 samples each data point of the data to be sampled based on clock signals with 90° and 270° phases, obtaining 40 parallel edge position sampling data points (De). <0> De <1> ...De <38> De <39> ,like Figure 2 As shown, Figure 2 This application provides a schematic diagram of sampling data based on a four-phase clock signal. The data is sorted at intervals according to the sampling order of the center position and the edge position. The sorted data is Dc. <0> De <0> Dc <1> De <1> ...Dc <38> De <38> Dc <39> De <39> Let the first reference value be Early and the second reference value be Later. Please refer to Table 1. Table 1 is a logical table used to update the first and second reference values ​​by judging the center position sampling data and edge position sampling data provided in this application. <n>This represents the sampled data at the current edge location, Dc <n>Dc represents the previous center position sampling data of the current edge position sampling data.<N+1> This represents the next center position sampling data after the current edge position sampling data. As can be seen from Table 1, when De <n>=1,Dc <n>=1, Dc<N+1> =1, De <n>Both and DC <n>Equal to, and also equal to DC<N+1> When they are equal, both the first reference value (Early) and the second reference value (Later) are incremented by 1; when De... <n>=1,Dc <n>=1, Dc<N+1> =0, De <n>and DC <n>Equal, but with Dc<N+1> If they are not equal, the first reference value Early is incremented by one, but the second reference value Later is incremented by 0, meaning the second reference value Later remains unchanged.

[0103] Table 1

[0104]

[0105] Since the 40th edge position sampling data De<39> only has the previous center position sampling data Dc<39> and no next center position sampling data, therefore, only from the first edge position sampling data De<0> to the 39th edge position sampling data De<38> are used to calculate the first reference value Early and the second reference value Later. That is, when the first edge position sampling data De<0> is set as the current edge position sampling data, it is determined whether the current edge position sampling data is the same as the first center position sampling data Dc<0>, and whether the current edge position sampling data is the same as the second center position sampling data Dc<1>, so as to change the first reference value Early and / or the second reference value Later; then when the second edge position sampling data De<1> is set as the current edge position sampling data, it is determined whether the current edge position sampling data is the same as the second center position sampling data Dc<1>, and whether the current edge position sampling data is the same as the third center position sampling data Dc<2>, so as to change the first reference value Early and / or the second reference value Later; and so on, until the 39th edge position sampling data De<38> is set as the current edge position sampling data, it is determined whether the current edge position sampling data is the same as the 39th center position sampling data Dc<38>, and whether the current edge position sampling data is the same as the 40th center position sampling data Dc<39>, so as to change the first reference value Early and / or the second reference value Later, and the final first reference value Early and second reference value Later are obtained. Subsequently, according to Table 2, it is determined how to adjust the configuration parameters of the phase interpolator. Table 2 is a table provided in this application for changing the phase encoding of the phase interpolator based on the first reference value and the second reference value. If (Early>Later) in Table 2 means that if the first reference value is greater than the second reference value, Phase_code is the phase encoding adjustment instruction of the phase interpolator, Phase_code + 1, corresponding to dir = 3b'010, which means that the phase encoding of the phase interpolator increases, and the phase interpolator adjusts the parameters of the clock generation module 2 so that the phases of the respective clock signals output by the clock generation module 2 are shifted backward; if (Early<Later) means that if the first reference value is less than the second reference value, Phase_code - 1, corresponding to dir = 3b'100, which means that the phase encoding of the phase interpolator decreases, and the phase interpolator adjusts the parameters of the clock generation module 2; if (Early = Later) means that if the first reference value is equal to the second reference value, Phase_code + 0, corresponding to dir = 3b'001, which means that the phase encoding of the phase interpolator remains unchanged, and the parameters of the clock generation module 2 are kept unchanged so that the phases of the respective clock signals output by the clock generation module 2 remain unchanged.

[0106] Table 2

[0107]

[0108] Please refer to Table 3, which shows the phase code and corresponding adjustment phase of a phase interpolator provided in this application. For example, if the initial condition is Phase_code=1, the phase interpolator directly transmits the clock signal output from the phase-locked loop to sampling module 1. If, after one round of calculation, Phase_code+1 is determined, then Phase_code=2, and the corresponding phase code of the phase interpolator is 1111 11100000 00000000 00010000 00000000 000000000000000 000000000 00000000 00000000. The phase interpolator shifts the phase of the clock signal output from the phase-locked loop by 5.625° before transmitting it to sampling module 1.

[0109] Table 3

[0110]

[0111] As a preferred embodiment, the next edge position sampling data of the current edge position sampling data is set as the current edge position sampling data, and the step of determining the previous and next center position sampling data adjacent to the current edge position sampling data is returned. This process continues until the next center position sampling data of the current edge position sampling data becomes the last center position sampling data. The method further includes:

[0112] Determine whether the phase of each clock signal generated by clock generation module 2 is locked;

[0113] If so, when the absolute value of the difference between the first reference value and the second reference value is not less than the preset difference, the phase of each clock signal generated by the clock generation module 2 is unlocked, and the process proceeds to the following steps: if the first reference value is greater than the second reference value, the parameters of the clock generation module 2 are adjusted to shift the phase of each clock signal output by the clock generation module 2 backward; if the first reference value is less than the second reference value, the parameters of the clock generation module 2 are adjusted to shift the phase of each clock signal output by the clock generation module 2 forward; if the first reference value is equal to the second reference value, the parameters of the clock generation module 2 are kept unchanged to adjust the phase of each clock signal output by the clock generation module 2.

[0114] When the absolute value of the difference between the first reference value and the second reference value is less than the preset difference, return to the step of acquiring the sampling data of each center position and each edge position output by the sampling module 1;

[0115] If not, proceed to the step of adjusting the parameters of clock generation module 2 if the first reference value is greater than the second reference value, so that the phase of each clock signal output by clock generation module 2 is shifted backward; adjusting the parameters of clock generation module 2 if the first reference value is less than the second reference value, so that the phase of each clock signal output by clock generation module 2 is shifted forward; and keeping the parameters of clock generation module 2 unchanged so that the phase of each clock signal output by clock generation module 2 remains unchanged if the first reference value is equal to the second reference value.

[0116] In this embodiment, after calculating the final first reference value and second reference value based on the first preset number of center position sampling data and edge position sampling data, the phase of the clock signal generated by the clock generation module 2 is not directly adjusted based on the first reference value and second reference value. Instead, it is first determined whether the phase of the clock signal generated by the clock generation module 2 is locked under the current situation. If it is not locked, then it is still in the phase adjustment stage of the clock signal generated by the clock generation module 2. The phase of the clock signal generated by the clock generation module 2 can be shifted forward, shifted backward, or left unchanged based on the relationship between the first reference value and the second reference value. However, if the phase of the clock signal generated by the clock generation module 2 is locked under the current situation, then the absolute value of the difference between the first reference value and the second reference value needs to be calculated first. If the absolute value is not greater than the preset difference, then the actual sampling position of the sampling data obtained by the sampling module 1 based on the phase of the clock signal generated by the clock generation module 2 does not have a large offset from the preset sampling position, and the sampling module 1 can continue to sample based on the phase of the clock signal generated by the clock generation module 2 after phase locking. However, if the absolute value is greater than the preset difference, then the phase of the clock signal generated by the clock generation module 2 is locked. If the sampling module 1 obtains a large offset between the actual sampling position and the preset sampling position of the sampling data obtained by sampling based on the phase of the clock signal generated by the clock generation module 2, the sampling data obtained by sampling based on the phase of the clock signal generated by the locked clock generation module 2 will be abnormal. Sampling module 1 cannot continue to sample based on the phase of the clock signal generated by the phase-locked clock generation module 2. Instead, it must unlock the phase of the clock signal generated by the phase-locked clock generation module 2 and adjust the phase of the clock signal generated by the clock generation module 2 based on the relationship between the first reference value and the second reference value. After the clock phase adjustment is performed a preset number of times, the phase of the clock signal generated by the clock generation module 2 is locked again. The module continues to acquire a first preset number of center position sampling data and edge position sampling data. Each time the first preset number of center position sampling data and edge position sampling data are acquired, the absolute value of the difference between the first reference value and the second reference value is compared with the preset difference to adjust the phase of the clock signal generated by the clock generation module 2 in a timely manner.

[0117] It should be noted that the preset clock adjustment value is not fixed and can be adjusted according to the actual situation. For example, if the letter M represents the preset clock adjustment value, then M can be set to 1 / 2*N, or M=3 / 4*N, or M=N, where N is the first preset quantity, such as the number of bits of the parallel data output by the serial-to-parallel conversion module in sampling module 1.

[0118] Please refer to Figure 3 and Figure 4 , Figure 3 This application provides a simulation diagram. Figure 4 Another simulation diagram provided for this application. Figure 3 The first three rows of waveforms represent the differences between the first and second reference values ​​at the first, second, and third margins, respectively. The fourth to sixth rows of waveforms show that at the first, second, and third margins, a high level indicates locking the clock signal phase, and a low level indicates unlocking the clock signal phase. It can be seen that the clock signal phase corresponding to the first margin can be locked and unlocked normally, but the clock signal phases corresponding to the second and third margins can only be locked but not unlocked. Therefore, when selecting the margin, it should be considered whether it can guarantee that the clock signal phase can be locked normally. The clock signal is set and unlocked to ensure correct data sampling. The waveforms in rows 7 to 9 represent the clock signals at the first, second, and third margins, respectively. 1 indicates that the first and second reference values ​​are equal, and the phase of the clock signal remains unchanged. 2 indicates that the first reference value is greater than the second reference value, meaning the phase of the clock signal is ahead, and the phase of the clock signal needs to be shifted backward. 4 indicates that the first reference value is less than the second reference value, meaning the phase of the clock signal is lagging, and the phase of the clock signal needs to be shifted forward. This corresponds to the change in the phase encoding of the phase interpolator, so that the phase interpolator can adjust the phase of the clock signal generated by the phase-locked loop accordingly. Figure 4 The clock signal phase is locked after the comparison between the first reference value and the second reference value is performed five times. After locking, the difference between the first reference value and the second reference value remains unchanged until the absolute value of the difference between the first reference value and the second reference value is not less than the preset difference, at which point the clock signal phase is unlocked.

[0119] It should also be noted that when the selected margin is the maximum margin, although the phase of the clock signal generated by the clock generation module 2 cannot be properly unlocked, the phase interpolator can dynamically adjust the phase of the clock signal generated by the clock generation module 2, so that the phase of the clock signal generated by the clock generation module 2 changes with the preset sampling position of the data to be sampled.

[0120] As a preferred embodiment, before determining the offset direction of the actual sampling position of each data point in the data to be sampled relative to the preset sampling position, the method further includes:

[0121] Determine whether the frequency of the data to be sampled is less than the frequency of the clock signal generated by clock generation module 2;

[0122] If not, proceed to the step of determining the offset direction of the actual sampling position of each data in the data to be sampled relative to the preset sampling position;

[0123] If so, then the sampling data output by sampling module 1 is obtained, and after the number of obtained sampling data is the second preset number, the sampling data is arranged according to the order of the clock signals when the sampling data is collected.

[0124] Each sampled data is divided into several data groups, and the amount of data in each data group is the first preset number. If the second preset number is not an integer ratio to the first preset number, the sampled data is reused.

[0125] Determine the number of target data points for each sampled data point in each data group;

[0126] Set the data group with the most data groups as the target data group;

[0127] Determine the sampling clock of each sampled data in the target data group as the target sampling clock;

[0128] Each target sampling clock is set to the clock at the preset sampling position of each data point to be sampled.

[0129] If the frequency of the data to be sampled is less than the frequency of the clock signal generated by the clock generation module 2, the existing technology usually adjusts the frequency of the clock signal generated by the clock generation module 2 to match the frequency of the data to be sampled. However, this adjustment method is relatively complex and costly.

[0130] In this embodiment, if the frequency of the data to be sampled is less than the frequency of the clock signal generated by the clock generation module 2, there is no need to adjust the frequency of the clock signal generated by the clock generation module 2. The sampling module 1 directly samples the data to be sampled according to the clock signal generated by the clock generation module 2. Although it is not possible to determine at this time whether the sampled data is the accurate data obtained by sampling at the preset sampling position of each data in the data to be sampled, the number of sampled data can be obtained as a second preset number. The sampled data is arranged according to the order of the clock signal when the sampled data is collected, and the sampled data is divided into several data groups. The amount of sampled data in each data group is a first preset number. The number of sampled data that are target data in each data group is determined, and the data group with the most sampled data that are target data is set as the target data group. The sampling clock when sampling each sampled data in the target data group is set as the target sampling clock. The sampled data obtained by the sampling module 1 based on the target sampling clock is the accurate sampled data, that is, the accurate sampled data obtained by sampling at the preset sampling position of each data in the data to be sampled.

[0131] For example, if the first preset quantity is 40 and the second preset quantity is 256, the sampling module 1 obtains a sampled data of 1 when sampling at the preset sampling positions and a sampled data of 0 when sampling at non-preset sampling positions. Since 256 is not an integer multiple of 40, direct grouping cannot guarantee that each data group contains 40 data points. In this case, some sampled data can be reused, such as reusing the 6th, 29th, 32nd, 38th, and 24 other data points in sequence. Finally, the 280 data points are divided into 7 data groups, each containing 40 sampled data points. The data group with the most sampled data points of 1 is determined, for example, the first data group has 10 sampled data points of 1, the second data group has 15, and so on. The third data group has 38 samples with a value of 1, the fourth data group has 20 samples with a value of 1, the fifth data group has 30 samples with a value of 1, the sixth data group has 33 samples with a value of 1, and the seventh data group has 25 samples with a value of 1. Therefore, the third data group can be determined as the target data group, and the sampling clock corresponding to each sampled data in the third data group is set as the target sampling clock. Sampling module 1 still samples based on the clock signal generated by clock generation module 2, but logic unit 3 can select the sampled data corresponding to the target sampling clock from the sampled data output by sampling module 1 as the preset sampling position for each data to be sampled, thus obtaining accurate data. Please refer to Table 4, which is a table provided in this application for dividing each sampled data into several data groups. The table shows A... <0> To A <256> The sorted sampled data are represented by B{6.4N}, B{6.4N+1}, B{6.4N+2}, B{6.4N+3}, B{6.4N+4}, B{6.4N+5}, B{6.4N+6}, and B{6.4N+7}, which are the sampled data sets of each data group. 6.4 is the result of 256 divided by 40 and rounded. Therefore, some sampled data is reused in the table. If the sampling clock corresponding to each sampled data in the third data group is set as the target sampling clock, then the column of sampled data corresponding to the third group in Table 4 is the sampled data in the target data group, and the sampling clock corresponding to this column of sampled data is the target sampling clock.

[0132] Table 4

[0133]

[0134] Furthermore, considering that when the frequency of the data to be sampled is less than the frequency of the clock signal, the sampling module 1 will sample the same data multiple times. In order to improve the accuracy of the final target clock signal, after arranging the sampled data according to the order of the clock signal when collecting each sampled data, the sampled data can be traversed. The middle sampled data in the sampled data that is consecutively 1 or 0 and has an odd number of consecutive occurrences is marked as 1, and the remaining sampled data is marked as 0. The middle two sampled data in the sampled data that is consecutively 1 or 0 and has an even number of consecutive occurrences is marked as 1. Taking the first 10 data in 256 data as an example, if the first 10 sampled data are 1111000111, then after the above processing, the first 10 data become 011010010.

[0135] To address the aforementioned technical problems, this application also provides a clock data recovery system applied to a logic unit 3. The logic unit 3 is connected to a sampling module 1 and a clock generation module 2. The clock generation module 2 is used to generate a clock signal. The sampling module 1 is used to sample each data in the data to be sampled based on the clock signal to obtain each sampled data. The system includes:

[0136] The first determining unit is used to determine the offset direction of the actual sampling position of each data in the data to be sampled relative to the preset sampling position.

[0137] The phase adjustment unit is used to adjust the phase of the clock signal generated by the clock generation module 2 based on the offset direction, until the sampling position of the sampling module 1 when sampling each data in the data to be sampled based on the clock signal after the clock phase adjustment is the preset sampling position.

[0138] Please refer to Figure 5 , Figure 5 A schematic diagram of a clock data recovery device provided in this application includes a sampling module 11, a clock generation module 22, and a logic unit 33;

[0139] The logic unit 33 is connected to the sampling module 1 and the clock generation module 2, and is used to perform the steps of the clock data recovery method described above;

[0140] Clock generation module 2 is used to generate clock signals;

[0141] Sampling module 1 is used to sample each data in the data to be sampled based on the clock signal to obtain each sampled data.

[0142] For a description of the clock data recovery device provided by the present invention, please refer to the above method embodiments; the present invention will not be described again here.

[0143] In a preferred embodiment, the clock signal generation module includes a phase-locked loop (PLL) and a phase interpolator. The PLL is used to output a clock signal, and the phase interpolator is used to adjust the phase of the clock signal output by the PLL and transmit it to the sampling module 1 based on the control of the logic unit 3.

[0144] In this embodiment, the clock signal generation module includes a phase-locked loop (PLL) and a phase interpolator. The PLL can output multi-phase clock signals to the phase interpolator. Based on the control of the logic unit 3, the phase interpolator shifts the phase of the clock signal output by the PLL forward, backward, or keeps it unchanged before transmitting it to the sampling module 1, so as to ensure the accuracy of the data sampled by the sampling module 1.

[0145] Please refer to Figure 6 , Figure 6 This is a schematic diagram of a specific structure of a clock data recovery device provided in this application. The sampling module 1 may include multiple samplers and a serial-to-parallel conversion module. The samplers sample the data to be sampled based on the clock signal generated by the clock generation module 2, converting the analog data to be sampled into a digital signal and outputting it. If the clock signal output by the phase-locked loop is a four-phase clock signal with phases of 0°, 90°, 180°, and 270°, and a clock signal with a frequency of 8 GHz, then the sampling module 1 includes four samplers and two serial-to-parallel conversion modules. The first sampler samples each data point in the data to be sampled based on the 0° phase clock signal, and the second sampler samples based on the 90° phase clock signal. The first sampler samples each data point in the sampled data based on a clock signal with a 180° phase, the second sampler samples each data point in the sampled data based on a clock signal with a 270° phase, the third sampler samples each data point in the sampled data based on a clock signal with a 180° phase, and the fourth sampler samples each data point in the sampled data based on a clock signal with a 270° phase. The first and third samplers are connected to the first serial-to-parallel conversion module, and the second and fourth samplers are connected to the second serial-to-parallel conversion module. The first serial-to-parallel conversion module converts the data sampled by the first and third samplers into parallel sampled data, and the second serial-to-parallel conversion module converts the data sampled by the second and fourth samplers into parallel sampled data.

[0146] If the data frequency of the data to be sampled is 16GHz, then the digital logic unit 3 in logic unit 3 adjusts the parameters of the phase interpolator by determining the offset direction of the edge position sampling data and the center position sampling data, so that the phase interpolator adjusts the phase of the four-phase clock signal and transmits it to the sampling module 1. This continues until the first and third samplers sample the preset center sampling position of each data in the data to be sampled, and the second and fourth samplers sample the preset edge sampling position of each data in the data to be sampled. The serial-to-parallel conversion module connected to the first and third samplers directly transmits the sampled data to the data selector for output.

[0147] If the frequency of the data to be sampled is 8GHz, then a 1 / 2 divider needs to be connected between the phase interpolator and the phase-locked loop. The 1 / 2 divider divides the 8GHz clock signal output by the phase-locked loop and transmits it to the phase interpolator. The digital logic unit 3 of logic unit 3 adjusts the parameters of the phase interpolator by determining the offset direction of the edge position sampling data and the center position sampling data. The phase interpolator then adjusts the phase of the four-phase clock signal after frequency division and transmits it to the sampling module 1. This process continues until the first and third samplers sample the preset center sampling position of each data in the data to be sampled, and the second and fourth samplers sample the preset edge sampling position of each data in the data to be sampled. The serial-to-parallel conversion module connected to the first and third samplers directly transmits the sampled data to the data selector for output.

[0148] If the frequency of the data to be sampled is 5GHz, it is not possible to directly divide the clock signal output by the phase-locked loop (PLL) using a frequency divider to sample the data at preset center and edge sampling positions. In this case, there is no need to divide or adjust the phase of the clock signal output by the PLL. The phase interpolator directly transmits the clock signal output by the PLL to each sampler. Each sampler samples the data to be sampled based on the clock signal of the corresponding phase. Each sampler transmits the sampled data to the oversampling module 1 of the logic unit 3. The oversampling module 1 groups the sampled data and determines the target sampling clock so that the data selector can determine the data corresponding to the target sampling clock from the sampled data output by the sampler. This data is the accurate data obtained by sampling from the preset sampling positions of each data in the data to be sampled.

[0149] If the frequency of the data to be sampled is 2.5GHz, then the clock signal needs to be divided by a 1 / 2 divider before being transmitted to the phase interpolator. The phase interpolator transmits the divided clock signal to each sampler. Each sampler samples the data to be sampled based on the clock signal of the corresponding phase. Each sampler transmits the sampled data to the oversampling module 1 of logic unit 3. The oversampling module 1 groups the sampled data and determines the target sampling clock so that the data selector can determine the data corresponding to the target sampling clock from the sampled data output by the sampler. This data is the accurate data obtained by sampling from the preset sampling positions of each data in the data to be sampled.

[0150] Therefore, regardless of the data frequency of the data to be sampled, this application can determine the accurate data obtained by the sampling module 1 sampling at the preset sampling position, ensuring the accuracy of data sampling and transmission over a wider range of data frequencies.

[0151] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0152] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A clock data recovery method, characterized by, It is applied to a logic unit, which is connected to a sampling module and a clock generation module, and the clock generation module is used to generate a clock signal; The sampling module is used to sample each data in the data to be sampled based on the clock signal to obtain each sampled data. The method includes: Determine the offset direction of the actual sampling position of each data in the data to be sampled relative to the preset sampling position; The phase of the clock signal generated by the clock generation module is adjusted based on the offset direction until the sampling module samples each data in the data to be sampled based on the clock signal with the adjusted clock phase, and the sampling position when obtaining each sampled data is the preset sampling position.

2. The clock data recovery method of claim 1, wherein, The clock signal generation module includes a phase-locked loop (PLL) and a phase interpolator. The PLL is used to generate a clock signal, and the phase interpolator is used to adjust the phase of the clock signal output by the PLL and transmit it to the sampling module based on the control of the logic unit. The phase of the clock signal generated by the clock generation module is adjusted based on the offset direction until the sampling module samples each data point in the data to be sampled based on the clock signal with the adjusted clock phase. The sampling position at which each sampled data point is obtained is the preset sampling position, including: The configuration parameters of the phase interpolator are adjusted based on the offset direction so that the phase interpolator transmits the phase of the clock signal output by the phase-locked loop to the sampling module after adjusting the phase of the clock signal. The sampling position when the sampling module samples each data in the data to be sampled based on the clock signal after the clock phase is adjusted by the phase interpolator is the preset sampling position.

3. The clock data recovery method of claim 1, wherein, The clock generation module is specifically used to generate clock signals with four phases, including a first-phase clock signal, a second-phase clock signal, a third-phase clock signal, and a fourth-phase clock signal in phase order. The sampling module is specifically used to sample each data in the data to be sampled based on each of the clock signals, and output the sampled data obtained based on the first-phase clock signal and the third-phase clock signal as the center position sampled data of each data in the data to be sampled, and output the sampled data obtained based on the second-phase clock signal and the fourth-phase clock signal as the edge position sampled data of each data in the data to be sampled. The sampled data includes the center position sampled data and the edge position sampled data. Determining the offset direction of the actual sampling position of each data point in the data to be sampled relative to a preset sampling position includes: Acquire the sampling data at each center position and each edge position output by the sampling module; The sampled data at each center position and each sampled data at each edge position are arranged at intervals according to the order of the clock signals when the sampled data at each center position and each sampled data at each edge position are collected; Based on the size relationship between the sampling data at each edge position and the sampling data at two adjacent center positions, the offset direction of the actual edge sampling position corresponding to each edge sampling data relative to the preset edge sampling position is determined, so as to determine the offset direction of each center sampling data relative to the preset center sampling position; the preset sampling position includes the preset edge sampling position and the preset center sampling position.

4. The clock data recovery method of claim 3, wherein, Based on the size relationship between the sampling data at each edge position and the sampling data at two adjacent center positions, the offset direction of the actual edge sampling position corresponding to each edge sampling data relative to the preset edge sampling position is determined, so as to determine the offset direction of each center sampling data relative to the preset center sampling position. The preset sampling positions include the preset edge sampling positions and the preset center sampling positions, including: Set a first reference value and a second reference value, and the initial values ​​of the first reference value and the second reference value are both 0; According to the order of the sampled data at each center position and the sampled data at each edge position after being arranged at intervals, the first sampled data at the edge position is set as the current sampled data at the edge position. Determine the previous and next center position sampling data adjacent to the current edge position sampling data; If the current edge position sampling data is the same as the previous center position sampling data, the first reference value is incremented by one; if the current edge position sampling data is the same as the next center position sampling data, the second reference value is incremented by one. The next edge position sampling data of the current edge position sampling data is set as the current edge position sampling data, and the step of determining the previous and next center position sampling data adjacent to the current edge position sampling data is returned until the next center position sampling data of the current edge position sampling data is the last center position sampling data. If the first reference value is greater than the second reference value, the parameters of the clock generation module are adjusted to shift the phase of each clock signal output by the clock generation module backward; if the first reference value is less than the second reference value, the parameters of the clock generation module are adjusted to shift the phase of each clock signal output by the clock generation module forward; if the first reference value is equal to the second reference value, the parameters of the clock generation module are kept unchanged to keep the phase of each clock signal output by the clock generation module unchanged.

5. The clock data recovery method of claim 4, wherein, After obtaining the sampling data at each center position and each edge position output by the sampling module, the method further includes: Determine whether the number of the obtained center position sampling data and edge position sampling data are both the first preset number. If so, proceed to the step of arranging the center position sampling data and edge position sampling data at intervals according to the order of the clock signals when collecting each center position sampling data and each edge position sampling data. Set the clock adjustment value to an initial value of 0, and proceed to the step of setting the first reference value and the second reference value, where the initial values ​​of the first reference value and the second reference value are both 0; If the first reference value is greater than the second reference value, the parameters of the clock generation module are adjusted to shift the phase of each clock signal output by the clock generation module backward; if the first reference value is less than the second reference value, the parameters of the clock generation module are adjusted to shift the phase of each clock signal output by the clock generation module forward; if the first reference value is equal to the second reference value, the parameters of the clock generation module are kept unchanged. After ensuring that the phase of each clock signal output by the clock generation module remains unchanged, the process further includes: Increment the value of the clock adjustment value by 1, and determine whether the clock adjustment value is the preset clock adjustment value; If not, return to the step of obtaining the sampling data of each center position and each edge position output by the sampling module; If so, the phase of each clock signal generated by the clock generation module is locked, and the clock adjustment value is cleared to zero.

6. The clock data recovery method of claim 5, wherein, The process of setting the next edge position sampling data of the current edge position sampling data as the current edge position sampling data, and returning to the step of determining the previous and next center position sampling data adjacent to the current edge position sampling data, continues until the next center position sampling data of the current edge position sampling data becomes the last center position sampling data, and further includes: Determine whether the phase of each clock signal generated by the clock generation module is locked; If so, when the absolute value of the difference between the first reference value and the second reference value is not less than a preset difference, the phase of each clock signal generated by the clock generation module is unlocked, and the process proceeds to the following steps: if the first reference value is greater than the second reference value, the parameters of the clock generation module are adjusted to shift the phase of each clock signal output by the clock generation module backward; if the first reference value is less than the second reference value, the parameters of the clock generation module are adjusted to shift the phase of each clock signal output by the clock generation module forward; if the first reference value is equal to the second reference value, the parameters of the clock generation module are kept unchanged to adjust the phase of each clock signal output by the clock generation module. When the absolute value of the difference between the first reference value and the second reference value is less than the preset difference, the process returns to the step of obtaining the sampling data of each center position and each edge position output by the sampling module. If not, proceed to the step of: if the first reference value is greater than the second reference value, adjust the parameters of the clock generation module to shift the phase of each clock signal output by the clock generation module backward; if the first reference value is less than the second reference value, adjust the parameters of the clock generation module to shift the phase of each clock signal output by the clock generation module forward; if the first reference value is equal to the second reference value, keep the parameters of the clock generation module unchanged so that the phase of each clock signal output by the clock generation module remains unchanged.

7. The clock data recovery method according to any one of claims 1-6, characterized in that, Before determining the offset direction of the actual sampling position of each data point in the data to be sampled relative to the preset sampling position, the method further includes: Determine whether the frequency of the data to be sampled is less than the frequency of the clock signal generated by the clock generation module; If not, proceed to the step of determining the offset direction of the actual sampling position of each data in the data to be sampled relative to the preset sampling position; If so, then each of the sampled data output by the sampling module is acquired, and after the number of acquired sampled data is a second preset number, the sampled data is arranged according to the order of the clock signals when each of the sampled data is acquired; Each of the sampled data is divided into several data groups, and the amount of data in each data group is a first preset number. If the second preset number is not an integer ratio to the first preset number, the sampled data is reused. Determine the number of target data points in each of the data groups; The data group with the largest number of each of the aforementioned data groups is set as the target data group; The sampling clock of each sampled data in the target data group is determined as the target sampling clock; Each of the target sampling clocks is set as a clock for sampling at a preset sampling position of each data point of the data to be sampled.

8. A clock data recovery system, characterized in that, It is applied to a logic unit, which is connected to a sampling module and a clock generation module, and the clock generation module is used to generate a clock signal; The sampling module is used to sample each data in the data to be sampled based on the clock signal to obtain each sampled data. The system includes: The first determining unit is used to determine the offset direction of the actual sampling position of each data in the data to be sampled relative to the preset sampling position. A phase adjustment unit is used to adjust the phase of the clock signal generated by the clock generation module based on the offset direction, until the sampling position when the sampling module samples each data in the data to be sampled based on the clock signal after the clock phase adjustment is the preset sampling position.

9. A clock data recovery device, characterized in that, It includes a sampling module, a clock generation module, and logic units; The logic unit is connected to the sampling module and the clock generation module, and is used to perform the steps of the clock data recovery method as described in any one of claims 1-7; The clock generation module is used to generate clock signals; The sampling module is used to sample each data in the data to be sampled based on the clock signal to obtain each sampled data.

10. The clock data recovery device as described in claim 9, characterized in that, The clock signal generation module includes a phase-locked loop (PLL) and a phase interpolator. The PLL is used to output a clock signal, and the phase interpolator is used to adjust the phase of the clock signal output by the PLL and transmit it to the sampling module based on the control of the logic unit.

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