A zero-delay buffer device and method having a programmable capacitance array
By combining a programmable capacitor array and a phase-locked loop module, the clock delay is dynamically adjusted, solving the zero-delay synchronization problem in the clock buffer device and achieving clock signal consistency under different environments and loads.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 58TH RES INST OF CETC
- Filing Date
- 2026-02-11
- Publication Date
- 2026-06-09
AI Technical Summary
Existing clock buffer devices suffer from inherent phase differences between the input and output clocks when faced with factors such as process deviations of different equipment, changes in ambient temperature, and electromagnetic interference, making it difficult to achieve a synchronous clock signal with zero delay.
By employing a programmable capacitor array and a phase-locked loop (PLL) module, and combining a PLL system consisting of a frequency and phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator, with the coarse and fine adjustment capacitors of the programmable capacitor module, the clock delay is dynamically adjusted to achieve zero-delay buffering.
Without changing the hardware, it effectively compensates for signal interference under different application environments and load conditions, ensuring that the output clock is in phase with the input clock and achieving zero latency.
Smart Images
Figure CN122178905A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communication technology, and in particular to a zero-delay buffer device and method with a programmable capacitor array. Background Technology
[0002] With the development of datafication, information systems have increasingly higher requirements for the quality of their input clocks. Typically, crystal oscillators provide reference clocks for various devices within a system. However, due to the uncertainty of crystal oscillation, even if these clocks oscillate at the same frequency, there will be phase differences between the output clock signals; this is called asynchronous clocking. In practical applications, engineers aim to minimize clock uncertainty and employ clock signals with "zero latency" characteristics. This can improve the overall system's synchronization and determinism, and enhance the predictability of different devices within the system.
[0003] In system design, clock buffers are typically used to fan out the clock signal, resulting in a synchronized clock signal with nearly identical frequency and phase. However, due to the working principle of this buffer structure, an inherent phase difference exists between the input and output clock signals. Furthermore, differences in the operation of different devices, such as ambient temperature, circuit manufacturing variations, and power supply voltage differences, can cause deviations in the clock signal input to the device. Moreover, environmental factors such as electromagnetic interference and signal crosstalk can also cause delays in the input clock.
[0004] To address the aforementioned issues, there is an urgent need for a zero-latency buffering device and method that can adapt to different operating conditions without altering the hardware configuration. Summary of the Invention
[0005] The purpose of this invention is to provide a zero-delay buffer device and method with a programmable capacitor array to solve the problems in the prior art.
[0006] To address the aforementioned technical problems, this invention provides a zero-delay buffer device with a programmable capacitor array, comprising: a programmable capacitor module and a phase-locked loop (PLL) module; the PLL module includes a frequency and phase detector, a charge pump, a loop filter, a first frequency divider, and a second frequency divider. The frequency and phase detector is used to determine the relationship between the input clock and the feedback clock; the charge pump receives the control signal generated by the frequency and phase detector and generates a control voltage signal through the charging and discharging principle; the loop filter performs voltage regulation and filtering on the control voltage signal of the charge pump; the voltage-controlled oscillator generates a certain oscillation frequency by passing the regulated and filtered control voltage signal through the voltage control unit; the first frequency divider divides the output frequency of the voltage-controlled oscillator to generate an output clock for output; the second frequency divider divides the output frequency of the voltage-controlled oscillator to generate a feedback clock, which is input to the frequency and phase detector for comparison of frequency and phase with the input clock.
[0007] The programmable capacitor module includes a primary switch and a secondary switch. The primary switch is used to select whether to connect a coarse adjustment capacitor to the node. If the primary switch is closed, the coarse adjustment capacitor is connected; if the primary switch is open, the coarse adjustment capacitor is not connected. The secondary switch is used to select whether to connect a fine adjustment capacitor to the node. If the secondary switch is closed, the fine adjustment capacitor is connected; if the secondary switch is open, the fine adjustment capacitor is not connected.
[0008] In one embodiment, the coarse adjustment capacitor is a capacitor with a large capacitance value, used to adjust the delay relationship between the output clock and the input clock by a larger margin; the fine adjustment capacitor is a capacitor with a small capacitance value, used to adjust the delay relationship between the output clock and the input clock by a smaller margin; where "larger" and "smaller" are relative to each other.
[0009] In one implementation, the division factor of the first frequency divider and the division factor of the second frequency divider are equal.
[0010] In one embodiment, the frequency of the input clock, the frequency of the output clock, and the frequency of the feedback clock are equal.
[0011] In one implementation, determining the relationship between the input clock and the feedback clock includes whether their frequencies are equal and whether their phases are leading or lagging.
[0012] A method for a zero-delay buffer device with a programmable capacitor array, comprising the following steps: Step 1: The circuit is initially powered on and the input clock is stable and valid. Half of the programmable capacitor module's first-stage switches are open and the remaining first-stage switches are closed; half of the second-stage switches are open and the remaining second-stage switches are closed. Step 2: The frequency and phase detector compares the frequency and phase relationship of the input clock and the feedback clock; if the feedback clock frequency is lower than the input clock frequency, or the feedback clock phase lags behind the input clock phase, it outputs a charge pump charging command; if the feedback clock frequency is higher than the input clock frequency, or the feedback clock phase leads the input clock phase, it outputs a charge pump discharging command. Step 3: After receiving a charging command, the charge pump closes the charging switch and opens the discharging switch to charge the control node and increase the output control voltage signal; after receiving a discharging command, the charging switch opens and the discharging switch closes to discharge the control node and decrease the output control voltage signal. Step 4: The loop filter performs voltage regulation and filtering on the control voltage signal of the charge pump control node; Step 5: The voltage-controlled oscillator receives the regulated and filtered control voltage signal and controls it to generate the oscillation frequency. Within the designed operating range, the higher the control voltage signal, the higher the oscillation frequency of the voltage-controlled oscillator; the lower the control node voltage, the lower the oscillation frequency of the voltage-controlled oscillator. Step 6: The first frequency divider receives the clock signal output from the voltage-controlled oscillator, divides it according to the design value, and outputs the clock signal. Step 7: The second frequency divider receives the clock signal output from the voltage-controlled oscillator, divides it according to the design value, and outputs a feedback clock; Step 8: The feedback clock is connected to an external programmable capacitor module and input to the frequency and phase detector; Step 9: If the frequency and phase detector detects that the frequency and phase relationship of the feedback clock and the input signal are relatively consistent and stable, the output LOCK signal is high, indicating that the output clock signal is valid, and proceed to the next step to adjust the delay of the output signal and the input signal; otherwise, the output LOCK signal is low, indicating that the output clock signal is invalid, and continue to repeat steps 2 to 9. Step 10: Compare the phase relationship between the input clock and the output clock, and record it in the register; Step 11: If the current output clock phase lags behind the input clock phase, the value of the programmable capacitor connected to the feedback clock node needs to be increased; if the current output clock signal phase leads the input clock phase, the value of the programmable capacitor connected to the feedback clock node needs to be decreased. Step 12: If the output clock phase is not equal to the input clock phase, repeat steps 10 to 12; if the output clock phase is equal to the input clock phase, end.
[0013] In one embodiment, the programmable capacitor module corrects and compensates for signal interference caused by different application environments and load conditions by adjusting the capacitance value, including the following steps: Step 21: Compare the output clock delay with the input clock delay; Step 22: If the output clock lags behind the input clock, and all secondary switches are closed and not all fine adjustment capacitors are connected, then the number of closed secondary switches increases by 1, the number of connected fine adjustment capacitors increases by 1, and the process returns to step 21. Step 23: If the output clock lags behind the input clock, and all secondary switches are closed and all fine adjustment capacitors are connected, further determine the status of the primary switches; if not all primary switches are closed and not all coarse adjustment capacitors are connected, then increase the number of primary switches closed by 1, increase the number of coarse adjustment capacitors connected by 1, open all secondary switches, disconnect all fine adjustment capacitors, and return to step 21; if all primary switches are closed and all coarse adjustment capacitors are connected, then the adjustable range is exceeded, and the process ends. Step 24: If the delay between the output clock and the input clock is 0, then the delay adjustment is complete; If the output clock leads the input clock, and all secondary switches are open at this time, and not all fine adjustment capacitors are disconnected, then the number of open secondary switches increases by 1, the number of connected fine adjustment capacitors decreases by 1, and the process returns to step 21. Step 25: If the output clock leads the input clock, and all secondary switches are open and all fine adjustment capacitors are disconnected, further determine the status of the primary switches; if not all primary switches are open and not all coarse adjustment capacitors are disconnected, then increase the number of primary switches open by 1, decrease the number of coarse adjustment capacitors connected by 1, close all secondary switches, connect all fine adjustment capacitors, and return to step 21; if all primary switches are open and all coarse adjustment capacitors are disconnected, then the adjustable range is exceeded, and the process ends.
[0014] In one embodiment, the output clock signal phase is consistent with the input clock phase, and has the characteristic of zero delay.
[0015] This invention provides a zero-delay buffer device and method with a programmable capacitor array. Without changing the hardware, the programmable capacitor module corrects and compensates for signal interference caused by different application environments and load conditions. In addition, the output clock phase of this invention is consistent with the input clock phase, and has the characteristic of zero delay. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of a zero-delay buffer device with a programmable capacitor array according to the present invention; Figure 2 This is a schematic diagram of the programmable capacitor module of the present invention; Figure 3 This is a schematic diagram illustrating the effect of the capacitance value of the programmable capacitor module of the present invention on the delay of the output clock signal and the input clock signal; Figure 4 This is a schematic flowchart of a zero-delay buffering method with a programmable capacitor array according to the present invention. Figure 5 This is a schematic diagram of the process for adjusting the capacitance value of a programmable capacitor connected to the feedback clock node according to the present invention. Detailed Implementation
[0017] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed account of the zero-delay buffer device and method with a programmable capacitor array proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0018] This invention provides a zero-delay buffer device with a programmable capacitor array, the structure of which is as follows: Figure 1As shown, it includes a programmable capacitor module and a phase-locked loop (PLL) module. The PLL module includes a frequency and phase detector, a charge pump, a loop filter, a frequency divider 1, and a frequency divider 2.
[0019] The frequency and phase detector is used to determine the relationship between the input clock and the feedback clock, including whether the frequencies are equal and whether the phases are leading or lagging. The charge pump receives the control signal generated by the frequency and phase detector and generates a control voltage signal through the charging and discharging principle. The loop filter performs voltage regulation and filtering on the control voltage signal of the charge pump to improve system stability. The voltage-controlled oscillator generates a certain oscillation frequency by passing the regulated and filtered control voltage signal through the voltage control unit. Frequency divider 1 divides the output frequency of the voltage-controlled oscillator to generate an output clock for output. Frequency divider 2 divides the output frequency of the voltage-controlled oscillator to generate a feedback clock, which is input to the frequency and phase detector for comparison of frequency and phase with the input clock.
[0020] like Figure 2 As shown, the programmable capacitor module includes a primary switch for selecting whether to connect a coarse adjustment capacitor to the node. If the primary switch is closed, the coarse adjustment capacitor is connected; if the primary switch is open, the coarse adjustment capacitor is not connected. The coarse adjustment capacitor is a capacitor with a large capacitance value, used to adjust the delay relationship between the output clock and the input clock by a larger margin. A secondary switch is used for selecting whether to connect a fine adjustment capacitor to the node. If the secondary switch is closed, the fine adjustment capacitor is connected; if the secondary switch is open, the fine adjustment capacitor is not connected. The fine adjustment capacitor is a capacitor with a small capacitance value, used to adjust the delay relationship between the output clock and the input clock by a smaller margin.
[0021] like Figure 3 The diagram illustrates the effect of the programmable capacitor module's capacitance value on the delay between the output and input clock signals. When the phase-locked loop (PLL) module has reached a stable state, the input, output, and feedback clocks have the same frequency and a fixed phase difference. If the rising edge of the input clock arrives at time T1, the rising edge of the output clock arrives at time T2, and the rising edge of the feedback clock arrives at time T3, the inherent delays of the frequency and phase detectors, output drivers, etc., mean that the delay between the output and input clocks (T2-T1) is a function of the delay between the feedback and input clocks (T3-T1), i.e., T2-T1 = f(T3-T1). By changing the capacitance value of the programmable capacitor module, the rate of change of the feedback clock can be altered, approximately equivalent to changing the arrival time of the feedback clock. In this case, the rising edge of the feedback clock arrives at T3' = T3 + ΔT. By selecting a suitable programmable capacitor so that f(T3 + ΔT - T1) = T2 - T1 = 0, compensation and correction of the delay between the output and input clock signals can be achieved.
[0022] The present invention also provides a method for applying the above-mentioned zero-latency buffer device, such as... Figure 4 As shown, it includes the following steps: Step 401: The circuit is initially powered on and the input clock is stable and valid. Half of the first-level switches of the programmable capacitor module are open (rounded down to the nearest integer), and the remaining first-level switches are closed; half of the second-level switches are open (rounded down to the nearest integer), and the remaining second-level switches are closed. Step 402: The frequency and phase detector compares the frequency and phase relationship between the input clock and the feedback clock; Step 403: If the feedback clock frequency is lower than the input clock frequency, or the feedback clock phase lags behind the input clock phase, then output a charge pump charging command; Step 404: If the feedback clock frequency is higher than the input clock frequency, or the feedback clock phase leads the input clock phase, then output a charge pump discharge command. Step 405: After receiving a charging command, the charge pump closes the charging switch and opens the discharging switch to charge the control node and increase the output control voltage signal; after receiving a discharging command, the charging switch opens and the discharging switch closes to discharge the control node and decrease the output control voltage signal. Step 406: The loop filter performs voltage regulation and filtering on the voltage signal of the charge pump control node; Step 407: The voltage-controlled oscillator receives the regulated and filtered control voltage signal and controls it to generate a certain oscillation frequency. Within the designed operating range, the higher the control voltage signal, the higher the oscillation frequency of the voltage-controlled oscillator; the lower the control voltage signal, the lower the oscillation frequency of the voltage-controlled oscillator. Step 408: Frequency divider 2 receives the clock signal output from the voltage-controlled oscillator, divides it according to the design value, and outputs a feedback clock; Step 409: The feedback clock is connected to an external programmable capacitor module and input to the frequency and phase detector; Step 410: The frequency and phase detector detects the frequency and phase relationship between the feedback clock and the input clock; Step 411: If the frequency and phase detector detects that the frequency and phase relationship between the feedback clock and the input clock are inconsistent or unstable, the output LOCK signal is low, indicating that the output clock is invalid. Repeat steps 402 to 410. Step 412: If the frequency and phase detector detects that the frequency and phase relationship of the feedback clock and the input clock are relatively consistent and stable, the output LOCK signal is high, indicating that the output clock is valid, and proceed to the next step to adjust the delay of the output signal and the input signal; Step 413: Frequency divider 1 receives the clock signal output from the voltage-controlled oscillator, divides it according to the design value, and outputs the clock signal; Step 414: Compare the phase relationship between the input clock and the output clock, and record it in the register; Step 415: If the current output clock phase leads the input clock phase, the value of the programmable capacitor connected to the feedback clock node needs to be increased. Step 416: If the current output clock phase lags behind the input clock phase, the value of the programmable capacitor connected to the feedback clock node needs to be reduced. Step 417: Compare the relationship between the output clock phase and the input clock phase; Step 418: If the output clock phase is not equal to the input clock phase, repeat steps 413 to 416; Step 419: If the output clock phase is equal to the input clock phase, then the process ends.
[0023] Figure 5 The following is a specific implementation method for adjusting the capacitance value of the programmable capacitor module in a zero-delay buffering method with a programmable capacitor array according to the present invention. The steps are as follows: (1) Compare the delay between the output clock and the input clock (step 501); (2) If the output clock lags behind the input clock (step 502), and all secondary switches are closed and not all fine adjustment capacitors are connected (step 503), then the number of closed secondary switches increases by 1, the number of connected fine adjustment capacitors increases by 1 (step 504), and the process returns to step 501. (3) If the output clock lags behind the input clock (step 502), and all secondary switches are closed and all fine adjustment capacitors are connected (step 505), further determine the status of the primary switches. If all primary switches are not closed and all coarse adjustment capacitors are not connected (step 506), then the number of primary switches closed increases by 1, the number of coarse adjustment capacitors connected increases by 1 (step 507), all secondary switches are open, and all fine adjustment capacitors are not connected (step 508), and return to step 501; if all primary switches are closed and all coarse adjustment capacitors are connected (step 509), then it exceeds the adjustable range, and the process ends (step 510). (4) If the delay between the output clock and the input clock is 0 (step 511), then the delay adjustment ends (step 512). If the output clock leads the input clock (step 513), and all secondary switches are open at this time, but not all fine adjustment capacitors are disconnected (step 520), then the number of open secondary switches increases by 1, the number of connected fine adjustment capacitors decreases by 1 (step 521), and the process returns to step 501. (5) If the output clock leads the input clock (step 513), and all secondary switches are open and all fine adjustment capacitors are disconnected (step 514), further determine the status of the primary switches. If not all primary switches are open and not all coarse adjustment capacitors are disconnected (step 517), the number of primary switches open increases by 1, the number of coarse adjustment capacitors connected decreases by 1 (step 518), all secondary switches are closed, all fine adjustment capacitors are connected (step 519), and return to step 501; if all primary switches are open and all coarse adjustment capacitors are disconnected (step 515), the adjustable range is exceeded, and the process ends (step 516).
[0024] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A zero delay buffer device having a programmable capacitance array, comprising: include: Programmable capacitor module and phase-locked loop module; the phase-locked loop module includes a frequency and phase detector, a charge pump, a loop filter, a first frequency divider and a second frequency divider; The frequency and phase detector is used to determine the relationship between the input clock and the feedback clock; the charge pump receives the control signal generated by the frequency and phase detector and generates a control voltage signal through the charging and discharging principle; the loop filter performs voltage regulation and filtering on the control voltage signal of the charge pump; the voltage-controlled oscillator generates a certain oscillation frequency by passing the regulated and filtered control voltage signal through the voltage control unit; the first frequency divider divides the output frequency of the voltage-controlled oscillator to generate an output clock for output; the second frequency divider divides the output frequency of the voltage-controlled oscillator to generate a feedback clock, which is input to the frequency and phase detector for comparison with the input clock in terms of frequency and phase. The programmable capacitor module includes a primary switch and a secondary switch. The primary switch is used to select whether to connect a coarse adjustment capacitor to the node. If the primary switch is closed, the coarse adjustment capacitor is connected; if the primary switch is open, the coarse adjustment capacitor is not connected. The secondary switch is used to select whether to connect a fine adjustment capacitor to the node. If the secondary switch is closed, the fine adjustment capacitor is connected; if the secondary switch is open, the fine adjustment capacitor is not connected.
2. The zero delay buffer device with programmable capacitance array of claim 1, wherein, The coarse adjustment capacitor is a capacitor with a large capacitance value, used to adjust the delay relationship between the output clock and the input clock to a larger extent; the fine adjustment capacitor is a capacitor with a small capacitance value, used to adjust the delay relationship between the output clock and the input clock to a smaller extent; where "larger" and "smaller" are relative to each other.
3. The zero-delay buffer device with a programmable capacitor array as described in claim 1, characterized in that, The division coefficient of the first frequency divider is equal to the division coefficient of the second frequency divider.
4. The zero-delay buffer device with a programmable capacitor array as described in claim 1, characterized in that, The frequency of the input clock, the frequency of the output clock, and the frequency of the feedback clock are equal.
5. The zero-delay buffer device with a programmable capacitor array as described in claim 1, characterized in that, The determination of the relationship between the input clock and the feedback clock includes whether their frequencies are equal and whether their phases are leading or lagging.
6. A method for a zero-delay buffer device with a programmable capacitor array as described in any one of claims 1-5, characterized in that, The method includes the following steps: Step 1: The circuit is initially powered on and the input clock is stable and valid. Half of the programmable capacitor module's first-stage switches are open and the remaining first-stage switches are closed; half of the second-stage switches are open and the remaining second-stage switches are closed. Step 2: The frequency and phase detector compares the frequency and phase relationship of the input clock and the feedback clock; if the feedback clock frequency is lower than the input clock frequency, or the feedback clock phase lags behind the input clock phase, it outputs a charge pump charging command; if the feedback clock frequency is higher than the input clock frequency, or the feedback clock phase leads the input clock phase, it outputs a charge pump discharging command. Step 3: After receiving a charging command, the charge pump closes the charging switch and opens the discharging switch to charge the control node and increase the output control voltage signal; after receiving a discharging command, the charging switch opens and the discharging switch closes to discharge the control node and decrease the output control voltage signal. Step 4: The loop filter performs voltage regulation and filtering on the control voltage signal of the charge pump control node; Step 5: The voltage-controlled oscillator receives the regulated and filtered control voltage signal and controls it to generate the oscillation frequency. Within the designed operating range, the higher the control voltage signal, the higher the oscillation frequency of the voltage-controlled oscillator; the lower the control node voltage, the lower the oscillation frequency of the voltage-controlled oscillator. Step 6: The first frequency divider receives the clock signal output from the voltage-controlled oscillator, divides it according to the design value, and outputs the clock signal. Step 7: The second frequency divider receives the clock signal output from the voltage-controlled oscillator, divides it according to the design value, and outputs a feedback clock; Step 8: The feedback clock is connected to an external programmable capacitor module and input to the frequency and phase detector; Step 9: If the frequency and phase detector detects that the frequency and phase relationship of the feedback clock and the input signal are relatively consistent and stable, the output LOCK signal is high, indicating that the output clock signal is valid, and proceed to the next step to adjust the delay of the output signal and the input signal; otherwise, the output LOCK signal is low, indicating that the output clock signal is invalid, and continue to repeat steps 2 to 9. Step 10: Compare the phase relationship between the input clock and the output clock, and record it in the register; Step 11: If the current output clock phase lags behind the input clock phase, the value of the programmable capacitor connected to the feedback clock node needs to be increased; if the current output clock signal phase leads the input clock phase, the value of the programmable capacitor connected to the feedback clock node needs to be decreased. Step 12: If the output clock phase is not equal to the input clock phase, repeat steps 10 to 12; if the output clock phase is equal to the input clock phase, end.
7. The method as described in claim 6, characterized in that, The programmable capacitor module corrects and compensates for signal interference caused by different application environments and load conditions by adjusting the capacitance value, including the following steps: Step 21: Compare the output clock delay with the input clock delay; Step 22: If the output clock lags behind the input clock, and all secondary switches are closed and not all fine adjustment capacitors are connected, then the number of closed secondary switches increases by 1, the number of connected fine adjustment capacitors increases by 1, and the process returns to step 21. Step 23: If the output clock lags behind the input clock, and all secondary switches are closed and all fine adjustment capacitors are connected, further determine the status of the primary switches; if not all primary switches are closed and not all coarse adjustment capacitors are connected, then increase the number of primary switches closed by 1, increase the number of coarse adjustment capacitors connected by 1, open all secondary switches, disconnect all fine adjustment capacitors, and return to step 21; if all primary switches are closed and all coarse adjustment capacitors are connected, then the adjustable range is exceeded, and the process ends. Step 24: If the delay between the output clock and the input clock is 0, then the delay adjustment is complete; If the output clock leads the input clock, and all secondary switches are open at this time, and not all fine adjustment capacitors are disconnected, then the number of open secondary switches increases by 1, the number of connected fine adjustment capacitors decreases by 1, and the process returns to step 21. Step 25: If the output clock leads the input clock, and all secondary switches are open and all fine adjustment capacitors are disconnected, further determine the status of the primary switches; if not all primary switches are open and not all coarse adjustment capacitors are disconnected, then increase the number of primary switches open by 1, decrease the number of coarse adjustment capacitors connected by 1, close all secondary switches, connect all fine adjustment capacitors, and return to step 21; if all primary switches are open and all coarse adjustment capacitors are disconnected, then the adjustable range is exceeded, and the process ends.
8. The method as described in claim 6, characterized in that, The output clock signal has the same phase as the input clock, exhibiting zero delay.