Manufacturing method of high-density buried via multilayer board for AI server storage modules

Abstract

This application relates to a method for manufacturing high-density buried via multilayer boards suitable for AI server storage modules, comprising the following steps: drilling, high-temperature baking, flash plating, dry film deposition of the vias, resin plug application, ceramic brushing, and browning film application are sequentially performed on a sub-board that has undergone one-time lamination; during the above expansion and contraction control processing steps and before the second lamination, layer misalignment detection strips pre-set in the non-functional areas of the sub-board are measured to obtain real-time expansion and contraction data characterizing the actual dimensional expansion and contraction state of the sub-board after processing; the real-time expansion and contraction data are input into a second lamination alignment system, which dynamically adjusts the grasping compensation coefficient of the composite alignment target set on the sub-board based on the real-time expansion and contraction data, and performs subsequent processing on at least two sub-boards according to the compensated alignment reference to form a multilayer board. This manufacturing method reduces expansion and contraction variables through source process optimization, significantly improving alignment accuracy and yield.

Description

Technical Field

[0001] This application relates to printed circuit board manufacturing technology, specifically to a method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules. Background Technology

[0002] With the continuous expansion of server data throughput, the demand for storage module capacity and quantity has surged, and 128GB and 256GB memory modules have been put into production and launched. In order to improve wiring density and expand memory capacity, PCB boards need to be upgraded from the traditional 12 layers to 16 to 28 layers, and the number of vias needs to be greatly increased, with a single memory module having more than 4,000 vias, introducing buried via design. To achieve this goal, the industry generally adopts a two- to three-stage lamination BVH buried via process, which involves laminating two multilayer sub-boards, each containing 8 or 14 layers (e.g., L1-L8 layers and L9-L16 layers), drilling, electroplating, resin plugging, image transfer, and etching processes, and then laminating them a second time to form a complete 16-28 layer board.

[0003] However, this process has the following drawbacks:

[0004] Sub-board Differential Processing Expansion and Contraction: After a single lamination process, the sub-board undergoes drilling, full-board electroplating, resin plugging, mechanical grinding, and etching. During these processes, it is subjected to the combined effects of mechanical stress, thermal stress, and chemical treatment, resulting in significant, non-linear dimensional changes. For example, mechanical grinding causes significant expansion in the X-direction, while grinding stress leads to abnormally increased shrinkage after subsequent etching. The variation in expansion and contraction between different batches, and even within the same batch, can be extremely large.

[0005] Secondary lamination layer misalignment and via misalignment: When two sub-boards that have undergone different expansion and contraction processes are laminated a second time, their dimensional states have already shifted uncontrollably. Using traditional fixed coordinates or physical pin alignment methods easily leads to severe deterioration of interlayer alignment. This interlayer misalignment directly transmits to the subsequent second through-hole drilling process, causing deviations between the through-holes and the buried vias in the sub-board after the first lamination. During the outer layer graphic image transfer processing, the same layer graphic simultaneously aligns with the buried vias in layers L1-L8, layers L9-L16, and through-holes in layers L1-L16, resulting in a "via misalignment" problem. This issue has become the primary cause of scrap for this type of high-multilayer board, with an average scrap rate exceeding 25%, and a defect rate in trial production batches even exceeding 35%. Summary of the Invention

[0006] To overcome the above-mentioned defects, this application provides a manufacturing method for high-density buried via multilayer boards suitable for AI server storage modules. This manufacturing method reduces expansion and contraction variables through source process optimization, and combined with real-time detection and dynamic compensation, it can significantly improve interlayer alignment, fundamentally prevent via misalignment, and significantly improve alignment accuracy and yield.

[0007] The technical solution adopted by this application to solve its technical problem is:

[0008] A method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules includes the following steps:

[0009] Sub-board expansion and contraction control processing steps: After completing one pressing, the sub-board is sequentially drilled, baked at high temperature, flash plated, plated dry film, resin plug film, ceramic brush, and browning film.

[0010] Real-time expansion and contraction data acquisition steps: When the above expansion and contraction control processing steps are completed and before the second pressing, the layer deviation detection strips pre-set in the non-functional area of ​​the sub-board are measured to obtain real-time expansion and contraction data that characterizes the actual size expansion and contraction state of the sub-board after processing.

[0011] The data-driven secondary lamination alignment step involves inputting the real-time expansion and contraction data into the secondary lamination alignment system. Based on the real-time expansion and contraction data, the system dynamically adjusts the grasping compensation coefficient of the composite alignment target set on the sub-board, and performs subsequent processing on at least two sub-boards according to the compensated alignment reference to form a multilayer board. The subsequent processing includes at least one of riveting, secondary lamination, and drilling and outer layer exposure after secondary lamination.

[0012] Optionally, the sub-plate expansion and contraction control processing steps include the following steps:

[0013] Fabrication of sub-boards: Fabricate at least two sub-boards, each including inner layer circuitry;

[0014] High-temperature baking: Drill holes in the sub-board and then bake at high temperature;

[0015] Through-hole dry film: After the sub-board is baked at high temperature, a copper layer is flash plated, then through-hole dry film is applied, and electroplating is performed to thicken it;

[0016] Resin plugging film: After removing the original film, apply a resin plugging protective film to the sub-board and perform laser drilling;

[0017] Ceramic brush: After laser drilling, the sub-board is filled with resin, and after the film is removed, the sub-board is subjected to ceramic brushing.

[0018] Browning film application: The outer layer circuit is fabricated on the daughterboard, an anti-browning film is applied, and then browning treatment is performed.

[0019] Subsequent molding steps: Press at least two sub-boards after browning treatment together to form a complete multilayer board, and then peel off the film and drill holes.

[0020] Optionally, the process also includes a multilayer board pressing step: pressing at least two sub-boards that have completed browning together to form a complete multilayer board, and then drilling holes after removing the film.

[0021] Optionally, during the flash copper plating process, a thin copper layer with a thickness of 0.2±0.02mil is formed; the high-temperature baking requires frame baking, with a baking temperature of 160~200℃ and a time of 90~150min.

[0022] Optionally, during the through-hole dry film process, through-hole dry film is attached to the outer layer of one side of the sub-board, and the dry film is exposed and developed to expose the buried holes that need to be electroplated. The window size formed after development is 0.075mm±0.01mm larger than the corresponding buried hole on one side. Then, copper is plated on the hole walls of the buried holes that are not covered by the dry film.

[0023] Optionally, during the resin plugging process, a high-temperature resistant release film is applied to the outer layer of one side of the sub-board, and the film is opened only at the buried hole location where resin plugging is required before the resin plugging operation is performed.

[0024] A carbon dioxide laser drilling machine was used to perform laser windowing on the conductive through-holes of the film. The distance between the boundary of the solder mask window and the edge of the conductive through-hole was 0.15mm±0.02mm. The laser parameters were set as follows: power 5600W, frequency 100HZ, energy 6mj.

[0025] Optionally, during the browning film application process, an anti-browning film is applied to the outer layer of one side of the sub-board. The anti-browning film includes a PI base film, a high-temperature resistant adhesive layer, and a release film applied sequentially. The thickness of the browning film is 65±10μm.

[0026] Optionally, the layer offset detection strip includes an outer layer monitoring structure and an inner layer monitoring structure. The outer layer monitoring structure is disposed on the surface of the sub-board. The outer layer monitoring structure includes an outer layer test point hole, an outer layer test pad disposed around the outer layer test point hole, and an outer layer isolation ring surrounding the outer layer test pad.

[0027] The inner layer monitoring structure is disposed on different inner layers of the sub-board. The inner layer monitoring structure includes inner layer test point holes, inner layer test pads disposed around the inner layer test point holes, and inner layer isolation rings disposed around the inner layer test pads. The inner layer isolation rings of each inner layer have a specific width, and the widths of at least two inner layer isolation rings are different from each other.

[0028] The outer test pads of the outer monitoring structure are electrically connected to the corresponding inner test point holes of the inner layer through conductive structures.

[0029] Using high-precision optical measurement equipment or a four-terminal fixture, coordinate measurements or continuity tests are performed on the outer layer test point holes and / or inner layer test point holes on the layer offset detection strip to obtain the actual dimensional expansion and contraction of the sub-board in the X and Y directions; the expansion and contraction is used as the real-time expansion and contraction data and input to the secondary pressing and alignment system.

[0030] Optionally, the sub-board includes a first sub-board and a second sub-board;

[0031] The inner monitoring structure includes:

[0032] The first inner layer monitoring structure is located in the inner layer of the first sub-board;

[0033] The second inner layer monitoring structure is located in the inner layer of the second sub-board;

[0034] The third inner layer monitoring structure is installed through the first sub-board and the second sub-board;

[0035] The outer test pads of the outer monitoring structure include:

[0036] The first test pad group is electrically connected to the first inner layer monitoring structure only through a conductive structure;

[0037] The second test pad group is electrically connected to the second inner layer monitoring structure only through a conductive structure;

[0038] The third test pad group is electrically connected to the third inner layer monitoring structure via a conductive structure.

[0039] Optionally, the inner layer monitoring structure includes inner layer test point holes arranged in an L-shape, used to monitor the offset in the X and Y directions by measuring electrical parameters in different directions.

[0040] Optionally, the width of the inner isolation ring is 5 mil to 7 mil, and the width of the outer isolation ring is 5 mil to 7 mil.

[0041] Optionally, the composite alignment target includes at least two sets of targets disposed on the sub-plate, namely:

[0042] The first set of composite targets is used for riveting alignment before secondary pressing, alignment reference during the secondary pressing process, outer layer exposure alignment after secondary pressing, and / or alignment reference for drilling after secondary pressing.

[0043] The second set of composite targets is used for borehole deviation verification and / or borehole compensation after secondary pressing and drilling.

[0044] Optionally, the sub-plate includes a first sub-plate and a second sub-plate, and the first set of composite targets includes a first alignment target and a second alignment target;

[0045] The first alignment target includes a plurality of first buried holes arranged on the periphery and a first through hole arranged in the center. The first buried holes are connected to the corresponding layer of the first sub-board, and the first through hole is connected to the entire layer.

[0046] The second alignment target includes a plurality of second buried holes arranged on the periphery and a second through hole arranged in the center. The second buried holes are connected to the corresponding layer of the second sub-board, and the second through hole is connected to the entire layer.

[0047] During alignment, the position data of the outer periphery holes and the central through hole of the first alignment target and / or the second alignment target are captured according to preset weights, and the expansion and contraction compensation coefficient is calculated accordingly.

[0048] Optionally, the preset weights are dynamically allocated based on the real-time expansion and contraction data, including:

[0049] The expansion and contraction states of the first sub-board and the second sub-board are determined based on the real-time expansion and contraction data.

[0050] Based on the expansion and contraction state, the first through hole is assigned a higher weight than the first buried hole, and the second through hole is assigned a higher weight than the second buried hole;

[0051] The optimal alignment center is calculated by weighted averaging of the position data of the first buried hole, the second buried hole, the first through hole, and the second through hole.

[0052] Optionally, a hollow area is provided in the corresponding layer below the first alignment target and / or the second alignment target. The diameter of the hollow area is larger than the outline of the corresponding target, so as to prevent PP glue from filling and clogging the target during secondary pressing.

[0053] Optionally, the second set of composite targets includes a first verification target and a second verification target;

[0054] The first verification target is set on the first sub-board and includes:

[0055] At least one third buried via is provided, which is connected to the corresponding layer of the first sub-board;

[0056] A sleeve section is disposed inside the third buried hole, and the sleeve section penetrates the first sub-plate;

[0057] And a first copper ring disposed on the outer surface of the first sub-board, the first copper ring surrounding the third buried hole;

[0058] The second verification target is set on the second sub-board and includes:

[0059] At least one fourth buried via, connecting to the corresponding layer of the second sub-board;

[0060] A sleeve section is disposed inside the fourth buried hole, and the sleeve section penetrates the second sub-plate;

[0061] And a second copper ring disposed on the outer surface of the second sub-board, the second copper ring surrounding the fourth buried hole;

[0062] In this process, the sleeve section of the first verification target and the sleeve section of the second verification target are connected and conductive after secondary pressing, together forming a sleeve that penetrates the entire layer of the multilayer board.

[0063] Optionally, the second set of composite targets is used to drill with the sleeve hole as a reference during drilling after secondary pressing, and to determine whether there is a deviation by visually or optically detecting the relative position of the wall of the through hole and the wall of the nested buried hole, as well as the relative position of the wall of the sleeve hole and the corresponding copper ring; if there is a deviation, the offset is fed back to the drilling system for compensation and adjustment.

[0064] The beneficial effects of this application are:

[0065] (1) In this application, after drilling holes in the sub-board, a high-temperature baking process is added immediately. The purpose is to completely release the residual stress inside the material after experiencing the mechanical stress of drilling, stabilize the substrate size, and avoid uncontrollable deformation caused by the slow release of stress in subsequent processes. By flash plating and plated dry film, the copper thickness on the outer surface of the sub-board is stably controlled in a thin copper state without the need to reduce copper, thereby controlling the key expansion and contraction variable of copper thickness change to a minimum and stable state. By applying film, the influence of resin, chemicals, mechanical brushing and other processes on the outer surface of the sub-board is isolated. That is, this application controls the key variables that cause expansion and contraction, such as copper thickness change, resin protrusion and mechanical stress, to a minimum and stable state, so that the sub-board has more stable and predictable geometric dimensions before entering the second lamination.

[0066] (2) In this application, the layer offset detection strip undergoes the same processing steps as the sub-board body. After key process nodes, such as resin plugging and etching, the absolute position coordinates of specific target points on the layer offset detection strip are measured using high-precision optical inspection equipment or a dedicated four-terminal fixture, or the relative offset between different conductive networks is measured. By comparing the measured values ​​with the original design coordinates, the macroscopic dimensional expansion and contraction of the sub-board in the X and Y directions can be accurately quantified, and the distribution of expansion and contraction between different layers can be analyzed. Its core function is to act as an embedded, online sensor, providing digital, real-time expansion and contraction status reports for each specific sub-board, rather than a simple pass / fail judgment.

[0067] (3) In this application, the real-time expansion and contraction data is input into the secondary pressing alignment system and the drilling system. The system dynamically adjusts the composite target grasping logic and compensation coefficient according to the data to perform high-precision secondary pressing. After pressing, drilling and post-drilling visual verification are performed using the composite target to realize closed-loop monitoring and fine-tuning of the process.

[0068] (4) This application reduces expansion and contraction variables through source process optimization. Combined with real-time detection and dynamic compensation, it can significantly improve the interlayer alignment of 16-28 layer boards, fundamentally prevent via misalignment, and significantly improve alignment accuracy and yield. The optimized process flow, such as film plugging, film copper plating, and film browning, has a high degree of standardization, reduces the dependence on operating experience, and makes the production process more stable and controllable, suitable for large-scale mass production. Attached Figure Description

[0069] Figure 1 This is a simplified schematic diagram of the outer monitoring structure in this application;

[0070] Figure 2 This is a simplified schematic diagram of the inner monitoring structure in this application;

[0071] Figure 3 This is a simplified schematic diagram of the first group of composite targets in this application;

[0072] Figure 4 This is a simplified schematic diagram of the second group of composite targets in this application. Detailed Implementation

[0073] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the embodiments of this application. Obviously, the embodiments described in this application are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0074] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such uses of the terms can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0075] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0076] A method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules includes the following steps:

[0077] Sub-board expansion and contraction control processing steps: After one pressing, the sub-board is sequentially subjected to drilling, high-temperature baking, flash plating, hole plating dry film, resin plug film application, ceramic grinding, and browning film application to stabilize the dimensional changes of the sub-board in subsequent processing.

[0078] Real-time expansion and contraction data acquisition steps: When the above expansion and contraction control processing steps are completed and before the second pressing, the layer deviation detection strips pre-set in the non-functional area of ​​the sub-board are measured to obtain real-time expansion and contraction data that characterizes the actual size expansion and contraction state of the sub-board after processing.

[0079] The data-driven secondary lamination alignment step involves inputting the real-time expansion and contraction data into the secondary lamination alignment system. Based on the real-time expansion and contraction data, the system dynamically adjusts the grasping compensation coefficient of the composite alignment target set on the sub-board, and performs subsequent processing on at least two sub-boards according to the compensated alignment reference to form a multilayer board. The subsequent processing includes at least one of riveting, secondary lamination, and drilling and outer layer exposure after secondary lamination.

[0080] In this application, after drilling holes in the sub-board, a high-temperature baking process is immediately added. This process ensures that the residual stress inside the material is completely released after experiencing the mechanical stress of drilling, stabilizing the substrate dimensions and preventing uncontrollable deformation caused by the slow release of stress in subsequent processes. Through flash plating and dry film plating, the copper thickness on the outer surface of the sub-board is stably controlled at a thin copper state, eliminating the need for copper reduction. This minimizes and stabilizes the key expansion and contraction variable of copper thickness variation. Through film lamination, the influence of resin, chemicals, mechanical abrasion, and other processes on the outer surface of the sub-board is isolated. In other words, this application minimizes and stabilizes key expansion and contraction variables such as copper thickness variation, resin protrusion, and mechanical stress, resulting in more stable and predictable geometric dimensions for the sub-board before entering the second lamination stage.

[0081] In this application, the layer offset detection strip undergoes the same processing steps as the sub-board body. After key process nodes, such as resin plugging and etching, high-precision optical inspection equipment or a dedicated four-terminal fixture is used to measure the absolute position coordinates of specific target points on the layer offset detection strip, or to measure the relative offset between different conductive networks. By comparing the measured values ​​with the original design coordinates, the macroscopic dimensional expansion and contraction of the sub-board in the X and Y directions can be accurately quantified, and the distribution of expansion and contraction across different layers can be analyzed. Its core function is to act as an embedded, online sensor, providing digital, real-time expansion and contraction status reports for each specific sub-board, rather than a simple pass / fail judgment.

[0082] In this application, the real-time expansion and contraction data is input into the secondary pressing alignment system and the drilling system. The system dynamically adjusts the composite target grasping logic and compensation coefficient according to the data to perform high-precision secondary pressing. After pressing, drilling is performed using the composite target and visual verification is performed after drilling, realizing closed-loop monitoring and fine-tuning of the process.

[0083] This application reduces expansion and contraction variables through source process optimization. Combined with real-time detection and dynamic compensation, it can significantly improve the interlayer alignment of 16-28 layer boards, fundamentally prevent via misalignment, and significantly improve alignment accuracy and yield. The optimized process flow, such as film-applied via plugging, film-applied copper plating, and film-applied browning, has a high degree of standardization, reducing reliance on operational experience and making the production process more stable and controllable, suitable for large-scale mass production.

[0084] The sub-plate expansion and contraction control processing steps include the following steps:

[0085] Fabrication of sub-boards: Fabricate at least two sub-boards, each including inner layer circuitry;

[0086] High-temperature baking: Drill holes in the sub-board and then bake at high temperature;

[0087] Through-hole dry film: After the sub-board is baked at high temperature, a copper layer is flash plated, then through-hole dry film is applied, and electroplating is performed to thicken it;

[0088] Resin plugging film: After removing the original film, apply a resin plugging protective film to the sub-board and perform laser drilling;

[0089] Ceramic grinding brush: After laser drilling, the sub-board is filled with resin, and after the film is removed, the sub-board is subjected to ceramic grinding brush; a 4-axis ceramic grinding brush is used for light grinding, replacing the traditional 12-axis high-cutting grinding.

[0090] Anti-browning film application: The outer layer circuit is fabricated on the sub-board, an anti-browning film is applied, and then browning treatment is performed; before browning treatment, a single layer of anti-browning film is applied to ensure that the outermost copper layer does not react with the browning solution.

[0091] Subsequent molding steps: At least two sub-boards after browning treatment are laminated to form a complete multilayer board, and the film is removed and holes are drilled. The process of preparing the sub-board includes: board cutting, inner layer circuit fabrication, pre-lamination punching of positioning holes, automatic optical inspection of inner layers, and lamination to form the sub-board.

[0092] The manufacturing method further includes a multilayer board pressing and forming step: pressing at least two sub-boards that have completed browning to form a complete multilayer board, and then drilling holes after removing the film. The multilayer board pressing and forming step is completed in a data-driven secondary pressing and alignment step.

[0093] During the flash copper plating process, a thin copper layer with a thickness of 0.2 ± 0.02 mil is formed. The high-temperature baking requires frame baking, with a baking temperature of 160~200℃ and a time of 90~150 min. After the circuit board undergoes hole wall metallization (PTH), it enters the first tank or unit (VCP) of the vertical continuous plating line (VCP), where a copper layer with a thickness of 0.2 mil (approximately 5 micrometers) is rapidly electroplated as a base layer for subsequent thicker plating. This process prepares the dry film for the holes, metallizing the hole walls after drilling and avoiding excessive roughening during the dry film pretreatment, which could affect the quality of the hole wall metallization.

[0094] In the dry film plating process, a dry film for plating is applied to the outer layer of one side of the sub-board. The dry film is then exposed and developed to reveal the buried vias that require electroplating. After development, the resulting window size is 0.075mm ± 0.01mm larger than the corresponding buried via on one side. Copper plating is then performed on the walls of the buried vias not covered by the dry film. This process can complete single-sided copper plating, effectively preventing unnecessary thick copper deposition on the outer surface, which traditional processes can result in copper thickness exceeding 1.5mil.

[0095] During the resin plugging process, a high-temperature resistant release film is applied to the outer layer of one side of the daughterboard. Windows are only opened in the film at the locations of the buried vias where resin plugging is required before the resin plugging operation. The film protects the outermost surfaces, such as layers L1 and L16, preventing resin contamination of the copper surface and laying the foundation for eliminating subsequent copper reduction and additional polishing processes. The applied release film consists of two layers of high-temperature resistant, high-transparency release film, with a release layer thickness of 60μm. It features low adhesion, high temperature resistance >180℃*2H, and leaves no residue after baking.

[0096] A CO2 laser drilling machine is used to laser-open the conductive vias of the film. The distance between the boundary of the solder mask opening and the edge of the conductive via is 0.15mm ± 0.02mm. Laser parameters are set as follows: power 5600W, frequency 100HZ, energy 6mJ. Laser opening is performed on one side only, with resin plugging the opening surface for ink application and the back side for ink exit. This reduces resin buildup on one side and decreases the number of high-speed cutting and grinding cycles.

[0097] During the browning film application process, an anti-browning film is applied to the outer layer of one side of the sub-board. This anti-browning film comprises a PI base film, a high-temperature resistant adhesive layer, and a release film, sequentially laminated together. The thickness of the browning film is 65±10μm. In one specific embodiment, the thickness of the brown PI base film is 36μm, the thickness of the high-temperature resistant adhesive layer is 5μm, and the thickness of the release film is 25μm. The browning film exhibits excellent adhesion and temperature resistance, can withstand use at 230℃, and features low shrinkage, non-breakability, and no adhesive residue.

[0098] The functions of the film are as follows: 1. This film prevents the copper surface from being corroded by the browning agent, and completely eliminates the need for high-cutting grinding to remove the PP powder adhering to the surface after secondary lamination in traditional processes; 2. It reduces copper content after browning and performs high-cutting grinding to remove the resin protrusions generated after copper reduction; 3. This directly eliminates the huge expansion and contraction stress source caused by three strong mechanical / chemical treatments; 4. The browning film thickness is about 0.06mm, which raises the board surface and appropriately buffers the pressure damage to half of the board caused by the protrusion of the rivets, and can effectively avoid the problem of pressure loss around the rivets caused by the protrusion of the rivets.

[0099] The layer offset detection strip includes an outer layer monitoring structure and an inner layer monitoring structure. The outer layer monitoring structure is disposed on the surface of the sub-board. The outer layer monitoring structure includes an outer layer test point hole, an outer layer test pad disposed around the outer layer test point hole, and an outer layer isolation ring surrounding the outer layer test pad.

[0100] The inner layer monitoring structure is disposed on different inner layers of the sub-board. The inner layer monitoring structure includes inner layer test point holes, inner layer test pads disposed around the inner layer test point holes, and inner layer isolation rings disposed around the inner layer test pads. The inner layer isolation rings of each inner layer have a specific width, that is, have a specific hole-to-copper spacing of that inner layer, and the widths of at least two inner layer isolation rings are different from each other.

[0101] The outer test pads of the outer monitoring structure are electrically connected to the corresponding inner test point holes of the inner layer through conductive structures.

[0102] Using high-precision optical measuring equipment or a four-terminal fixture, coordinate measurements or continuity tests are performed on the outer layer test point holes and / or inner layer test point holes on the layer offset detection strip to obtain the actual dimensional expansion and contraction of the sub-board in the X and Y directions; the expansion and contraction is used as real-time expansion and contraction data and input to the secondary lamination alignment system. The outer layer monitoring structure is fabricated synchronously with the outer layer circuitry of the sub-board, and the inner layer monitoring structure is fabricated synchronously with the inner layer circuitry of the sub-board.

[0103] The sub-board includes a first sub-board and a second sub-board;

[0104] The inner monitoring structure includes:

[0105] The first inner layer monitoring structure is located in the inner layer of the first sub-board;

[0106] The second inner layer monitoring structure is located in the inner layer of the second sub-board;

[0107] The third inner layer monitoring structure is installed through the first sub-board and the second sub-board;

[0108] The outer test pads of the outer monitoring structure include:

[0109] The first test pad group is electrically connected to the first inner layer monitoring structure only through a conductive structure;

[0110] The second test pad group is electrically connected to the second inner layer monitoring structure only through a conductive structure;

[0111] The third test pad group is electrically connected to the third inner layer monitoring structure via a conductive structure.

[0112] The inner layer monitoring structure includes L-shaped inner layer test point holes, used to monitor the offset in the X and Y directions by measuring electrical parameters in different directions.

[0113] The test pads of the outer monitoring structure include at least one pair of four-terminal test pads for connecting a four-terminal fixture to perform high-precision continuity testing.

[0114] The width of the inner isolation ring is 5 mil to 7 mil, and the width of the outer isolation ring is 5 mil to 7 mil. For example... Figure 2 As shown, the width of the inner isolation ring, i.e., the distance from the inner test point hole to the copper, includes five specifications: 5mil, 5.5mil, 6.0mil, 6.5mil, and 7mil. Figure 1 As shown, the width of the outer isolation ring, i.e. the distance from the outer test point hole to the copper, includes five specifications: 5mil, 5.5mil, 6.0mil, 6.5mil, and 7mil.

[0115] The diameter of the outer layer test point hole is 0.25±0.05mm, and the ring width of the outer layer test pad is 10±2mm. This layer offset test strip undergoes all secondary processing steps together with the sub-board body. After key process nodes (such as after resin plugging or final etching), the electrical or geometric parameters on the test strip can be obtained through measuring equipment to quantify the expansion and contraction state of the sub-board.

[0116] As one implementation method, a high-precision optical measurement device (such as a CCD) can be used to measure the absolute position coordinates of a specific target point (such as the center of the outer test point hole) on the test strip. By comparing the measured value with the original design coordinates, the macroscopic dimensional expansion and contraction of the sub-board in the X and Y directions can be accurately calculated.

[0117] As another implementation method, a dedicated four-terminal fixture can be used to measure the relative offset between different conductive networks. By analyzing the electrical changes corresponding to the test points of each inner layer, the distribution of expansion and contraction between different layers can be analyzed.

[0118] The core function of this layer offset detection strip is to act as an embedded, online sensor, providing a digital, real-time expansion and contraction status report for each individual sub-board before secondary lamination. This provides a basis for subsequent data-driven precise alignment, rather than a simple pass / fail judgment.

[0119] In order to obtain accurate dimensional data of the sub-board after processing, this application designs and manufactures a special RVC (Resin Via Capture) layer deviation detection strip on the edge of the sub-board or other non-functional areas. In the finished product state, each test hole of the RVC layer deviation detection strip has a predefined electrical connection relationship, which is used to quantitatively detect the expansion and contraction state of the sub-board before secondary pressing.

[0120] Specifically, the test holes in the layer offset detection strip are distinguished by different symbols in the accompanying drawings according to their different conduction levels. These symbols are only used to clearly describe this application and do not constitute a limitation on the physical colors.

[0121] In one specific embodiment, such as Figure 1 As shown, the first type of test hole (such as...) Figure 1 (As shown in the green legend), its electrical network is configured to conduct only the L1-L8 layers of the first sub-board for monitoring the interlayer alignment within the first sub-board;

[0122] Type II test wells (such as...) Figure 1 (As shown in the blue illustration), its electrical network is configured to conduct only layers L9-L16 of the second sub-board for monitoring interlayer alignment within the second sub-board;

[0123] Third type of test hole (such as...) Figure 1 (As shown in the black diagram in the middle), its electrical network is configured to conduct all layers L1-L16 to monitor the overall interlayer alignment after the first sub-board and the second sub-board are laminated.

[0124] Preferably, the third type of test hole is designed as a four-terminal test structure for connecting a four-terminal fixture to perform high-precision continuity testing, so as to accurately measure the relative offset between each network. When an inner layer is offset, the electrical connection state between the isolation ring of the corresponding layer and the test hole will change. By measuring the continuity between different test holes, the layer, hole diameter and offset direction of the offset can be quickly located.

[0125] The composite alignment target includes at least two sets of targets disposed on the sub-plate, namely:

[0126] The first set of composite targets is used for riveting alignment before secondary pressing, alignment reference during the secondary pressing process, outer layer exposure alignment after secondary pressing, and / or alignment reference for drilling after secondary pressing.

[0127] The second set of composite targets is used for borehole deviation verification and / or borehole compensation after secondary pressing and drilling.

[0128] The sub-plate includes a first sub-plate and a second sub-plate, and the first set of composite targets includes a first alignment target and a second alignment target;

[0129] The first alignment target includes a plurality of first buried holes arranged on the periphery and a first through hole arranged in the center. The first buried holes are connected to the corresponding layer of the first sub-board, and the first through hole is connected to the entire layer.

[0130] The second alignment target includes a plurality of second buried holes arranged on the periphery and a second through hole arranged in the center. The second buried holes are connected to the corresponding layer of the second sub-board, and the second through hole is connected to the entire layer.

[0131] During alignment, the system captures the position data of the peripheral buried holes and central through holes of the first and / or second alignment targets according to preset weights, and calculates the expansion and contraction compensation coefficient accordingly. Specifically, the secondary pressing alignment system dynamically allocates capture weights based on the real-time expansion and contraction data, assigning a higher weight to the through hole features than to the buried hole features in the first and second alignment targets. The system then performs a weighted average of the position data of the through hole and buried hole features to calculate the optimal alignment center. Based on this, it dynamically compensates for the alignment reference during the secondary pressing and riveting process, as well as for drilling and / or outer layer exposure after pressing.

[0132] The preset weights are dynamically allocated based on the real-time expansion and contraction data, including:

[0133] The expansion and contraction states of the first sub-board and the second sub-board are determined based on the real-time expansion and contraction data.

[0134] Based on the expansion and contraction state, the first through hole is assigned a higher weight than the first buried hole, and the second through hole is assigned a higher weight than the second buried hole;

[0135] The positional data of the first buried hole, the second buried hole, the first through hole, and the second through hole are weighted and averaged to calculate the optimal alignment center. In the preset weights, the weight of the first through hole is greater than the weight of the first buried hole, and the weight of the second through hole is greater than the weight of the second buried hole; preferably, the weights of the first through hole and the second through hole each account for 60%-70%, and the weights of the first buried hole and the second buried hole each account for 30%-40%.

[0136] The secondary pressing and alignment system dynamically allocates grasping weights based on the real-time expansion and contraction data: the weights of the first through hole and the second through hole are higher than the weights of the first buried hole and the second buried hole.

[0137] The position data of the first buried hole, the second buried hole, the first through hole, and the second through hole are weighted and averaged to calculate the optimal alignment center, and dynamic compensation is performed on the secondary pressing and riveting, drilling after pressing, or outer layer exposure accordingly.

[0138] Optionally, the first and second peripheral holes are 12 in number and arranged in a ring; the first and second central through holes are 1.

[0139] During alignment, the position data weights of the central first and second through holes are set to be greater than the position data weights of the peripheral first and second buried holes.

[0140] The weight of the first and second central through holes is 60%-70%, and the weight of the first and second peripheral buried holes is 30%-40%.

[0141] The corresponding layer below the first and / or second alignment targets has a hollowed-out area. The diameter of the hollowed-out area is larger than the outline of the corresponding target to prevent PP glue from filling and clogging the target during secondary lamination. The diameter of the hollowed-out area is 6.5mm ± 0.5mm.

[0142] The second set of composite targets includes a first verification target and a second verification target;

[0143] The first verification target is set on the first sub-board and includes:

[0144] At least one third buried via is provided, which is connected to the corresponding layer of the first sub-board;

[0145] A sleeve section is disposed inside the third buried hole, and the sleeve section penetrates the first sub-plate;

[0146] And a first copper ring disposed on the outer surface of the first sub-board, the first copper ring surrounding the third buried hole;

[0147] The second verification target is set on the second sub-board and includes:

[0148] At least one fourth buried via, connecting to the corresponding layer of the second sub-board;

[0149] A sleeve section is disposed inside the fourth buried hole, and the sleeve section penetrates the second sub-plate;

[0150] And a second copper ring disposed on the outer surface of the second sub-board, the second copper ring surrounding the fourth buried hole;

[0151] In this design, the sleeve segment of the first verification target and the sleeve segment of the second verification target are connected and conductive after secondary lamination, jointly forming a sleeve that penetrates the entire multilayer board. The diameter of the sleeve segment is smaller than the diameter of the embedded via it. The sleeve segment is formed by secondary drilling after the first and / or second embedded vias have been resin-filled. The criterion for determining whether there is a misaligned via is whether the wall of the sleeve segment is tangent to the wall of the embedded via. The offset is fed back to the drilling system for compensation and adjustment, including adjusting the expansion and contraction compensation value of subsequent drillings and / or real-time correction of the drilling coordinates of other areas of the same multilayer board.

[0152] The first copper ring is concentrically arranged with the sleeve section of the first verification target, and the second copper ring is concentrically arranged with the sleeve section of the second verification target.

[0153] The second set of composite targets is used to drill holes with the sleeve hole as a reference during drilling after secondary pressing. The relative positions of the through hole wall and the nested buried hole wall, as well as the relative positions of the sleeve hole wall and the corresponding copper ring, are visually or optically detected to determine whether there is a hole deviation. If a hole deviation exists, the offset is fed back to the drilling system for compensation and adjustment.

[0154] In one possible implementation, the diameter of the third and fourth buried holes is 0.5 mm, and the diameter after resin plugging is 0.45 mm; the diameter of the sleeve hole is 0.2 mm.

[0155] The single-sided distance between the edge of the sleeve section and the edge of the embedded hole it contains is 0.125mm.

[0156] Specifically: when drilling through holes after secondary pressing, the hole is drilled using the aforementioned sleeve hole as a reference; after drilling, a visual inspection is performed:

[0157] The relative position of the wall of the through hole and the wall of the third buried hole is used to determine the alignment with the first sub-plate.

[0158] The relative position of the wall of the through hole and the wall of the fourth buried hole is used to determine the alignment with the second sub-plate.

[0159] The overall offset is determined by the concentricity offset between the center of the through hole and the inner edges of the first copper ring and the second copper ring.

[0160] If a misaligned hole is detected during visual inspection, the offset is fed back to the drilling system for subsequent expansion and contraction compensation adjustments during drilling. The first set of composite targets and the second set of composite targets each consist of two targets, respectively positioned at the four corner areas of the sub-board.

[0161] Example 1: A method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules, wherein the multilayer board has 16 layers.

[0162] I. Sub-board preparation: Two 8-layer sub-boards, L1-L8 and L9-L16, are prepared respectively. The sub-board edges are designed with the RVC layer offset detection strip and composite alignment target pattern: the composite alignment target includes the first alignment target FHI, the second alignment target FH2, the first verification target FH3 and the second verification target FH4.

[0163] The simplified process flow is as follows: Cutting board → Inner layer → Pressing and punching 1 → Inner layer AOI → Pressing 1 → Drilling 1 → [High temperature baking] → PTH / VCP1 (flash plating 0.2mil) → [Dry film for plating] → PTH / VCP2 → Film removal → [Resin plug film application] → [Laser opening] → Resin plug 1 → Film peeling → Ceramic brush → Dry film 1 → Positive film etching 1 → Pressing and punching → Mid-measure AOI 1 → [Brown film application] → Pressing → Film peeling → Drilling;

[0164] The innovative process is described below:

[0165] [High-Temperature Baking] After pressing the L1-L8 core boards and L9-L16 core boards together and completing drilling 1, perform high-temperature baking with the following parameters: 190℃ * 2 hours. Frame baking is also required to ensure even stress release.

[0166]

PTH / VCP1

[0167] [Through Hole Plating Dry Film] The through hole plating dry film is a single-sided film, applied only to layers L1 and L16. Exposure and development are performed on the via openings within the board to expose the vias, ensuring the exchange of copper plating solutions and the integrity of the copper thickness on the via walls. The via openings in layers L1 and L16 are 0.075mm larger than the via on each side. When placing the board horizontally along the dry film development line, ensure the dry film side is facing down, and avoid any dry film debris clogging the vias. Selective copper plating is then performed on the boards after through hole plating dry film plating using a pulse plating line. The nozzle flow on the plating surface is normal, while the flow on the dry film surface is reduced by 70%.

[0168]

Tree Plug Film

[0169] [Laser Drilling] A Mitsubishi CO2 laser drilling machine is used to laser-drill windows in the buried holes of the film. The window is 0.15mm larger than the hole on each side. Laser parameters are set as follows: power 5600W, frequency 100HZ, energy 6mJ. Hole enlargement processing is used. Laser drilling is a single-sided drilling method. The resin plugging hole has ink flowing down on the drilled side and ink flowing out on the back side, which can reduce resin accumulation on one side and reduce the number of high-cutting grinding cycles.

[0170]

Ceramic Grinding Brush

[0171]

Brown Coating Film

[0172] After AOI testing, an anti-browning film is applied, browning treatment is performed, and the browned sub-boards are paired and riveted together. A second pressing is then completed with the film on, and the copper-side protective release film is removed.

[0173] II. Fabrication of RVC layer offset detection strips for real-time quantitative detection of sub-board expansion and contraction

[0174] In order to obtain accurate dimensional data after the sub-board is processed, this application designs and manufactures a special RVC (Resin Via Capture) layer deviation detection strip on the edge of the sub-board (or other non-functional area).

[0175] 1. Outer layer graphic, i.e., outer layer monitoring structure design description:

[0176] 1.1. For example Figure 1 As shown, it includes 16 outer layer test point holes with a diameter of 0.25mm, including 4 green holes, 4 blue holes, and 6 black holes. The black holes are designed as test points.

[0177] 1.2. The width of the outer layer test pad, i.e. the diameter of the entire pad, is 10 mil;

[0178] 1.3. Five pad-to-copper distance options are available: 5mil, 5.5mil, 6.0mil, 6.5mil, and 7mil. Figure 1 As shown, the holes connecting the wires are all of the same specification;

[0179] 1.4. The hole-to-hole spacing is designed to be 20 mil, and the line width is designed to be 7 mil;

[0180] 1.5. Green holes are designed for conduction in layers L1-L8; blue holes are designed for conduction in layers L9-L16; black holes are designed for conduction in layers L1-L16. If a short circuit is found, the layer, diameter, and depth of the internal short circuit can be quickly and accurately identified.

[0181] 2. Inner layer graphics, i.e., inner layer monitoring structure design description:

[0182] 2.1. For example Figure 2 As shown, the different layers of the L2-L17 isolation layers are connected to external vias on different layers for conduction. If additional layers are needed, the connection layers can be densified to 28 layers.

[0183] 2.2. Inner layer isolation ring design reference Figure 2 ;

[0184] The inner layer isolation ring copper spacing is designed in five different sizes: 5mil, 5.5, 6.0, 6.5, and 7mil.

[0185] 2.3. The two sets of inner layer test point holes are arranged in an L-shape. By detecting the continuity between each pair of holes, the expansion and contraction offset of the board in both the X and Y directions can be quantitatively monitored to see if it exceeds the set threshold range. Figure 2 As shown, the three inner layer test holes (light blue pads) 5 mil away from the copper and the three inner layer test holes (purple pads) 7 mil away from the copper are all arranged in an L-shape.

[0186] This layer of the test strip contains a series of specially designed via networks and isolation patterns. For example, a measurement point with a diameter of 0.25mm (black via) is designed, and isolation rings with five different "via-to-copper" spacings ranging from 5mil to 7mil are set around it. Through specific design, vias of different colors (such as green, blue, and black vias) are respectively connected to specific networks in layers L1-L8, L9-L16, and the entire L1-L16 layer. The inner layer pattern designs independent connection networks and isolation rings for different layers (L2-L17), forming a multi-level, distributed sensor array.

[0187] Working principle and data acquisition:

[0188] This layer offset detection strip undergoes all secondary processing steps along with the main sub-board. After critical process nodes, such as resin plugging and final etching, high-precision optical measurement equipment, such as a CCD or a dedicated four-terminal fixture, is used to measure the absolute position coordinates of specific target points on the layer offset detection strip, such as the center of the black hole, or to measure the relative offset between different conductive networks. By comparing the measured values ​​with the original design coordinates, the macroscopic dimensional expansion and contraction of the sub-board in the X and Y directions (unit: mil or micrometer) can be accurately quantified, and the distribution of expansion and contraction across different layers can be analyzed. Its core function is as an embedded, online sensor, providing digital, real-time expansion and contraction status reports for each specific sub-board, rather than a simple pass / fail judgment.

[0189] III. Composite Alignment Targets for Data-Driven Alignment

[0190] To achieve accurate secondary pressing alignment based on measured data from the layer offset detection strip, this application designs two sets of dedicated composite alignment targets (FH1, FH2, FH3, FH4).

[0191] 1. The first set of composite targets (FH1, FH2) are single-sided buried via + through-hole composite targets, used for outer layer exposure alignment and target grabbing; FH1 is the first alignment target, and FH2 is the second alignment target;

[0192] Target description: such as Figure 3 As shown, the first set of composite targets (FH1, FH2) includes 12 buried holes on the periphery and 1 through hole in the center. During the outer layer image transfer exposure alignment after secondary lamination, the alignment measurement first captures the 12 buried holes on the periphery and the 1 through hole in the center, measuring the expansion and contraction at the four corners of the periphery. The expansion and contraction weight of the 1 through hole in the center is set to 60%-70%, and the weight of the 12 periphery holes is set to 30%-40%. Exposure is then performed with equal distribution of expansion and contraction.

[0193] After the secondary lamination, the drilling is also performed using these two sets of verification targets for CCD target measurement of expansion and contraction. Different weight values ​​are set based on the actual measured expansion and contraction data of the target holes in layers L1-L8 and L9-L16, and the expansion and contraction ratio is adjusted in real time. During the processing of the suspended layer, a 10mm drill bit is used to remove the PP in this area to prevent PP overflow from covering the target hole.

[0194] [Pre-drilling CCD identification and positioning, and adjustment for expansion and contraction compensation during the second drilling operation]

[0195] FH1: The 12 outermost first buried holes are buried holes in layers L1-L8, and the middle first through hole is a through hole in layers L1-L16; 6.5mm holes are drilled below the buried hole layers (layers L9-L16) to avoid the secondary pressure PP filling glue entering the hole, which would cause the target to block the hole and prevent the CCD camera module from capturing and recognizing the target.

[0196] FH2: The principle and design are the same as FH1, with layers L9-L16 as the target and layers L1-L8 as the drilling layers. Among them, the 12 outer second buried holes are buried holes in layers L9-L16, and the middle second through hole is a through hole in layers L1-L16.

[0197] Structure: Taking FH1 as an example, it has 12 first buried holes on the periphery (corresponding to buried holes in layers L1-L8) and one first through hole in the center (corresponding to through holes in layers L1-L16). 6.5mm large holes are pre-drilled at the corresponding positions in layers L9-L16 below the target to prevent PP glue from filling and blocking the holes during secondary lamination.

[0198] Function: After secondary lamination, during outer layer image transfer (exposure) or secondary drilling (CCD positioning), the machine vision system simultaneously captures the peripheral buried holes and the central through holes. The system incorporates the sub-board expansion and contraction data measured by the RVC Coupon into the alignment algorithm: assigning a higher weight (e.g., 70%) to the central through holes and a lower weight (30%) to the peripheral buried holes, and performing weighted averaging and compensation calculations on the coordinates of reference points from different sources, thereby achieving a comprehensive balance of the differentiated expansion and contraction of the two sub-boards and obtaining the optimal alignment center.

[0199] 2. The second set of composite targets (FH3, FH4) consists of buried holes in layers L1-L8 or buried holes in layers L9-L16, plus casing holes in layers L1 / L16, plus copper rings in layers L1 / L16—used for secondary drilling verification and visual judgment of hole deviation.

[0200] like Figure 4 As shown, FH3 is the first verification target, comprising the green via, the pink upper section of the via, and the sky-blue copper ring above it; FH4 is the second verification target, comprising the blue via, the pink lower section of the via, and the sky-blue copper ring below it.

[0201] Structure: This target integrates buried vias (green) in layers L1-L8, buried vias (blue) in layers L9-L16, vias (pink) in layers L1 / L16, and a copper ring (sky blue). The buried via diameter is 0.5mm, and after copper-plated resin plugging, it is approximately 0.45mm. A 0.2mm pink via is drilled in its center, and the distance between the via and the edge of the buried via on one side is designed to be 0.125mm.

[0202] Function: During the processing of the outer dummy layer of the sub-board after the first lamination, the hole rings corresponding to the target area of ​​the L1 / L16 layer are intentionally etched away, exposing the hole walls of the buried vias. When drilling through holes after the second lamination, the pink via is used as the reference. After drilling, the tangency of the pink through hole wall with the surrounding green / blue buried via wall can be directly visually inspected. If there is a significant offset, it indicates that there is a hole deviation, and the expansion and contraction compensation value of the drilling program can be adjusted immediately to achieve secondary real-time dynamic compensation.

[0203] System closed-loop workflow:

[0204] After the sub-board completes the optimized process flow, its final expansion and contraction data are measured using a layer offset detection strip.

[0205] The data is uploaded to the secondary pressing and alignment system and the drilling system.

[0206] The system dynamically adjusts the grasping logic and compensation coefficients of the composite targets FH1 / FH2 based on the data, and performs high-precision secondary pressing.

[0207] After pressing, drilling and post-drilling visual verification are performed using composite targets FH3 / FH4 to achieve closed-loop monitoring and fine-tuning of the process.

[0208] IV. Real-time detection

[0209] After all secondary processing of the sub-boards was completed, the coordinates of the designated measurement points on the layer offset detection strip were measured using an optical measuring instrument. The results showed that the expansion / contraction in the X direction of the L1-L8 sub-boards was +120 ppm, and in the Y direction it was -50 ppm. Similarly, the expansion / contraction in the X direction of the L9-L16 sub-boards was measured to be +80 ppm, and in the Y direction it was +30 ppm.

[0210] V. Data-driven secondary punching and riveting combined with secondary pressing processing

[0211] Input the expansion and contraction data of the two sub-plates into the secondary pressing 8-axis riveting alignment system.

[0212] After the 8-axis riveting alignment system loads the materials, the CCD vision system captures the FH3 target on sub-boards L1-L8 and the FH4 target on sub-boards L9-L16. The system algorithm calculates the standard capture coordinates of the targets in real time based on pre-inputted expansion and contraction data and then performs riveting. A secondary pressing is then performed on the two riveted sub-boards, with the pressing force, temperature, and time parameters set as usual.

[0213] VI. Post-compression verification and compensation

[0214] After lamination, secondary through holes are drilled in the FH3 / FH4 target areas. The operator visually inspects the area and finds that the gap between the pink sleeve hole wall and the surrounding buried hole walls is uniform, with no tangency or excessive deviation, indicating accurate alignment and no risk of hole misalignment. If a visually perceptible offset is found in any target area, the offset is fed back to the drilling system. This system then makes minor adjustments to the drilling coordinates of that area during the next drilling operation or in subsequent boards of this batch.

[0215] Results: The 16-layer memory module PCB produced using this method, after slicing analysis and electrical testing, showed an interlayer alignment deviation of less than 3mil, good alignment between vias and buried vias, and a defect rate of off-center vias reduced to below 3%, which is significantly better than traditional processes.

[0216] Example 2: Extended Applications of 28-Layer PCBs

[0217] The core principle of this method also applies to PCBs with 28 layers or more that require three or more laminations. The PCB can be viewed as being composed of multiple independently processed sub-modules (e.g., L1-L8, L9-L20, L21-L28) 8+12+8. Each sub-module is fabricated using the optimized process described above and integrates a layer misalignment detection strip. Before each lamination step between sub-modules, the layer misalignment detection strip data of the preceding module is measured to guide alignment compensation in the next lamination. The design of the composite target can be adaptively adjusted according to the actual layer stack structure. Through a layer-by-layer recursive "process control - real-time detection - dynamic compensation" closed loop, high-precision inter-layer alignment control is achieved throughout the entire process for ultra-high layer count PCBs.

[0218] It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this patent application shall be determined by the appended claims.

Claims

1. A method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules, characterized in that: Includes the following steps: Sub-board expansion and contraction control processing steps: After completing one pressing, the sub-board is sequentially drilled, baked at high temperature, flash plated, plated dry film, resin plug film, ceramic brush, and browning film. Real-time expansion and contraction data acquisition steps: When the above expansion and contraction control processing steps are completed and before the second pressing, the layer deviation detection strips pre-set in the non-functional area of ​​the sub-board are measured to obtain real-time expansion and contraction data that characterizes the actual size expansion and contraction state of the sub-board after processing. The data-driven secondary lamination alignment step involves inputting the real-time expansion and contraction data into the secondary lamination alignment system. Based on the real-time expansion and contraction data, the system dynamically adjusts the grasping compensation coefficient of the composite alignment target set on the sub-board, and performs subsequent processing on at least two sub-boards according to the compensated alignment reference to form a multilayer board. The subsequent processing includes at least one of riveting, secondary lamination, and drilling and outer layer exposure after secondary lamination.

2. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 1, characterized in that: The sub-plate expansion and contraction control processing steps include the following steps: Fabrication of sub-boards: Fabricate at least two sub-boards, each including inner layer circuitry; High-temperature baking: Drill holes in the sub-board and then bake at high temperature; Through-hole dry film: After the sub-board is baked at high temperature, a copper layer is flash plated, then through-hole dry film is applied, and electroplating is performed to thicken it; Resin plugging film: After removing the original film, apply a resin plugging protective film to the sub-board and perform laser drilling; Ceramic brush: After laser drilling, the sub-board is filled with resin, and after the film is removed, the sub-board is subjected to ceramic brushing. Browning film application: The outer layer circuit is fabricated on the daughterboard, an anti-browning film is applied, and then browning treatment is performed. Subsequent molding steps: Press at least two sub-boards after browning treatment together to form a complete multilayer board, and then peel off the film and drill holes.

3. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 2, characterized in that: It also includes a multilayer board pressing and forming step: pressing at least two sub-boards that have completed browning together to form a complete multilayer board, and then drilling holes after peeling off the film.

4. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 2, characterized in that: During the flash copper plating process, a thin copper layer with a thickness of 0.2±0.02mil is formed; the high-temperature baking requires frame baking, and the baking temperature is 160~200℃ and the time is 90~150min.

5. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 2, characterized in that: During the through-hole dry film process, through-hole dry film is attached to the outer layer of one side of the sub-board, and the dry film is exposed and developed to expose the buried holes that need to be electroplated. The window size formed after development is 0.075mm±0.01mm larger than the corresponding buried hole on one side. Then, copper is plated on the hole walls of the buried holes that are not covered by the dry film.

6. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 2, characterized in that: During the resin plugging process, a high-temperature resistant release film is applied to the outer layer of one side of the sub-board, and the film is opened only at the buried hole position where resin plugging is required before the resin plugging operation is carried out. A carbon dioxide laser drilling machine was used to perform laser windowing on the conductive through-holes of the film. The distance between the boundary of the solder mask window and the edge of the conductive through-hole was 0.15mm±0.02mm. The laser parameters were set as follows: power 5600W, frequency 100HZ, energy 6mj.

7. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 2, characterized in that: During the browning film application process, an anti-browning film is applied to the outer layer of one side of the sub-board. The anti-browning film includes a PI base film, a high-temperature resistant adhesive layer, and a release film that are applied sequentially. The thickness of the browning film is 65±10μm.

8. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 1, characterized in that: The layer offset detection strip includes an outer layer monitoring structure and an inner layer monitoring structure. The outer layer monitoring structure is disposed on the surface of the sub-board. The outer layer monitoring structure includes an outer layer test point hole, an outer layer test pad disposed around the outer layer test point hole, and an outer layer isolation ring surrounding the outer layer test pad. The inner layer monitoring structure is disposed on different inner layers of the sub-board. The inner layer monitoring structure includes inner layer test point holes, inner layer test pads disposed around the inner layer test point holes, and inner layer isolation rings disposed around the inner layer test pads. The inner layer isolation rings of each inner layer have a specific width, and the widths of at least two inner layer isolation rings are different from each other. The outer test pads of the outer monitoring structure are electrically connected to the corresponding inner test point holes of the inner layer through conductive structures. Using high-precision optical measurement equipment or a four-terminal fixture, coordinate measurements or continuity tests are performed on the outer layer test point holes and / or inner layer test point holes on the layer offset detection strip to obtain the actual dimensional expansion and contraction of the sub-board in the X and Y directions; the expansion and contraction is used as the real-time expansion and contraction data and input to the secondary pressing and alignment system.

9. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 8, characterized in that: The sub-board includes a first sub-board and a second sub-board; The inner monitoring structure includes: The first inner layer monitoring structure is located in the inner layer of the first sub-board; The second inner layer monitoring structure is located in the inner layer of the second sub-board; The third inner layer monitoring structure is installed through the first sub-board and the second sub-board; The outer test pads of the outer monitoring structure include: The first test pad group is electrically connected to the first inner layer monitoring structure only through a conductive structure; The second test pad group is electrically connected to the second inner layer monitoring structure only through a conductive structure; The third test pad group is electrically connected to the third inner layer monitoring structure via a conductive structure.

10. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 8, characterized in that: The inner layer monitoring structure includes L-shaped inner layer test point holes, used to monitor the offset in the X and Y directions by measuring electrical parameters in different directions.

11. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 8, characterized in that: The width of the inner isolation ring is 5 mil to 7 mil, and the width of the outer isolation ring is 5 mil to 7 mil.

12. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 8, characterized in that: The composite alignment target includes at least two sets of targets disposed on the sub-plate, namely: The first set of composite targets is used for riveting alignment before secondary pressing, alignment reference during the secondary pressing process, outer layer exposure alignment after secondary pressing, and / or alignment reference for drilling after secondary pressing. The second set of composite targets is used for borehole deviation verification and / or borehole compensation after secondary pressing and drilling.

13. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 12, characterized in that: The sub-plate includes a first sub-plate and a second sub-plate, and the first set of composite targets includes a first alignment target and a second alignment target; The first alignment target includes a plurality of first buried holes arranged on the periphery and a first through hole arranged in the center. The first buried holes are connected to the corresponding layer of the first sub-board, and the first through hole is connected to the entire layer. The second alignment target includes a plurality of second buried holes arranged on the periphery and a second through hole arranged in the center. The second buried holes are connected to the corresponding layer of the second sub-board, and the second through hole is connected to the entire layer. During alignment, the position data of the outer periphery holes and the central through hole of the first alignment target and / or the second alignment target are captured according to preset weights, and the expansion and contraction compensation coefficient is calculated accordingly.

14. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 13, characterized in that: The preset weights are dynamically allocated based on the real-time expansion and contraction data, including: The expansion and contraction states of the first sub-board and the second sub-board are determined based on the real-time expansion and contraction data. Based on the expansion and contraction state, the first through hole is assigned a higher weight than the first buried hole, and the second through hole is assigned a higher weight than the second buried hole; The optimal alignment center is calculated by weighted averaging of the position data of the first buried hole, the second buried hole, the first through hole, and the second through hole.

15. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 14, characterized in that: The corresponding layer below the first alignment target and / or the second alignment target is provided with a hollow area. The diameter of the hollow area is larger than the outline of the corresponding target, so as to prevent PP glue from filling and clogging the target during secondary pressing.

16. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 13, characterized in that: The second set of composite targets includes a first verification target and a second verification target; The first verification target is set on the first sub-board and includes: At least one third buried via is provided, which is connected to the corresponding layer of the first sub-board; A sleeve section is disposed inside the third buried hole, and the sleeve section penetrates the first sub-plate; And a first copper ring disposed on the outer surface of the first sub-board, the first copper ring surrounding the third buried hole; The second verification target is set on the second sub-board and includes: At least one fourth buried via, connecting to the corresponding layer of the second sub-board; A sleeve section is disposed inside the fourth buried hole, and the sleeve section penetrates the second sub-plate; And a second copper ring disposed on the outer surface of the second sub-board, the second copper ring surrounding the fourth buried hole; In this process, the sleeve section of the first verification target and the sleeve section of the second verification target are connected and conductive after secondary pressing, together forming a sleeve that penetrates the entire layer of the multilayer board.

17. The method for manufacturing a high-density buried via multilayer board suitable for AI server storage modules according to claim 16, characterized in that: The second set of composite targets is used to drill holes with the sleeve hole as a reference during drilling after secondary pressing. The relative positions of the through hole wall and the nested buried hole wall, as well as the relative positions of the sleeve hole wall and the corresponding copper ring, are visually or optically detected to determine whether there is a hole deviation. If a hole deviation exists, the offset is fed back to the drilling system for compensation and adjustment.

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