Fabrication process and semiconductor devices for ESD protection devices

Abstract

This application provides a fabrication process and semiconductor device for an ESD protection device. The process includes: providing a semiconductor substrate; performing a first ion implantation of the semiconductor substrate with a first conductivity type, implanting a first dose of a first impurity; performing a second ion implantation of the semiconductor substrate with a second conductivity type, implanting a second dose of a second impurity, the second impurity being a donor impurity or acceptor impurity opposite to the first impurity, the difference between the second dose and the first dose being configured to be equivalent to the net doping dose of the target dose implantation within a preset range; and annealing the semiconductor substrate after the two ion implantations to activate the implanted impurities. This application achieves low-concentration doping by controlling the difference between the two higher dose implantations, solving the problems of insufficient process window and poor equipment stability in low-dose implantation, improving process stability and device performance consistency, and reducing production costs.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a fabrication process and semiconductor device for an ESD protection device. Background Technology

[0002] In the semiconductor device manufacturing field, ESD (electrostatic discharge) protection devices are crucial for protecting integrated circuits from electrostatic damage. Existing ESD protection devices typically employ ion implantation to adjust the device's capacitance performance, specifically achieving low-concentration doping through a single low-dose ion implantation. However, in current technologies, low-dose implantation processes place extremely high demands on equipment stability. Conventional ion implantation equipment has insufficient process windows at low doses, making precise control of the implantation dose difficult, resulting in poor equipment stability, inability to meet mass production requirements, and poor compatibility with other conventional processes. This necessitates reliance on specialized IMP (injection-permeable) equipment, leading to increased production costs. Therefore, a technical solution to address these issues is urgently needed. Summary of the Invention

[0003] In view of the defects and deficiencies in the prior art described above, this application provides a fabrication process and semiconductor device for ESD protection devices, which achieves low-concentration doping by implanting two high-dose impurities of opposite conductivity types, thereby improving process stability and product consistency and reducing production costs.

[0004] In a first aspect, this application provides a fabrication process for an ESD protection device, comprising the following steps: providing a semiconductor substrate; performing a first ion implantation of the semiconductor substrate with a first conductivity type to implant a first impurity at a first dose; performing a second ion implantation of the semiconductor substrate with a second conductivity type to implant a second impurity at a second dose, wherein the second impurity is a donor impurity or acceptor impurity opposite to the first impurity, and the difference between the second dose and the first dose is configured to be equivalent to the net doping dose of the target dose implantation within a preset range; and annealing the semiconductor substrate after the two ion implantations to activate the implanted impurities.

[0005] The above technical solution uses two high-dose ion implantations and the difference between the two doses to precisely control the final net doping concentration. This avoids the problem of insufficient stability of conventional equipment when directly performing extremely low-dose implantation. It enables high-precision low-concentration doping using general-purpose equipment, improves process stability and device performance consistency, and reduces equipment dependence and cost.

[0006] In one embodiment, the first conductivity type is P-type, and the first impurity is an acceptor impurity, including one or more of boron, indium, and gallium; the second conductivity type is N-type, and the second impurity is a donor impurity, including one or more of phosphorus, arsenic, and antimony.

[0007] In one embodiment, the first conductivity type is N-type, and the first impurity is a donor impurity, including one or more of phosphorus, arsenic, and antimony; the second conductivity type is P-type, and the second impurity is an acceptor impurity, including one or more of boron, indium, and gallium.

[0008] In one implementation, both the first dose and the second dose are between 1×10⁻⁶. 12 atoms / cm 2 Up to 1×10 13 atoms / cm 2 The target dose is between 1×10 10 atoms / cm 2 Up to 5×10 11 atoms / cm 2 The preset range is ±5% of the target dose.

[0009] The above technical solution ensures that both injections are within the high stability range of conventional equipment by limiting the specific dosage range, and at the same time achieves precise control of extremely low target doses through differential measurement.

[0010] In one implementation, the implantation energies for the first and second ion implantations are both between 10 keV and 100 keV. Depending on the type of impurity and the required compensation effect, the energies for the two implantations can be the same or different.

[0011] The above technical solution maintains consistent injection energy, ensuring that the impurity distribution depths of the two injections basically overlap, which is beneficial for the accurate compensation and activation of impurities during subsequent annealing.

[0012] In one embodiment, after the first ion implantation and before the second ion implantation, the method further includes the step of forming an oxide layer on the surface of the semiconductor substrate, adjusting the actual doping dose of the second ion implantation by adjusting the thickness of the oxide layer, wherein the oxide layer thickness is adjusted from 1 nm to 10 nm, and the adjustment range of the second ion implantation dose is ±3% to ±8%.

[0013] The above technical solution adds oxide layer thickness adjustment as a fine-tuning method, further improving the flexibility and precision of controlling the final net doping concentration.

[0014] In one embodiment, the ratio of the first dose to the second dose is 1.01:1 to 2:1, and the activation rates of both the first impurity and the second impurity are not less than 95%.

[0015] As one implementation method, the preset range is ±3% to ±10% of the target dose, and the gradient control of different net doping concentrations is achieved by controlling the difference between the first dose and the second dose.

[0016] In one implementation, the time interval between the first ion implantation and the second ion implantation is 0.5 h to 2 h, during which the semiconductor substrate is protected by purging with inert gas.

[0017] The above technical solution uses inert gas protection to prevent the wafer surface from being contaminated or oxidized during the waiting process, thus ensuring the reliability of the process.

[0018] Secondly, this application also provides a semiconductor device, comprising: a semiconductor substrate; and a doped region formed in the semiconductor substrate, the doped region comprising a first impurity and a second impurity, wherein the first impurity and the second impurity have opposite conductivity types, and the implantation dose of the first impurity and the implantation dose of the second impurity are both between 1 × 10⁻⁶. 12 atoms / cm 2 Up to 1×10 13 atoms / cm 2 And the difference between the two is between 1×10 10 atoms / cm 2 Up to 5×10 11 atoms / cm 2 .

[0019] The above technical solution provides a semiconductor device with specific impurity distribution characteristics. This device, fabricated through the aforementioned process, exhibits excellent ESD protection performance and parameter consistency.

[0020] Compared with the prior art, the technical solution provided in this application has the following beneficial effects:

[0021] This application provides a fabrication process for ESD protection devices. Addressing the issues of insufficient low-dose ion implantation process windows and poor equipment stability leading to production limitations in existing technologies, this process compensates for these problems by first implanting a certain dose of a first conductivity type impurity, followed by a certain dose of a second conductivity type impurity. The difference in dose between the two implantations is used to precisely achieve the target low-dose net doping effect. This process transforms the difficult-to-control extremely low-dose implantation into easily controllable high-dose implantation difference control, significantly improving process stability and repeatability. It enables high-precision low-concentration doping on conventional general-purpose equipment, reducing reliance on specialized equipment and lowering production costs. Attached Figure Description

[0022] Figure 1 This is a diagram illustrating the fabrication steps of the ESD protection device provided in this application.

[0023] Figure 2 This is a schematic diagram of the fabrication process of the ESD protection device provided in this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in the specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application.

[0025] Example 1:

[0026] This embodiment provides a fabrication process for an ESD protection device, aiming to solve the problems of insufficient process window and poor equipment stability in the existing technology for low-dose ion implantation. For example... Figure 1 and Figure 2 As shown, the process specifically includes the following steps.

[0027] Step S100: Provide a semiconductor substrate.

[0028] Specifically, the semiconductor substrate, serving as the carrier for device fabrication, requires material selection based on the performance requirements of the final device. In this embodiment, the semiconductor substrate can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, or silicon-on-insulator (SOI) substrate, etc. The substrate's conductivity type can be either P-type or N-type, depending on the type of impurities subsequently implanted and the structural requirements of the final device. Furthermore, a substrate cleaning step is typically included, such as using the RCA standard cleaning process, to remove organic contaminants, particles, and native oxide layers from the surface, ensuring interface quality and process consistency for subsequent ion implantation.

[0029] Step S200: Perform a first ion implantation of a first conductivity type on the semiconductor substrate, implanting a first dose of a first impurity.

[0030] Specifically, the purpose of the first ion implantation is to introduce impurity atoms of a first conductivity type into the substrate. In this embodiment, the first conductivity type is P-type, and the first impurity is an acceptor impurity, specifically boron (B) is selected as the implanted impurity. In other embodiments, indium (In), gallium (Ga), or other acceptor impurities can also be used, or donor impurities such as phosphorus, arsenic, and antimony can be selected according to design requirements to form N-type doping.

[0031] The key to this step is that the initial injection dose is relatively large, and this dose falls within the high-precision control range of a conventional ion implantation machine. In this embodiment, the initial dose is set to 6.3 × 10⁻⁶. 12 atoms / cm 2 At this dose, the ion implantation equipment exhibits excellent beam stability, and the dose control system can accurately measure the dose with an error controlled within ±1%. In contrast, if a low dose is directly injected into the target, such as 3 × 10⁻⁶, the beam stability is significantly lower. 11 atoms / cm 2 Within this dose range, the beam current of the instrument fluctuates significantly, the measurement noise to signal ratio increases significantly, and the dose control error can reach ±10% or even higher.

[0032] Furthermore, the choice of implantation energy also affects the implantation quality. In this embodiment, the first implantation energy is set to 25 keV. This energy selection ensures that the projected range of the implanted impurities is within a depth range of approximately 80 nm to 100 nm below the substrate surface. Too high an implantation energy will result in excessively deep impurity distribution, increasing the difficulty of annealing activation; too low an implantation energy will cause impurities to concentrate too much on the surface, easily forming a surface enrichment layer, affecting subsequent oxide layer growth and device performance. The second implantation energy can be selected independently according to the type of impurity. For example, when the second implantation is of phosphorus, 78 keV can be used to achieve the required compensating depth distribution.

[0033] Step S300: Perform a second ion implantation of the second conductivity type on the semiconductor substrate, implanting a second dose of the second impurity.

[0034] The second impurity is either a donor or acceptor impurity, the opposite of the first impurity. For example, if the first impurity is p-type boron, then the second impurity is n-type phosphorus; and vice versa. The difference between the second and first doses is configured to be equivalent to the net doping dose implanted at the target dose within a preset range. The target dose is between 1 × 10⁻⁶. 11 atoms / cm 2 Up to 5×10 11 atoms / cm 2 The preset range is ±5% of the target dose.

[0035] In this embodiment, the second conductivity type is N-type, and the second impurity is a donor impurity, specifically phosphorus (P) is selected as the implanted impurity. The second dose is set to 6.0 × 10⁻⁶. 12 atoms / cm 2 The difference between the first and second doses is 3 × 10⁻⁶. 11 atoms / cm 2This difference is configured to be equivalent to the net doping dose implanted at the target dose. The preset range is ±5% of the target dose, i.e., in this embodiment, the target dose is 3 × 10⁻⁶. 11 atoms / cm 2 The actual net doping dose was controlled between (2.85 and 3.15) × 10⁻⁶. 11 Within the range of atoms / cm², this embodiment employs differential control. Through two high-dose injections, the final effective doping concentration is kept in the low concentration range, while the actual process concentration remains within the high-precision control range of the instrument. This significantly improves the stability and repeatability of the process, making it possible to achieve high-precision low-concentration doping on a general-purpose instrument.

[0036] In this embodiment, to achieve more precise control, the ratio of the first dose to the second dose is limited to 1.01:1 to 2:1, and the activation rates of both the first impurity and the second impurity are not less than 95%. For example, 1.35 × 10⁻⁶ can be used. 12 atoms / cm 2 Boron and 1.0 × 10 12 atoms / cm 2 The phosphorus composition was controlled at a ratio of 1.35:1, and the equivalent of 3×10⁻⁶ was achieved through post-annealing compensation. 11 The net doping effect is measured in atoms / cm². This ratio range ensures that the first impurity is always slightly higher in dosage than the second impurity, thus guaranteeing that the final net doping conductivity type is consistent with the design target. For example, if the target is P-type, the first impurity is P-type with a slightly higher dosage. Simultaneously, the preset range is ±3% to ±10% of the target dosage, allowing for gradient control of different net doping concentrations by adjusting the difference between the first and second dosages. This means that by fine-tuning the difference between two high-dose injections, a series of low-doped regions with different concentrations can be flexibly obtained without changing a large number of instrument parameter settings, thereby adapting to the differentiated requirements of different ESD protection devices for trigger and sustaining voltages.

[0037] Regarding the parameter settings for implantation energy, the implantation energies for both the first and second ion implantations in the technical solution provided in this embodiment are between 10 keV and 100 keV, specifically determined based on the type of impurity and the required compensation effect. For example, when the first impurity is boron (B) and the second impurity is phosphorus (P), adjusting the implantation energy allows for effective compensation distribution of the two impurities after annealing. It is understood that the ion implantation energy determines the projected range of impurity atoms in the semiconductor substrate. By appropriately selecting the energies for the two implantations (which can be the same or different), the depth matching of the impurity distribution can be controlled, thereby optimizing the compensation effect. For example, with parameter settings of 25 keV for the first impurity and 78 keV for the second impurity, the distribution depth of the two impurities in the substrate can be controlled by appropriately selecting the implantation energy. This allows donor and acceptor impurities to effectively compensate within the same depth range during annealing, thereby forming a uniform and precise net doped region and avoiding the negative impact of longitudinal concentration fluctuations on device performance.

[0038] In one implementation, after the first ion implantation and before the second ion implantation, the method further includes: forming an oxide layer on the surface of a semiconductor substrate, and adjusting the actual doping dose of the second ion implantation by adjusting the thickness of the oxide layer. The oxide layer can act as a physical barrier layer. When the ion beam passes through the oxide layer and enters the silicon substrate, it collides with atoms in the oxide layer and loses some energy, causing some ions to remain in the oxide layer and unable to enter the substrate to become effective dopant. In this embodiment, the oxide layer thickness is adjusted from 1 nm to 10 nm, and the adjustment range of the second ion implantation dose is ±3% to ±8%. Furthermore, for every 1 nm increase in oxide layer thickness, the actual doping dose of the second ion implantation decreases by 0.5% to 1%.

[0039] Compared to directly adjusting the beam current or implantation time of an ion implanter, minute fluctuations in equipment parameters are often difficult to control precisely, especially in the extremely low dose range. However, the thickness of the oxide layer can be precisely controlled at the atomic level through thermal oxidation or chemical vapor deposition processes, with an accuracy of 0.1 nm or even lower. Therefore, fine-tuning the actual implantation dose by changing the oxide layer thickness is essentially a more refined and stable adjustment method than simply adjusting the implantation equipment parameters. For example, if it is necessary to reduce the effective dose of the second implantation by 2%, it can be achieved by simply increasing the oxide layer thickness by approximately 2 nm to 4 nm. By combining the dose control of the equipment itself with oxide layer thickness control, the entire process can be controlled more precisely. It is understood that the oxide layer can be either a thermally oxidized layer or a chemically vapor-deposited oxide layer. Thermally oxidized layers have good density and low interface state density; chemically vapor-deposited oxide layers have the advantages of low deposition temperature and fast growth rate. Engineers can flexibly choose according to specific production line conditions.

[0040] In actual production line operations, the time interval between the first and second ion implantations is 0.5 to 2 hours, during which the semiconductor substrate is purged with inert gas for protection. This time interval exists because the ion source may need to be changed or the equipment parameters adjusted between the two implantations. During this period, purging the wafer surface with inert gases such as nitrogen or argon effectively prevents the exposed implantation area from adsorbing moisture or dust particles from the air, avoiding oxide layer defects or contamination during subsequent annealing, thus ensuring the cleanliness and reliability of the process.

[0041] Step S400: Anneal the semiconductor substrate that has undergone two ion implantations to activate the implanted impurities.

[0042] Specifically, ion implantation forcibly inserts impurity atoms into the crystal lattice, causing lattice damage. The implanted impurity atoms are not in substitutional positions and are not electrically active at this stage. Annealing repairs the lattice damage through high-temperature treatment and drives impurity atoms into substitutional positions, thereby releasing charge carriers. The annealing process can employ rapid thermal annealing (RTP), with temperatures ranging from 850°C to 1050°C and durations lasting several tens of seconds. During annealing, the first and second impurities, due to their opposite conductivity, undergo an electrical compensation effect, and the net carrier concentration of the final doped region is determined by the difference in their concentrations. Due to the high-precision control of the preceding implantation process, the performance consistency of the annealed device is significantly improved.

[0043] Following the second ion implantation and before annealing, a pre-baking process is performed on the semiconductor substrate. The pre-baking temperature is 200°C to 400°C, and the holding time is 5 to 15 minutes. This process removes moisture and residual impurities adsorbed during ion implantation. The pre-baking step effectively prevents moisture from entering the crystal lattice and forming defects during high-temperature annealing, further improving device reliability.

[0044] After annealing, the process includes surface cleaning of the semiconductor substrate to remove the oxide layer generated during annealing, followed by the sequential formation of the gate structure, dielectric layer, and electrode structure. Since the two high-dose implantation processes used in this embodiment are fully compatible with conventional ion implantation equipment, and the annealing process can utilize existing process parameters, subsequent processes can proceed smoothly with the two ion implantations and annealing treatments without requiring modifications to existing production lines. This effectively solves the problem of poor compatibility between existing IMP equipment and other processes, significantly reducing the mass production threshold and cost.

[0045] This embodiment utilizes the difference control between two high-dose injections to avoid the poor stage stability during low-dose injections, thus achieving the fabrication of a low-cost, high-stability ESD protection device.

[0046] Example 2:

[0047] This embodiment provides a semiconductor device obtained using the fabrication process described in Embodiment 1. Specifically, the semiconductor device includes a semiconductor substrate and a doped region formed within the semiconductor substrate. The doped region is the core area for achieving ESD protection; it is located inside the semiconductor substrate and is typically formed through ion implantation.

[0048] The semiconductor device provided in this embodiment contains a first impurity and a second impurity in the doped region, and the first impurity and the second impurity have opposite conductivity types. Specifically, if the first impurity is a P-type acceptor impurity, such as boron, indium, or gallium, then the second impurity is an N-type donor impurity, such as phosphorus, arsenic, or antimony; and vice versa. Unlike traditional single-type impurity doped regions, the doped region in this embodiment contains a large number of donor and acceptor impurity atoms. In terms of electrical performance, the electrons provided by the donor impurity and the holes provided by the acceptor impurity recombine and compensate for each other. Ultimately, the conductivity type and carrier concentration of the doped region are determined by the difference between the concentrations of the two impurities.

[0049] Since the injection doses of both the first and second impurities are at 1×10 12 Up to 1×10 13 In the high-dose range, even with minute statistical errors in the ion implantation process, the high implantation dose makes these errors negligible and easily controllable. When two high-dose impurities compensate for each other, their respective implantation errors largely cancel each other out. The resulting net doping concentration, or concentration difference, has extremely high accuracy and repeatability, thus enabling precise control of the doped region concentration in semiconductor devices within 1×10⁻⁶. 10 Up to 5×10 11 It achieves extremely low doping levels while maintaining extremely high batch-to-batch process stability. For ESD protection devices, precise control of the doping concentration directly determines the consistency of the device's trigger and sustaining voltages, thereby significantly improving the stability and reliability of ESD protection performance and solving the device performance fluctuation problem caused by low-dose implantation instability in existing technologies.

[0050] It should be understood that, although Figure 2 The diagram only schematically illustrates a doped region. However, in practical applications, semiconductor devices may also include other conventional components such as gate structures, dielectric layers, and electrode structures. These components are electrically connected to the doped region, together forming a complete ESD protection circuit. The doped region structural features emphasized in this embodiment can be widely applied to various semiconductor devices that require precise control of low doping concentrations, not limited to ESD protection devices, but also including other semiconductor structures with strict requirements for threshold voltage or capacitance performance.

[0051] In summary, the fabrication process of the ESD protection device provided in this application increases the implantation dose from the traditional low-dose range to the high-dose range, placing the process operation within the stable operating range of the ion implantation equipment. It is also fully compatible with existing production line equipment, eliminating the need for investment in special low-dose implantation equipment, effectively reducing equipment investment costs, and enhancing product market competitiveness. The reliability and yield of the ESD protection device fabricated using this embodiment are also effectively improved. Therefore, the technical solution of this application has high industrial applicability because it effectively overcomes the various shortcomings of the prior art.

[0052] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A fabrication process for an ESD protection device, characterized in that, Includes the following steps: Provide semiconductor substrates; The semiconductor substrate is subjected to a first ion implantation of a first conductivity type, and a first dose of a first impurity is implanted. The semiconductor substrate is subjected to a second ion implantation of a second conductivity type, and a second dose of a second impurity is implanted, wherein the second impurity is a donor impurity or acceptor impurity opposite to the first impurity, and the difference between the second dose and the first dose is configured to be equivalent to the net doping dose of the target dose implantation within a preset range. The semiconductor substrate, after undergoing two ion implantations, is annealed to activate the implanted impurities.

2. The fabrication process of the ESD protection device according to claim 1, characterized in that, The first conductivity type is P-type, and the first impurity is an acceptor impurity, including one or more of boron, indium, and gallium; The second conductivity type is N-type, and the second impurity is a donor impurity, including one or more of phosphorus, arsenic, and antimony.

3. The fabrication process of the ESD protection device according to claim 1, characterized in that, The first conductivity type is N-type, and the first impurity is a donor impurity, including one or more of phosphorus, arsenic, and antimony; The second conductivity type is P-type, and the second impurity is an acceptor impurity, including one or more of boron, indium, and gallium.

4. The fabrication process of the ESD protection device according to claim 1, characterized in that, Both the first dose and the second dose are between 1×10 12 atoms / cm 2 Up to 1×10 13 atoms / cm 2 The target dose is between 1×10 10 atoms / cm 2 Up to 5×10 11 atoms / cm 2 The preset range is ±5% of the target dose.

5. The fabrication process of the ESD protection device according to claim 1, characterized in that, The implantation energies for the first and second ion implantations were both between 10 keV and 100 keV, and the implantation energies for the two ion implantations were the same or different.

6. The fabrication process of the ESD protection device according to claim 1, characterized in that, The procedure, following the first ion implantation and before the second ion implantation, also includes the following steps: An oxide layer is formed on the surface of the semiconductor substrate. The actual doping dose of the second ion implantation is adjusted by adjusting the thickness of the oxide layer. The oxide layer thickness is adjusted from 1 nm to 10 nm, and the second ion implantation dose is adjusted by ±3% to ±8%.

7. The fabrication process of the ESD protection device according to claim 1, characterized in that, The ratio of the first dose to the second dose is 1.01:1 to 2:1, and the activation rates of both the first impurity and the second impurity are not less than 95%.

8. The fabrication process of the ESD protection device according to claim 1, characterized in that, The preset range is ±3% to ±10% of the target dose, and the gradient control of different net doping concentrations is achieved by controlling the difference between the first dose and the second dose.

9. The fabrication process of the ESD protection device according to claim 1, characterized in that, The time interval between the first and second ion implantations is 0.5 h to 2 h, during which the semiconductor substrate is protected by inert gas purging.

10. A semiconductor device, characterized in that, include: Semiconductor substrate; A doped region formed in the semiconductor substrate, the doped region comprising a first impurity and a second impurity, the first impurity and the second impurity having opposite conductivity types, and the implantation dose of both the first impurity and the second impurity being between 1 × 10⁻⁶. 12 atoms / cm 2 Up to 1×10 13 atoms / cm 2 And the difference between the two is between 1×10 10 atoms / cm 2 Up to 5×10 11 atoms / cm 2 .

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