A multi-issue CPU instruction stitching method

Abstract

The application discloses a multi-transmit CPU instruction splicing method, comprising: an early splicing step, used for splicing instructions according to PC information and Fetch Group information predicted by a branch prediction part and writing the Fetch Group information into a Fetch Group queue in a fetch stage; and a read Fetch Group queue and then optimize splicing timing through multiple continuous time periods; a speculation splicing step, used for performing instruction splicing processing on the Fetch Group information to obtain a branch prediction result in a branch prediction pipeline and a fetch pipeline parallel process; wherein branch prediction information is given in stages in the first N cycles of the branch prediction pipeline; and the fetch pipeline dynamically updates the Fetch Group information according to the branch prediction information. The application performs instruction splicing preparation according to branch prediction information in the fetch stage in advance, and significantly reduces time delay in a subsequent processing stage. According to the length and transmission bandwidth of the Fetch Group information, the application dynamically adjusts a data reading and splicing method in multiple continuous time periods, and maximizes utilization of resources.

Description

Technical Field

[0001] This invention relates to the field of CPU instruction splicing and fetching technology, specifically to a method for splicing multi-issue CPU instructions. Background Technology

[0002] In multi-issue systems, a single instruction fetch reads a fixed-length instruction (e.g., X bits). The length of a single instruction fetch is called a Fetch Group. Considering branch jumps, the effective bit width of a Fetch Group is often less than X. In multi-issue systems, the instruction fetch rate must be guaranteed because it affects the overall CPU issue bandwidth. Generally, when the issue bandwidth is Y, the width X of the Fetch Group must be greater than Y to ensure sufficient CPU bandwidth. This ensures that, over long-term operation, the fetch throughput exceeds the throughput of subsequent operations, thus guaranteeing CPU performance. When the effective bit width of a Fetch Group is less than Y, two Fetch Groups need to be concatenated to form an effective data set equal to Y. Specifically... Figure 1 As shown, assuming X = 2Y, in most cases, X can guarantee the throughput of Y. However, when X branches, the effective bit width provided by X is less than that of Y, resulting in data concatenation. Data concatenation is generally affected by two factors: whether the concatenation timing is convergent and the real-time performance of the concatenation.

[0003] Taking a 32B Fetch Group as an example, a single data concatenation may involve multiple scenarios, such as... Figure 2 As shown, a 32-byte block is divided into 16 half-words, denoted by HWx. Taking the concatenated data HW1 as an example, its data source is represented by the gray half-words in FetchGroup0 / 1, with as many as 31 possible scenarios. Data concatenation is generally accompanied by instruction boundary splitting. Considering both together, this becomes a timing bottleneck, thus affecting CPU performance. In multi-issue CPUs, branch prediction is a complex component, typically completed in stages. A complete branch prediction usually incurs 2-3 cycles of timing overhead. The CPU is a highly real-time system, and the effective bit width of a Fetch Group depends on the result of branch prediction. Waiting until branch prediction is complete before concatenation will impact system performance.

[0004] To address the aforementioned issues, this invention proposes a multi-issue CPU instruction concatenation method to maximize resource utilization and reduce time delays in subsequent processing stages. Summary of the Invention

[0005] In view of the above problems, the present invention provides a method for concatenating multiple-issue CPU instructions, comprising: The pre-assembly step is used to write the PC information and Fetch Group information predicted by the branch prediction part into the Fetch Group queue during the instruction fetching stage; and to optimize the assembly sequence through multiple consecutive time periods after reading the Fetch Group queue. The speculative splicing step is used to perform instruction splicing processing on Fetch Group information to obtain branch prediction results during the parallel process of branch prediction pipeline and fetch pipeline; wherein, branch prediction information is given in stages in the first N cycles of branch prediction pipeline; and the fetch pipeline dynamically updates the Fetch Group information based on the branch prediction information.

[0006] In one alternative approach, the plurality of consecutive time periods include clock phase F0, clock phase F1, and clock phase F2.

[0007] In an alternative embodiment, the method further includes the following steps in the pre-assembly step: During the F0 clock phase, based on the length of a Fetch Group message in the Fetch Group queue, it is determined in advance whether the length of the data to be sent this time meets the transmission bandwidth requirements; if not, the information of two Fetch Groups is read and the length of data that should be sent for each Fetch Group this time is calculated. During the F1 clock phase, the mapping relationship between each Fetch Group information and the final spliced ​​data is calculated when data is arranged. During the F2 clock phase, based on the information provided in the F0 and F1 clock phases, data is selected from the Fetch Group information and added to the final output data to complete the data splicing.

[0008] In an alternative embodiment, the method further includes the following steps in the speculative splicing step: During the F2 clock phase, if the branch prediction result is less than that during the F0 clock phase, less data has been read, and a flush operation is performed to reread the data; if the branch prediction result is shorter than that during the F0 clock phase, no flush operation is performed.

[0009] In an alternative approach, the method further includes: At clock F2, two or more Fetch Group messages are concatenated. When the process is saturated, they are back-pressurized to the front stage in a layer-by-layer back-pressurization manner.

[0010] In one alternative approach, the pre-joining step and the speculative joining step are adapted to a decoupled CPU instruction fetching system, wherein the pre-fetching stage of the CPU instruction fetching system includes a branch prediction section and an instruction fetching section.

[0011] In one alternative approach, the Fetch Group queue is a FIFO structure used to store PC information and Fetch Group information for branch prediction.

[0012] In an alternative approach, the step of determining in advance whether the length of the data to be transmitted meets the transmission bandwidth requirements based on the length of a FetchGroup information in the Fetch Group queue during the F0 clock phase further includes: If the length of the Fetch Group information is less than the minimum threshold required for transmission bandwidth, check if there is any subsequent Fetch Group information available for reading in the Fetch Group queue; if there is subsequent Fetch Group information, merge the current Fetch Group information with the next one or more Fetch Group information, and determine whether the transmission bandwidth requirement is met.

[0013] In an alternative approach, the method further includes, during the Flush reread operation: A specified range of Fetch Group information that needs to be reread is determined, including a start address and an end address; wherein, during the rereading process, the Fetch Group information is selected and spliced ​​using the updated information of the branch prediction results; Relocate and read Fetch Group information within a specified range from the Fetch Group queue.

[0014] In one alternative approach, the backpressure to the preceding stage in a layer-by-layer backpressure manner further includes: Monitor the load information at each level in the Fetch Group information splicing, including the utilization rate of processing units, data cache, and bus resources; When a certain level reaches or exceeds the preset load threshold, a reverse pressure signal is sent to the next higher level, instructing it to reduce the data transmission rate or pause transmission. After receiving the reverse pressure signal, the upstream unit dynamically adjusts its output rate according to the current working status and queue situation to alleviate the load pressure on the downstream.

[0015] According to the solution provided by the present invention, the method includes: a pre-assembly step, used to write PC information and Fetch Group information predicted by the branch prediction part into the Fetch Group queue during the instruction fetching stage; and optimizing the assembly timing through multiple consecutive time periods after reading the Fetch Group queue; a speculative assembly step, used to perform instruction assembly processing on the Fetch Group information to obtain the branch prediction result during the parallel process of the branch prediction pipeline and the instruction fetching pipeline; wherein, the branch prediction information is given in stages in the first N cycles of the branch prediction pipeline; the instruction fetching pipeline dynamically updates the Fetch Group information according to the branch prediction information. The present invention prepares for instruction assembly in advance based on the branch prediction information during the instruction fetching stage, significantly reducing the time delay in subsequent processing stages. It dynamically adjusts the data reading and assembly methods according to the length of the Fetch Group information and the transmission bandwidth within multiple consecutive time periods, maximizing resource utilization.

[0016] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0017] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This illustrates a data splicing diagram in the prior art; Figure 2 A schematic diagram of splicing timing in the prior art is shown; Figure 3 A flowchart illustrating the multi-issue CPU instruction splicing method according to an embodiment of the present invention is shown; Figure 4 A schematic diagram of pre-assembly according to an embodiment of the present invention is shown; Figure 5 A schematic diagram of a speculative splicing method according to an embodiment of the present invention is shown; Figure 6 A schematic diagram of the back pressure in an embodiment of the present invention is shown. Detailed Implementation

[0018] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0019] Figure 3 A flowchart illustrating a multi-issue CPU instruction concatenation method according to an embodiment of the present invention is shown. Specifically, as... Figure 3 As shown, it includes the following steps: Step S101, the pre-assembly step, is used to write the PC information and Fetch Group information predicted by the branch prediction part into the Fetch Group queue during the instruction fetching stage; and to optimize the assembly timing through multiple consecutive time periods after reading the Fetch Group queue.

[0020] In this embodiment, instruction splicing preparation based on branch prediction information during the instruction fetch stage can reduce time delays in subsequent processing stages, thereby improving instruction processing efficiency. The pre-sponsoring step can more effectively utilize the Fetch Group queue, avoiding resource idleness and waste.

[0021] In this embodiment, multiple consecutive time periods include the F0 clock phase, the F1 clock phase, and the F2 clock phase. In the pre-assembly step, during the F0 clock phase, based on the length of a Fetch Group message in the Fetch Group queue, it is determined whether the length of the data to be sent meets the transmission bandwidth requirements. If not, two Fetch Group messages are read, and the data length that should be transmitted for each Fetch Group is calculated. During the F1 clock phase, the mapping relationship between each Fetch Group message and the final assembled data is calculated during data arrangement. During the F2 clock phase, based on the information provided in the F0 and F1 clock phases, data is selected from the Fetch Group messages and added to the final output data to complete the data assembly.

[0022] like Figure 4 As shown, for a decoupled architecture, the CPU's front-end instruction fetching is generally divided into two main parts: branch prediction and instruction fetching. Branch prediction is used to obtain pointers for each fetch group. The instruction fetching part fetches valid instruction data based on the program counter (PC) and sends it to the CPU's decoder for further decoding. The instruction fetching part includes the following steps: Step 1: Write the PC information predicted by the branch prediction part and a Fetch Group length into the Fetch Group Queue.

[0023] Step two: After obtaining the Fetch Group Queue data, the fetch section begins reading the Queue, obtains the FetchGroup information, and starts working. This work is divided into three time periods, F0, F1, and F2, which are three clock cycles.

[0024] Step 3: At F0, based on the length information of a Fetch Group in the Fetch Group Queue, pre-calculate whether the length of the data to be sent this time meets the requirement of Y. If not, read two Fetch Groups and calculate the data length that should be sent by each Fetch Group this time, and simultaneously read the Data RAM.

[0025] Step four: At F1, the data in Data RAM has been obtained, and data arrangement begins. The mapping relationship between each Fetch Group and the final assembled data is calculated to obtain the final assembled data, where the selection information for each part of the data is from which part of the Fetch Group.

[0026] Step 5: At F2, data is selected from the Fetch Group based on the information provided by the previous step and added to the final output data to complete the data splicing. The splicing and selection logic is distributed to the F0 and F1 levels, which optimizes the timing.

[0027] In an alternative approach, the step of determining in advance whether the length of the data to be transmitted meets the transmission bandwidth requirements based on the length of a FetchGroup information in the Fetch Group queue during the F0 clock phase further includes: If the length of the Fetch Group information is less than the minimum threshold required for transmission bandwidth, check if there is any subsequent Fetch Group information available for reading in the Fetch Group queue; if there is subsequent Fetch Group information, merge the current Fetch Group information with the next one or more Fetch Group information, and determine whether the transmission bandwidth requirement is met.

[0028] In this embodiment, merging Fetch Groups can more effectively utilize transmit bandwidth, especially when processing small instruction sets or short branches, avoiding bandwidth waste. If subsequent Fetch Group information exists, the current Fetch Group information is merged with the next one or more Fetch Group information according to priority rules. The length of the merged data block is checked to ensure that the transmit bandwidth requirement is met. If it still does not meet the requirement, more Fetch Group information is checked and merged until the requirement is met.

[0029] Step S102, the speculative splicing step, is used to perform instruction splicing processing on the FetchGroup information to obtain the branch prediction result during the parallel process of branch prediction pipeline and instruction fetch pipeline; wherein, the branch prediction information is given in stages in the first N cycles of the branch prediction pipeline; the instruction fetch pipeline dynamically updates the Fetch Group information according to the branch prediction information.

[0030] In this embodiment, by processing the branch prediction pipeline and the instruction fetch pipeline in parallel, the branch prediction results are obtained in advance, thereby avoiding pipeline stalls and delays and improving the overall execution efficiency of the processor.

[0031] Specifically, such as Figure 5 As shown, in the first N cycles of the branch prediction pipeline, branch prediction information is provided in stages. This information includes the direction and target address of the branch instruction. Upon receiving the branch prediction information, the fetch pipeline dynamically updates the fetch group information. The fetch group information refers to a set of instructions fetched from the instruction cache (I-Cache) that will be executed in subsequent pipeline stages. If the branch prediction result indicates a jump is needed, the fetch pipeline updates the fetch group information; otherwise, sequential fetching continues. In the speculative concatenation step, the results of the parallel processing of the branch prediction pipeline and the fetch pipeline are concatenated, integrating the branch prediction information with the fetch group information to form a complete instruction flow.

[0032] Branch prediction for the same Fetch Group is divided into multiple stages. Generally, branch prediction is divided into several stages, each providing branch prediction information. For example, Cycle 0 provides preliminary branch prediction information, which is mostly correct, but it is also possible that the prediction result is incorrect. In Cycle 1, another branch prediction result is provided, which may be consistent with Cycle 0 or may overturn the result of Cycle 0. The complete branch prediction process consists of 3 cycles, from Cycle 0 to Cycle 2, and the prediction information may be continuously updated.

[0033] In an alternative embodiment, the method further includes the following steps in the speculative splicing step: During the F2 clock phase, if the branch prediction result is less than that during the F0 clock phase, less data has been read, and a Flush operation is performed to reread the data; if the branch prediction result is shorter than that during the F0 clock phase, no Flush operation is performed.

[0034] In this embodiment, the finger fetching pipeline is also running during the branch prediction pipeline, and the two pipelines operate in parallel. Therefore, the Fetch Group length information obtained by the finger fetching pipeline may be constantly updated. The Fetch Group length information obtained at F0 may be refreshed at F1 / F2. During the finger fetching pipeline processing of the Fetch Group, the branch prediction information provided by the branch pipeline may also be constantly updated. If an incorrect branch prediction result is used when concatenating data at F0 level, and the prediction result is found to be problematic at F2 level, it is handled in two ways: Figure 5 As shown, if the final result of the branch prediction is longer than F0, and F0 has read less data, then a flush must be performed to reread the data, which will incur performance overhead. If the final result of the branch prediction is shorter than F0, then a flush is not necessary because the data has already been read.

[0035] In an alternative approach, the method further includes: At clock F2, two or more Fetch Group messages are concatenated. When the process is saturated, they are back-pressurized to the front stage in a layer-by-layer back-pressurization manner.

[0036] In this embodiment, a flush occurs if a prediction error occurs, resulting in overhead. Considering timing and complexity, a maximum of two Fetch Groups can be concatenated. An alternative approach is to perform data concatenation at level F2, because accurate branch prediction information is available at this stage, allowing for direct concatenation of the Fetch Group data based on the actual situation. The advantage is reduced flush overhead caused by prediction errors, and the concatenation is performed entirely based on the latest valid data. Figure 6 As shown, F0 will always read at maximum efficiency, while F2 will combine two or more Fetch Group data according to the actual situation. When the process is saturated, it will backpressure to the front stage in a layer-by-layer manner to ensure greater bandwidth.

[0037] In one alternative approach, the pre-joining step and the speculative joining step are adapted to a decoupled CPU instruction fetching system, wherein the pre-fetching stage of the CPU instruction fetching system includes a branch prediction section and an instruction fetching section.

[0038] In this embodiment, the CPU instruction fetch system with a decoupled structure achieves a significant performance improvement in scalar operations by separating the instruction fetching and execution processes.

[0039] In one alternative approach, the Fetch Group queue is a FIFO (First-In-First-Out) structure used to store PC information and Fetch Group information for branch prediction.

[0040] In this embodiment, the FIFO queue avoids data races and chaos, and in branch prediction, it helps ensure that the predicted PC information matches the actual instruction execution order. By storing the predicted PC information and Fetch Group information in the FIFO queue, the branch prediction part can obtain the above information more quickly.

[0041] In an alternative approach, the method further includes, during the Flush reread operation: A specified range of Fetch Group information that needs to be reread is determined, including a start address and an end address; wherein, during the rereading process, the Fetch Group information is selected and spliced ​​using the updated information of the branch prediction results; Relocate and read Fetch Group information within a specified range from the Fetch Group queue.

[0042] In this embodiment, by relocating and reading the Fetch Group information within a specified range, the CPU can recover to the correct execution state more quickly, thereby improving the program's execution efficiency.

[0043] Specifically, when a Flush operation needs to be performed, the specified range of Fetch Group information that needs to be reread is determined based on the current execution status and branch prediction results. This range is used to identify the position of the instruction sequence that needs to be reread in the Fetch Group queue.

[0044] After performing the Flush operation, the branch prediction information is updated based on the latest execution results and feedback information to guide the selection and splicing optimization of subsequent Fetch Group information.

[0045] The Fetch Group information within a specified range is selected and optimized based on updated branch prediction information. For example, the remaining valid instruction sequences are filtered out, and the instructions to be executed are sorted and adjusted according to the prediction results.

[0046] Based on the selected optimization, the information of Fetch Groups within a specified range is spliced ​​and optimized. For example, multiple small Fetch Groups are merged into a larger Fetch Group to reduce the number of fetches and improve fetch efficiency.

[0047] Based on the optimized Fetch Group information, the system repositions itself to the starting position of the specified range in the Fetch Group queue and reads the corresponding Fetch Group information to pass to the execution part for subsequent processing.

[0048] In one alternative approach, the backpressure to the preceding stage in a layer-by-layer backpressure manner further includes: Monitor the load information at each level in the Fetch Group information splicing, including the utilization rate of processing units, data cache, and bus resources; When a certain level reaches or exceeds the preset load threshold, a reverse pressure signal is sent to the next higher level, instructing it to reduce the data transmission rate or pause transmission. After receiving the reverse pressure signal, the upstream unit dynamically adjusts its output rate according to the current working status and queue situation to alleviate the load pressure on the downstream.

[0049] In this embodiment, when a certain level reaches or exceeds a preset load threshold, it can promptly send a backpressure signal to the next higher level, instructing it to reduce the data transmission rate or suspend transmission, thereby effectively preventing data congestion. This layered backpressure mechanism enables more rational allocation and utilization of resources, avoiding resource waste.

[0050] According to the solution provided by the present invention, the method includes: a pre-assembly step, used to write PC information and Fetch Group information predicted by the branch prediction part into the Fetch Group queue during the instruction fetching stage; and optimizing the assembly timing through multiple consecutive time periods after reading the Fetch Group queue; a speculative assembly step, used to perform instruction assembly processing on the Fetch Group information to obtain the branch prediction result during the parallel process of the branch prediction pipeline and the instruction fetching pipeline; wherein, the branch prediction information is given in stages in the first N cycles of the branch prediction pipeline; the instruction fetching pipeline dynamically updates the Fetch Group information according to the branch prediction information. The present invention prepares for instruction assembly in advance based on the branch prediction information during the instruction fetching stage, significantly reducing the time delay in subsequent processing stages. It dynamically adjusts the data reading and assembly methods according to the length of the Fetch Group information and the transmission bandwidth within multiple consecutive time periods, maximizing resource utilization.

[0051] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination of all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed can be employed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose. Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims listing several devices, several of these devices may be embodied by the same hardware item. Unless otherwise specified, the steps in the above embodiments should not be construed as limiting the order of execution.

Claims

1. A method of splicing multiple-issue CPU instructions, the method comprising: include: The pre-assembly step is used to write the PC information and Fetch Group information predicted by the branch prediction part into the Fetch Group queue during the instruction fetching stage; and to optimize the assembly sequence through multiple consecutive time periods after reading the Fetch Group queue. The speculative splicing step is used to perform instruction splicing processing on Fetch Group information to obtain branch prediction results during the parallel process of branch prediction pipeline and fetch pipeline; wherein, branch prediction information is given in stages in the first N cycles of branch prediction pipeline; and the fetch pipeline dynamically updates the Fetch Group information based on the branch prediction information.

2. The multi-issue CPU instruction stitching method of claim 1, wherein, The multiple consecutive time periods include the F0 clock phase, the F1 clock phase, and the F2 clock phase.

3. The multi-issue CPU instruction stitching method of claim 2, wherein, In the pre-assembly step, the method further includes: During the F0 clock phase, based on the length of a Fetch Group message in the Fetch Group queue, it is determined in advance whether the length of the data to be sent this time meets the transmission bandwidth requirements; if not, the information of two Fetch Groups is read and the length of data that should be sent for each Fetch Group this time is calculated. During the F1 clock phase, the mapping relationship between each Fetch Group information and the final spliced ​​data is calculated when data is arranged. During the F2 clock phase, based on the information provided in the F0 and F1 clock phases, data is selected from the Fetch Group information and added to the final output data to complete the data splicing.

4. The multi-issue CPU instruction stitching method of claim 2, wherein, In the speculative splicing step, the method further includes: During the F2 clock phase, if the branch prediction result is less than that during the F0 clock phase, less data has been read, and a flush operation is performed to reread the data; if the branch prediction result is shorter than that during the F0 clock phase, no flush operation is performed.

5. The multi-issue CPU instruction stitching method of claim 3, wherein, The method further includes: At clock F2, two or more Fetch Group messages are concatenated. When the process is saturated, they are back-pressurized to the front stage in a layer-by-layer back-pressurization manner.

6. The multi-issue CPU instruction stitching method of claim 2, wherein, The pre-assembly step and the speculative assembly step are suitable for CPU instruction fetching systems with decoupled architectures, wherein the pre-fetching stage of the CPU instruction fetching system includes a branch prediction part and an instruction fetching part.

7. The multi-issue CPU instruction stitching method of claim 2, wherein, The Fetch Group queue is a FIFO structure used to store PC information and Fetch Group information for the branch prediction part.

8. The multi-issue CPU instruction stitching method of claim 3, wherein, The step of determining in advance whether the length of the data to be sent meets the transmission bandwidth requirements based on the length of a Fetch Group message in the Fetch Group queue during the F0 clock phase further includes: If the length of the Fetch Group information is less than the minimum threshold required for transmission bandwidth, check if there is any subsequent Fetch Group information available for reading in the Fetch Group queue; if there is subsequent Fetch Group information, merge the current Fetch Group information with the next one or more Fetch Group information, and determine whether the transmission bandwidth requirement is met.

9. The multi-issue CPU instruction stitching method of claim 4, wherein, When performing a flush reread operation, the method further includes: A specified range of Fetch Group information that needs to be reread is determined, including a start address and an end address; wherein, during the rereading process, the Fetch Group information is selected and spliced ​​using the updated information of the branch prediction results; Relocate and read Fetch Group information within a specified range from the Fetch Group queue.

10. The multi-issue CPU instruction splicing method according to claim 5, characterized in that, The step of applying reverse pressure to the preceding stage in a layer-by-layer reverse pressure manner further includes: Monitor the load information at each level in the Fetch Group information splicing, including the utilization rate of processing units, data cache, and bus resources; When a certain level reaches or exceeds the preset load threshold, a reverse pressure signal is sent to the next higher level, instructing it to reduce the data transmission rate or pause transmission. After receiving the reverse pressure signal, the upstream unit dynamically adjusts its output rate according to the current working status and queue situation to alleviate the load pressure on the downstream.

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