A system on chip, electronic device and vehicle

Abstract

This application provides a system-on-a-chip (SoC), an electronic device, and a vehicle, relating to the field of automotive electronic control technology. The SoC includes: a main processor module containing multiple processor cores; at least one digital signal processor (DSP) module connected to the main processor module; and at least one neural network processor (NN) module connected to both the main processor module and the DSP module. At least one first processor core in the main processor module allocates tasks to be processed to at least one of the other processor cores, the DSP module, or the NN module for execution. The DSP module, the NN module, and the main processor module interact with each other via a shared memory area. This application achieves precise matching of computing power for general control, signal processing, and artificial intelligence inference tasks through a heterogeneous multi-core architecture and a dynamic allocation mechanism based on task characteristics, thereby improving processing performance, energy efficiency, and functional safety levels.

Description

Technical Field

[0001] This application relates to the field of automotive electronic control technology, specifically to a system-on-a-chip, electronic equipment, and vehicle. Background Technology

[0002] As the level of automotive intelligence continues to improve, higher demands are placed on the computing power, energy efficiency, and real-time performance of vehicle control systems. In scenarios such as advanced driver assistance systems and power domain control, it is necessary to simultaneously handle complex radar signal preprocessing, AI-based target recognition and motion prediction algorithms, and highly reliable real-time control tasks.

[0003] In related technologies, various chip architecture solutions exist to address different task requirements. For example, multi-core digital signal processor architectures are used to process radar signals, or general-purpose processors are combined with software algorithms to perform control tasks. However, when facing application scenarios that require the integration of signal processing, artificial intelligence inference, and high real-time control tasks, these solutions often face technical challenges such as unreasonable allocation of computing power, inefficiency due to frequent data transfer between different processing units, and difficulty in guaranteeing the real-time performance of critical tasks.

[0004] Specifically, in collaborative scenarios involving radar signal processing and AI inference, the data interaction efficiency between the signal preprocessing unit and the AI ​​inference unit is often low, and frequent data transfer results in significant energy efficiency losses. In scenarios such as motor control, separating sensor data processing and the execution of advanced control algorithms into different processing units introduces substantial response latency. Furthermore, existing solutions lack sufficient flexibility in task scheduling and resource allocation among multi-core processors, making it difficult to meet the stringent functional safety and real-time requirements of complex automotive applications. Summary of the Invention

[0005] In view of the above problems, embodiments of this application provide a system-on-a-chip, an electronic device, and a vehicle to solve the above technical problems.

[0006] In a first aspect, embodiments of this application provide a system-on-a-chip (SoC) including a main processor module comprising multiple processor cores; at least one digital signal processor (DSP) module connected to the main processor module; and at least one neural network processor (NN) module connected to the main processor module and the at least one DSP module. The at least one first processor core in the main processor module is configured to: allocate tasks to be processed to at least one of the other processor cores, the DSP module, or the NN module for execution. The DSP module, the NN module, and the main processor module interact via a shared storage area, enabling on-demand offloading and precise matching of general control tasks, signal processing tasks, and artificial intelligence inference tasks among heterogeneous computing units. This avoids computational bottlenecks and resource idleness caused by a single processor core handling mixed loads. Simultaneously, establishing direct data interaction paths between modules through the shared storage area eliminates redundant copying and cache consistency maintenance overhead during cross-core data transfer, significantly reducing communication latency and system power consumption during task collaboration. This achieves efficient coupling and dynamic adaptation of heterogeneous computing power, improving processing capabilities, energy efficiency, and response determinism in complex real-time application scenarios.

[0007] Secondly, embodiments of this application also provide an electronic device, including the above-described system-on-a-chip.

[0008] Thirdly, embodiments of this application also provide a vehicle, including the above-described system-on-a-chip and / or the above-described electronic equipment.

[0009] The system-on-a-chip, electronic device, and vehicle provided in this application's embodiments, by configuring the main processor module to include multiple processor cores and dynamically allocating tasks to be processed by at least one first processor core, offload tasks suitable for execution by a digital signal processor and tasks suitable for execution by a neural network processor to corresponding dedicated acceleration modules, and enabling direct data interaction between the digital signal processor module, the neural network processor module, and the main processor module through a shared storage area, achieves refined matching and collaborative work of heterogeneous computing resources at the chip architecture level. General control tasks, signal processing tasks, and artificial intelligence inference tasks are carried out by their respective most proficient computing units, avoiding computing power mismatch and resource contention caused by a single general-purpose processor handling mixed loads. The shared storage area eliminates redundant copying and cache consistency maintenance overhead during data transfer between modules, minimizing data interaction latency and power consumption loss. The overall architecture achieves optimization of computing power utilization, data interaction efficiency, and system energy efficiency ratio.

[0010] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This paper shows a schematic diagram of the system-on-a-chip provided in an embodiment of this application; Figure 2 This paper illustrates another schematic diagram of the system-on-a-chip provided in an embodiment of this application. Figure 3 This paper illustrates a topology diagram of the module connections of a system-on-a-chip provided in an embodiment of this application. Figure 4 This illustration shows another topology diagram of the module connection of the system-on-a-chip provided in the embodiments of this application; Figure 5 This illustration shows another topology diagram of the module interconnection of the system-on-a-chip provided in the embodiments of this application; Figure 6 This illustration shows yet another topology diagram of the module interconnection of the system-on-a-chip provided in the embodiments of this application; Figure 7 This paper illustrates another schematic diagram of the system-on-a-chip provided in an embodiment of this application. Figure 8 A schematic diagram of the principle framework of the processor core provided in the embodiments of this application is shown; Figure 9 This illustrates yet another schematic diagram of the system-on-a-chip provided in an embodiment of this application; Figure 10 This paper shows a schematic diagram of the automotive radar controller on-chip system provided in an embodiment of this application; Figure 11 This paper illustrates a schematic diagram of the principle framework for processing frequency modulated continuous wave (FMCW) signals transmitted by a radar sensor in an on-chip system of an automotive radar controller provided in an embodiment of this application. Figure 12 This paper shows a schematic diagram of the principle framework of the automotive motor vector controller on-chip system provided in an embodiment of this application; Figure 13 A schematic diagram of the principle framework of the electronic device provided in the embodiments of this application is shown; Figure 14 A schematic diagram of the principle framework of the vehicle provided in the embodiment of this application is shown. Detailed Implementation

[0013] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0014] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0015] In the embodiments of this application, "at least one" refers to one or more; "multiple" refers to two or more. In the description of this application, the terms "first," "second," "third," etc., are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance, nor should they be construed as indicating or implying order.

[0016] References such as “one embodiment” or “some embodiments” as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the terms “comprising,” “including,” “having,” and variations thereof, as used in this specification, mean “including, but not limited to,” unless otherwise specifically emphasized.

[0017] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three kinds of relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0018] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0019] The system-on-a-chip (SoC) provided in this application is a heterogeneous multi-core chip that can be applied to the electronic and electrical architecture of intelligent vehicles, particularly as the core computing unit of a domain controller. In this application scenario, the chip is used to receive and process data from various vehicle sensors and execute corresponding control commands. Specifically, intermediate frequency or digital signals from radar sensors, current and position sensor signals from the motor control system, and control commands and status information received through the vehicle bus are input to the chip. The main processor module inside the chip is responsible for task scheduling, system management, and real-time control; the digital signal processor module is responsible for performing preprocessing such as pulse compression and filtering on the input raw radar signals, and performing operations such as coordinate transformation on the motor control signals; the neural network processor module is responsible for performing target recognition and classification on the preprocessed radar data, or performing artificial intelligence reasoning tasks such as state prediction and fault diagnosis on the motor system. The processed results, such as the identified target information, generated control parameters, or prediction results, are integrated by the main processor module and output through the corresponding communication interface for subsequent functions such as vehicle decision-making, chassis control, and human-machine interaction. Optionally, the controller containing the system-on-a-chip can be specifically applied to automotive radar controllers, automotive motor controllers, or domain controllers that integrate multiple functions.

[0020] This application provides an on-chip system, such as... Figure 1 As shown, the system-on-a-chip 100 includes a main processor module 10, at least one digital signal processor (DSP) module 20, and at least one neural network processing unit (NPU) module 30. At least one DSP module 20 is connected to the main processor module 10, and at least one NPU module 30 is connected to both the main processor module 10 and the at least one DSP module 20. The main processor module 10 includes multiple processor cores 101, and at least one first processor core 101 in the main processor module 10 is configured to distribute tasks to be processed to at least one of the other processor cores 101, the DSP module 20, or the NPU module 30 for execution. The DSP module 20, the NPU module 30, and the main processor module 10 interact with each other via a shared memory area 40.

[0021] The main processor module 10 is used to perform overall system control and task scheduling. In one specific embodiment, the multiple processor cores 101 are homogeneous processor cores, such as processor cores using the ARM Cortex-M42 series or RISC-V architecture. Each processor core 101 has an independent instruction execution pipeline and supports virtualization technology to achieve multi-task concurrent processing. Each processor core 101 can independently run a real-time operating system or bare-metal program and is interconnected with other on-chip modules through an on-chip bus.

[0022] At least one first processor core in the main processor module 10 (e.g. Figure 1 The first processor core 101 (CPU0) is configured to perform task scheduling. After the chip powers on, this first processor core 101 is responsible for system initialization, resource management, and dynamic allocation of tasks to be processed. Specifically, the first processor core 101 runs a task allocation and scheduling program, which allocates tasks to be processed to at least one of the other processor cores (CPU1~CPU5), DSP module 20, or NPU module 30 for execution based on task type, real-time requirements, or computational characteristics.

[0023] DSP module 20 is dedicated to performing computationally intensive tasks involving specific mathematical transformations and signal processing algorithms. In one specific embodiment, DSP module 20 employs a multi-core DSP architecture and integrates dedicated hardware accelerators, such as those optimized for algorithms like Fast Fourier Transform (FFT) and Constant False Alarm Rate (CFAR) detection. Exemplarily, DSP module 20 also features a highly efficient hardware multiply-accumulate unit (MAC), which significantly improves processing speed and reduces power consumption.

[0024] In this embodiment, the number of DSP modules 20 can be one or more to meet different computing power expansion needs.

[0025] The NPU module 30 integrates a neural network engine, which can include matrix operation units, vector processing units, and activation function units, dedicated to performing inference operations on neural network models. The NPU module 30 supports fixed-point and floating-point precision calculations such as INT8 and FP16, and is compatible with mainstream AI frameworks such as TensorFlow and PyTorch, enabling efficient execution of inference operations for various neural network models.

[0026] It should be noted that, Figure 1This application provides a schematic diagram of the system-on-a-chip architecture. To clearly illustrate the core components and connections, the number of each functional module in the diagram is merely illustrative; the number of DSP modules 20 and NPU modules 30 can be expanded to one or more depending on the computing power requirements of the application scenario, and is not limited to the single module form shown in the diagram. The number of processor cores in the main processor module 10 can also be increased or decreased according to performance requirements.

[0027] This embodiment configures the main processor module 10 to include multiple processor cores 101, with at least one first processor core 101 centrally executing the dynamic allocation of tasks to be processed. At the same time, the digital signal processor module, the neural network processor module, and the main processor module can directly interact with each other through a shared storage area. This achieves fine-grained matching and collaborative work of heterogeneous computing resources at the chip architecture level, and optimizes computing power utilization, data interaction efficiency, and system energy efficiency ratio in the overall architecture.

[0028] In some embodiments, the first processor core 101 is used for: The tasks to be processed involving digital signal processing algorithms are assigned to the DSP module 20 for execution; Tasks involving neural network inference algorithms are assigned to NPU module 30 for execution.

[0029] In some embodiments, the digital signal processing algorithm includes at least one of Fast Fourier Transform, Constant False Alarm Rate (CFAR) detection, and coordinate transformation operations. These algorithms are all core foundational algorithms in the fields of automotive radar signal processing and motor vector control.

[0030] In some embodiments, coordinate transformation operations include Parker transformation or Clarke transformation.

[0031] In some embodiments, the neural network inference algorithm includes at least one of target recognition, motion prediction, and fault diagnosis. These algorithms are all key AI tasks in the perception, decision-making, and maintenance stages of the automotive intelligence process.

[0032] The core control logic of the system-on-a-chip in this embodiment is as follows: the first processor core 101 dynamically allocates the task to the most suitable processing module for execution based on the inherent computational characteristics of the task. Here, the computational characteristics of the task refer to the degree of matching between the core computing type upon which the task depends and the hardware acceleration unit.

[0033] Specifically, when the first processor core 101 acquires a task to be processed (such as an intermediate frequency digital signal from a radar sensor, current sampling data from a motor control system, or a planning instruction issued by an upper-layer application), it analyzes the task type, data characteristics, or algorithm tags. This analysis can be achieved in the following ways: the task carries attribute identifiers (such as function annotations or model metadata) when it is submitted; or the task scheduler run by the first processor core 101 matches the task according to a preset rule table; or the static analysis results completed by the compiler during the compilation phase are written into the task descriptor.

[0034] If the core computation of the task is determined to involve typical digital signal processing algorithms such as Fast Fourier Transform (FFT), Constant False Alarm Rate (CFAR) detection, and coordinate transformation operations, then the first processor core 101 will assign it to the DSP module 20 for execution. This is because the DSP module 20 integrates a dedicated hardware multiply-accumulate unit (MAC), an FFT accelerator, a CFAR detection accelerator, etc., and its operation mode is highly matched with the above algorithms. It can complete multiple multiply-accumulate operations in a single clock cycle, which is significantly better than the software implementation of general-purpose processor cores.

[0035] If the core computation of the task is determined to be inference computation based on a neural network model, such as convolution, matrix multiplication and addition, activation function mapping, etc., then the first processor core 101 allocates it to the NPU module 30 for execution. The NPU module 30 has built-in matrix operation units, vector processing units, and depth-configurable systolic arrays. Its parallel computing architecture is highly compatible with the computing mode of neural network forward inference, and it can complete large-scale tensor operations with extremely low power consumption.

[0036] System management, task scheduling, interrupt response, peripheral driver and other general logic control tasks are executed by the first processor core 101 itself or assigned to other processor cores (CPU1~CPU5) in the main processor module 110 to ensure resource isolation between real-time tasks and computationally intensive tasks.

[0037] This data interaction process does not require the main processor module 110 to perform data transfer or format conversion, thus avoiding the additional latency and power consumption caused by cross-core data copying, cache consistency maintenance, and bus arbitration in traditional architectures.

[0038] This embodiment's system-on-a-chip integrates three heterogeneous computing units—a main processor, a DSP, and an NPU—and intelligently allocates resources based on the task's computational characteristics. This allows signal processing, AI inference, and control tasks to be executed in parallel on dedicated hardware, solving the inefficiency problem caused by frequent data transfer between different processing units in related technologies. Because tasks are directly routed to modules with the corresponding computing capabilities, unnecessary intermediate transmissions are reduced. Simultaneously, it addresses the issue of high system response latency caused by task execution separation; dedicated hardware acceleration and parallel processing significantly shorten the processing chain for critical tasks. Furthermore, the dynamic allocation strategy based on computational characteristics makes task scheduling and resource allocation among multiple cores more flexible and efficient, better meeting the stringent requirements of complex automotive applications for real-time performance and dynamic computing power allocation.

[0039] In some embodiments, such as Figure 2 As shown, the main processor module 10 is connected to the DSP module 20 and the NPU module 30 via a high-speed bus 11.

[0040] This embodiment utilizes a high-speed bus 11 to interconnect the main processor module 10, the digital signal processor module 20, and the neural network processor module 30, providing a high-bandwidth, low-latency physical communication infrastructure for the heterogeneous computing units within the system-on-a-chip 100. The high-speed bus 11 supports concurrent access from multiple master devices and out-of-order transmission, eliminating the need for each processor module to wait for bus arbitration to become idle when accessing the shared memory area 40, significantly reducing bus contention latency in multi-core parallel computing scenarios.

[0041] In some embodiments, such as Figure 2 As shown, the system-on-chip 100 also integrates a direct memory access (DMA) controller 50, which supports independent data transfer between the main processor module 10, the DSP module 20 and the NPU module 30 without occupying the computing resources of the processor core, thereby further improving data transfer efficiency.

[0042] This embodiment establishes a data transfer engine independent of the processor core by integrating a direct memory access controller 50. After the initial configuration of the task scheduling core is completed, the DMA controller 50 can autonomously perform batch data transfers specified by the descriptor between the main processor module 10, the digital signal processor module 20, the neural network processor module 30, and the storage module 401, without any processor core intervention in instruction execution or interrupt response, thus freeing the processor core from the data transfer task.

[0043] In some embodiments, the system-on-a-chip 100 further includes a storage module 401, which is connected to the main processor module 10, the DSP module 20 and the NPU module 30; a shared storage area 40 is located in the storage module 401.

[0044] In this embodiment, the shared memory region 40 can be located in on-chip static random access memory (SRAM) or in dedicated tightly coupled memory (TCM) inside the main processor module 10. All processor modules can directly access the shared memory region 40, thereby achieving zero-copy data transfer.

[0045] The storage module 401 serves as an on-chip centralized storage resource pool, interconnected with the main processor module 10, DSP module 20, NPU module 30, and direct memory access controller 50 via high-speed bus 11. The storage module 401 supports concurrent access from multiple master devices and incorporates an arbitration mechanism to ensure the real-time requirements of high-priority tasks.

[0046] Storage module 401 may include various types of storage media to accommodate different data requirements for capacity, speed, power consumption and non-volatility, such as static random access memory (SRAM) and non-volatile memory (NVM).

[0047] In some embodiments, the storage module 401 includes a non-volatile storage cell employing a resistive variable memory.

[0048] This embodiment optimizes capacity, speed, power consumption, and reliability in the storage subsystem of the automotive domain control system-on-a-chip by using resistive random access memory (RRAM) as the non-volatile storage unit in storage module 401.

[0049] It should be noted that the storage module 401 and its included shared storage area 40 are the preferred physical carriers for implementing data interaction functions in this application, but not the only implementation method. When the system-on-chip 100 does not integrate a dedicated storage module, the same interaction function can still be achieved through on-chip distributed SRAM, cache coherence interconnect, or off-chip memory.

[0050] In some embodiments, at least one DSP module 20 is connected to the main processor module 10 via a parallel bus or a point-to-point link.

[0051] As an optional implementation method, such as Figure 3 As shown, the main processor module 10 is connected to multiple DSP modules 20 (DSP module 1, DSP module 2, ..., DSP module N) via a shared parallel bus. The parallel bus includes independent address, data, and control buses, supporting both broadcast and burst transmission modes. The main processor module 10 acts as the bus master, accessing the internal registers or memory space of each DSP module 20 through an arbitration mechanism. This implementation is suitable for scenarios with a large number of DSP modules 20 but where the communication bandwidth requirements of a single module are not extreme, offering advantages such as fewer connections and convenient expansion.

[0052] As another alternative implementation method, such as Figure 4 As shown, the main processor module 10 is connected to at least one DSP module 20 via point-to-point links. Each point-to-point link is an independent physical channel, such as an LVDS differential pair, a source-synchronous clock interface, or an on-chip high-speed serial link, dedicated to high-bandwidth, low-latency communication between the main processor module 10 and a single DSP module 20. In this implementation, the link bandwidth is not shared between the DSP modules 20, and the main processor module 10 can simultaneously exchange full-duplex data with multiple DSP modules 20 without interference. This method is suitable for scenarios with stringent real-time requirements, such as in motor vector control loops where the main processor needs to exchange current loop data with the DSP modules at microsecond intervals.

[0053] The two connection methods described above can be flexibly selected or deployed in combination based on the overall architecture of the on-chip system, the target application scenario, and power consumption constraints. Regardless of whether a parallel bus or a point-to-point link is used, the main processor module 10 and the DSP module 20 maintain a unified address space addressing or independent addressing mapping, facilitating transparent access by upper-layer software.

[0054] In some embodiments, the number of at least one NPU modules 30 is multiple, and the at least one DSP module 20 and the multiple NPU modules 30 have a one-to-one or one-to-many interconnection topology.

[0055] As an optional implementation method, such as Figure 3 and Figure 4 As shown, at least one DSP module 20 and multiple NPU modules 30 are interconnected in a one-to-one topology. That is, each DSP module 20 is fixedly paired with a specific NPU module 30. This implementation is suitable for scenarios with clear data pipelines and independent channels. For example, in a multi-radar fusion sensing system, each radar channel is equipped with an independent DSP for signal preprocessing, and the preprocessing results are directly sent to its paired NPU for target recognition. Each channel processes data in parallel and is decoupled from the others. This topology has the advantages of good data isolation and simple software design.

[0056] As another alternative implementation method, such as Figure 5 and Figure 6As shown, at least one DSP module 20 and multiple NPU modules 30 are interconnected in a one-to-many topology. That is, the preprocessing result of a single DSP module 20 can be distributed to multiple NPU modules 30 for parallel execution of inference tasks, or routed to different NPU modules 30 according to task type. This implementation is suitable for scenarios where single-channel sensor data needs to perform multi-model inference simultaneously. For example, after the image acquired by the forward-looking camera is preprocessed by the DSP, it can be simultaneously sent to NPU module 1 for vehicle detection, NPU module 2 for lane line recognition, and NPU module 3 for drivable area segmentation. This topology fully utilizes the parallel computing power of the NPU array and significantly reduces the cumulative latency of multi-task serial processing.

[0057] The aforementioned one-to-one or one-to-many interconnection topologies can be implemented through on-chip cross switches, data distribution units, or configurable routing tables. The interconnection topology can be fixed during the chip design phase or can be dynamically reconfigured at runtime to adapt to the computing power scheduling requirements of different application scenarios.

[0058] In some embodiments, such as Figure 7 As shown, a dedicated data transmission path 102 is provided between at least one DSP module 20 and at least one NPU module 30. The DSP module 20 is used to send the generated data to the NPU module 30 through the dedicated data transmission path 102.

[0059] In this embodiment, a dedicated data transmission path 102, independent of the shared memory module 401 and the main processor module 10, is established between the DSP module 20 and the NPU module 30. This path does not pass through the main shared bus or general memory interconnect network of the system-on-chip 100, thus avoiding arbitration conflicts with access requests from other master devices. The establishment of the path, the initiation and completion of data transmission are all autonomously managed by the hardware state machine or DMA controller 50. The main processor module 10 is only configured during the initialization phase, and no processor core is required during the transmission process. This achieves physical isolation of data transmission and allows concurrent operation without interference when multiple DSP modules 20 and multiple NPU modules 30 are configured.

[0060] The dedicated data transmission path 102 may be implemented in one or more combinations of the following hardware forms, including but not limited to: hardware synchronous FIFO, DMA dedicated channel, and dedicated storage area.

[0061] In some embodiments, such as Figure 8 As shown, among the multiple isomorphic processor cores 101, at least one processor core 101 includes a main processing core 1010 and a lock-step core 1011 set for the corresponding main processing core 1010. The lock-step core 1011 is used to verify the execution result of the corresponding main processing core 1010.

[0062] The main processing core 1010 is the core of executing program instructions and processing data. It reads instructions and data from the non-volatile memory NVM 402 and performs arithmetic and logical operations, control flow jumps, and peripheral access.

[0063] Lockstep core 1011 and main arithmetic core 1010 work together in lockstep mode. In this mode, lockstep core 1011 receives the same input signals as main arithmetic core 1010, including instruction codes, memory addresses, write data, and interrupt events, and independently executes the same computational operations. Lockstep core 1011 can be implemented using the same microarchitecture as main arithmetic core 1010, or it can be a simplified processor core with reduced functionality but instruction set compatibility, to achieve a balance between area overhead and fault coverage.

[0064] Comparator 1012 is connected to the outputs of both the main arithmetic core 1010 and the lockstep core 1011. Comparator 1012 is configured to compare key results generated by the main arithmetic core 1010 and the lockstep core 1011 during execution, either in real-time or at fixed clock intervals. These key results include, but are not limited to: data and addresses written to memory, updated values ​​in the status register, changes in the program counter (PC), and control signals output to peripherals. It is understood that comparator 1012 can be integrated into the core or used as a standalone module.

[0065] When comparator 1012 detects that the outputs of the main arithmetic core 1010 and the lockstep core 1011 are completely consistent, it determines that the current execution process of the main arithmetic core 1010 is normal, and the system continues to run. If the comparison results are inconsistent, it indicates that at least one of the main arithmetic core 1010 or the lockstep core 1011 may have experienced a random hardware failure or transient error. At this time, the system can trigger a preset safety mechanism to generate an error indication signal, such as generating a functional safety interrupt, recording an error, initiating a system recovery process, or safely migrating the task to another intact processor core, thereby ensuring the overall functional safety and reliability of the system. This error indication signal is sent to the functional safety management unit 103.

[0066] The lockstep core 1011 can perform verification of the main processing core 1010 at different granularities. For example, it can be configured as instruction-level lockstep, comparing the execution results of each instruction, resulting in the shortest fault detection latency and highest accuracy, suitable for ASIL-D level safety-critical applications. It can also be configured as cycle-level or block-level lockstep, comparing data in units of fixed clock cycles or basic operation blocks. The lockstep core 1011 itself can be a complete processor core with the same microarchitecture as the main processing core 1010, or it can be a simplified coprocessor core focused on result verification.

[0067] By introducing a lockstep core architecture, the system-on-a-chip (SoC) in this embodiment can effectively achieve real-time monitoring and fault tolerance of the processor core's computation process, making it suitable for application scenarios requiring high functional safety integrity levels (such as ASIL-D level in automotive electronics). The combination of the lockstep core and dynamic task allocation based on computational characteristics enables the SoC to provide high-performance heterogeneous computing capabilities while also possessing the basic hardware guarantees to meet the highest safety standards, thus solving the technical challenge of achieving both high computing power and high reliability in complex automotive environments.

[0068] In some embodiments, such as Figure 9 As shown, the system-on-a-chip 100 also includes a communication interface module 60, which includes at least one of a controller local area network (CAN) interface, an Ethernet interface, a serial peripheral interface (SPI), an internal integrated circuit interface (I2C), and a pulse width modulation interface (PWM).

[0069] The communication interface module 60 is the physical layer and link layer channel for the system-on-chip 100 to exchange data with external sensors, actuators, other controllers and diagnostic devices.

[0070] It should be noted that the communication interface module 60 is not a necessary technical feature for realizing the inventive concept of this application. The heterogeneous architecture, task scheduling, and shared memory interaction mechanism of the main processor module 10, DSP module 20, and NPU module 30 in the embodiments of this application are completely independent of whether the system-on-a-chip 100 integrates the communication interface described in this embodiment.

[0071] To fully explain the working principle and technical effects of the present invention, the following section provides a detailed explanation of the heterogeneous collaborative working mechanism of the system-on-a-chip, using two typical application scenarios: automotive radar signal processing and motor vector control.

[0072] This application scenario focuses on millimeter-wave radar perception tasks within Advanced Driver Assistance Systems (ADAS). For example... Figure 10 As shown, the radar sensor transmits a frequency-modulated continuous wave (FMCW) signal, which is reflected by the target and captured by the receiving antenna. After mixing in the radar chip 201, an intermediate frequency (IF) analog signal is generated. This signal is then digitized by an analog-to-digital converter (ADC) to form a raw radar data frame, which is input to the system-on-chip 200 of this application for processing. Figure 11 As shown, a complete radar perception pipeline needs to sequentially complete range-dimensional FFT, Doppler-dimensional FFT, constant false alarm rate (CFAR) detection, peak selection and target clustering, target recognition and classification, and target tracking and motion prediction tasks.

[0073] Among the tasks mentioned above, distance-dimensional FFT, Doppler-dimensional FFT, CFAR detection, peak selection and clustering belong to digital signal processing algorithms, characterized by fixed computation patterns, regular data flow, and high real-time requirements; target recognition and motion prediction belong to neural network inference algorithms, characterized by complex computation patterns, high parallelism, and high requirements for accuracy and generalization ability.

[0074] In this scenario, the workflow of the on-chip system of the present invention is as follows: The radar intermediate frequency signal is converted into digital baseband data by an off-chip ADC and transmitted to the input buffer of the storage module 401 through the communication interface module 60 or the direct memory access controller 50. The first processor core (CPU0) in the main processor module 10 detects the arrival of a new data frame, creates a radar processing task instance, and marks it as "radar signal processing pipeline" according to the task type label.

[0075] The first processor core 101 executes a task scheduler, allocating digital signal processing subtasks such as distance-dimensional FFT, Doppler-dimensional FFT, CFAR detection, peak selection and clustering to the DSP module 20 for execution; and allocating neural network inference subtasks such as target recognition and motion prediction based on point cloud input to the NPU module 30 for execution; system status monitoring, task progress tracking and result reporting are automatically executed by the first processor core 101 or other processor cores (CPU1~CPU5).

[0076] After receiving the task, DSP module 20 reads the raw radar data frame from the input buffer of storage module 401. The DSP core utilizes its integrated FFT accelerator, CFAR detection unit, and clustering engine to sequentially execute range-dimensional FFT, Doppler-dimensional FFT, CFAR detection, peak selection, and clustering tasks. These processes are executed entirely pipelined within DSP module 20 without intervention from main processor module 10. After preprocessing, DSP module 20 writes the generated point cloud target list (containing information such as range, velocity, azimuth, and signal-to-noise ratio for each target) to the shared storage area of ​​storage module 401.

[0077] After the DSP module 20 completes preprocessing, it directly notifies the NPU module 30 that the data is ready via a hardware synchronization mechanism (such as a dedicated interrupt line or DMA channel completion signal). The NPU module 30 reads the point cloud target list from the shared memory area through a dedicated data transmission path, without the need for the main processor module 10 to intervene in address resolution and data transfer.

[0078] The NPU module 30 loads a pre-trained point cloud neural network model and sequentially performs target recognition and motion prediction on the input point cloud to generate inference results.

[0079] The inference results are written back to the result area of ​​the storage module 401 by the NPU module 30. The first processor core 101 learns that the results are ready through polling or interrupt mechanisms, reads the target information and sends it to the actuator (such as the braking system or instrument panel) or the central computing platform through the communication interface module 60.

[0080] In radar signal processing scenarios, this solution offloads computationally intensive preprocessing tasks such as range-dimensional FFT, Doppler-dimensional FFT, and CFAR detection to a dedicated acceleration unit in the DSP module, and offloads AI inference tasks such as target recognition and classification to a parallel computing architecture in the NPU module. Simultaneously, a dedicated data transmission path between the DSP and NPU enables zero-copy direct delivery of preprocessing results, forming a tightly coupled hardware pipeline from raw radar to perception output. Compared to traditional CPU-DSP discrete solutions or pure software implementations, this solution reduces end-to-end latency in radar perception, decreases CPU computational power consumption, and improves system energy efficiency. Furthermore, the execution cycles of both DSP preprocessing and NPU inference are hardware-level deterministic, meeting the stringent requirements of L2+ level assisted driving for both perception latency and functional safety.

[0081] This application scenario targets vector control tasks for traction motors or electric power steering (EPS) motors in new energy vehicles. For example... Figure 12 As shown, the vector control of a permanent magnet synchronous motor (PMSM) needs to perform the following computational tasks with extremely high real-time cycle: phase current sampling and reconstruction, Clarke Transform, Park Transform, PID regulation, Inverse Park Transform, and Space Vector Pulse Width Modulation (SVPWM).

[0082] In the above tasks, Clarke transform, Park transform, and inverse Park transform are coordinate transformation algorithms, while PID control and SVPWM are real-time control algorithms. All of them have the characteristics of strict period determinism, microsecond-level execution budget, and zero jitter tolerance.

[0083] In this scenario, the workflow of the on-chip system of the present invention is as follows: The on-chip system's internal timer generates a fixed-period PWM synchronization interrupt. The first processor core 101 (CPU0) responds to the interrupt, creates an FOC control cycle task, and assigns coordinate transformation operations such as Clarke transform, Park transform, and inverse Park transform to DSP module 20 for execution. Real-time control operations such as PID regulation and SVPWM duty cycle calculation are assigned to other processor cores (such as CPU1) for execution, or are executed by CPU0 itself. System status monitoring and fault diagnosis tasks are assigned to the lockstep core monitoring thread for execution.

[0084] DSP module 20 reads the three-phase current sampling values ​​from ADC module 302 (or storage module). The DSP core uses its internally integrated coordinate transformation dedicated arithmetic unit to complete coordinate transformation operations such as Clark transformation, Park transformation, and inverse Park transformation within a single instruction cycle, and writes the dq axis current values ​​into the shared storage area 40 of storage module 401, notifying CPU1 that the data is ready through hardware semaphores.

[0085] CPU1 reads the dq axis current value from the shared memory area, compares it with the target instruction value, performs PID adjustment and SVPWM duty cycle calculation, and writes the calculated PWM duty cycle parameter into the comparison register of the PWM module. The PWM module 301 automatically generates a complementary PWM waveform according to the set carrier frequency to drive the three-phase motor 303.

[0086] This scenario has extremely high functional safety requirements (typically ASIL-C or ASIL-D). The main processor module 110 is equipped with a lockstep processor core (such as CPU2) that performs current sensor validity checks, overcurrent threshold monitoring, and watchdog feeding tasks in parallel.

[0087] The lockstep core performs redundant execution and compares the results of the control calculations executed by CPU1. If an inconsistency is detected (such as due to a transient fault), the safety state machine is immediately triggered, including: blocking the PWM output to put the motor into a safe torque shutdown state; recording the fault context to the non-volatile area of ​​the storage module 401; and reporting the fault code through the CAN interface.

[0088] In motor vector control scenarios, this solution offloads coordinate transformation operations such as Clarke transform, Park transform, and inverse Park transform to a dedicated coordinate transformation unit in the DSP module, completing current decoupling calculations within a single instruction cycle. Real-time control tasks such as PID regulation and SVPWM are assigned to independent CPU cores for execution. Simultaneously, a lockstep core is used for redundant execution of control operations and real-time result verification. This solution enables the complete execution of high-frequency control cycles (10kHz~20kHz) within 20μs, completely eliminating deterministic jitter in control delays. Furthermore, a hardware-level redundant comparison mechanism achieves microsecond-level detection and safety response to random hardware faults. This allows the on-chip system to meet ASIL-D functional safety requirements without additional software self-testing overhead, providing a high-power-density motor controller with an integrated on-chip solution that combines ultimate real-time performance with functional safety.

[0089] like Figure 13 As shown, this application embodiment also provides an electronic device 400, which includes a device body and a system-on-a-chip 100 / 200 / 300 as described above disposed within the device body.

[0090] In some embodiments, the electronic device 400 is an automotive radar controller, an automotive motor controller, or an automotive domain controller. The electronic device 400 is located in the vehicle and is used to perform at least one control task among intelligent driving perception fusion, motor vector control, and vehicle domain function coordination.

[0091] Electronic devices may include, but are not limited to, automotive domain controllers, industrial controllers, robot controllers, drone controllers, and energy storage inverters.

[0092] The electronic device 400, by employing the aforementioned system-on-a-chip 100 / 200 / 300, utilizes the first processor core 101 in the main processor module 10 to dynamically allocate signal processing tasks and artificial intelligence inference tasks to the DSP module 20 and NPU module 30 respectively for execution based on the computational characteristics of the tasks to be processed. It also achieves efficient data interaction between the modules through a shared storage area. This solves the technical problems of low heterogeneous computing power collaboration efficiency, insufficient real-time response capability, high system power consumption, and high cost of functional safety implementation in existing intelligent control devices when processing hybrid computing tasks, and significantly improves the overall processing performance and energy efficiency ratio of electronic devices in complex application scenarios.

[0093] See Figure 14 , Figure 14 This is a schematic diagram of the principle framework of a vehicle provided in the embodiments of this application. The vehicle 500 includes a system-on-a-chip 100 / 200 / 300, which is as described in the above embodiments.

[0094] The System-on-a-Chip (SoC) 100 / 200 / 300 is primarily used as a core computing unit in the electronic and electrical architecture of automobiles, and is located in the domain controller, central computing platform, or area controller of the vehicle 500. Through its heterogeneous multi-core architecture, task-based dynamic allocation mechanism, and data interaction system that coordinates shared storage areas and dedicated data transmission paths, the SoC 100 / 200 / 300 enables the vehicle 500 to simultaneously achieve high computing power perception, high real-time control, and high functional safety assurance in complex and dynamic driving environments. This significantly reduces the complexity and cost of the overall vehicle electronic and electrical architecture and supports continuous functional upgrades in the era of software-defined vehicles.

[0095] It should be noted that the vehicle 500 described in this embodiment is not limited to pure electric passenger vehicles, but may also be a hybrid vehicle, commercial vehicle, special operation vehicle, or low-speed park shuttle vehicle with autonomous driving function. Any vehicle that includes the on-chip system described in any embodiment of the present invention as the control core falls within the protection scope of this application.

[0096] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A system-on-a-chip, characterized in that, include: The main processor module includes multiple processor cores; At least one digital signal processor module is connected to the main processor module; At least one neural network processor module is connected to the main processor module and the at least one digital signal processor module; Wherein, at least one first processor core in the main processor module is configured to: assign the task to be processed to at least one of the other processor cores among the plurality of processor cores, the digital signal processor module, or the neural network processor module for execution; The digital signal processor module, the neural network processor module, and the main processor module interact with each other through a shared storage area.

2. The system-on-a-chip according to claim 1, characterized in that, The multiple processor cores are homogeneous processor cores.

3. The system-on-a-chip according to claim 1, characterized in that, The first processor core is used for: The tasks to be processed involving digital signal processing algorithms are assigned to the digital signal processor module for execution; Tasks involving neural network inference algorithms are assigned to the neural network processor module for execution.

4. The system-on-a-chip according to claim 3, characterized in that, The digital signal processing algorithm includes at least one of Fast Fourier Transform, Constant False Alarm Rate Detection, and Coordinate Transformation; the digital signal processor module includes a hardware acceleration unit customized based on automotive radar signal processing or motor vector control.

5. The system-on-a-chip according to claim 3, characterized in that, The neural network inference algorithm includes at least one of target recognition, motion prediction, and fault diagnosis; the neural network processor module includes a neural network operator acceleration unit customized based on vehicle environment perception or state prediction.

6. The system-on-a-chip according to claim 1, characterized in that, Among the plurality of processor cores, at least one processor core includes a main processing core and a lockstep core configured corresponding to the main processing core. The lockstep core is used to verify the execution result of the corresponding main processing core.

7. The system-on-a-chip according to claim 1, characterized in that, The at least one digital signal processor module is connected to the main processor module via a parallel bus or a point-to-point link.

8. The system-on-a-chip according to claim 1, characterized in that, The number of the at least one neural network processor modules is multiple, and the at least one digital signal processor module and the multiple neural network processor modules have a one-to-one or one-to-many interconnection topology.

9. The system-on-a-chip according to claim 1, characterized in that, A dedicated data transmission path is provided between the at least one digital signal processor module and the at least one neural network processor module, and the digital signal processor module is used to send the generated data to the neural network processor module through the dedicated data transmission path.

10. The system-on-a-chip according to claim 1, characterized in that, The main processor module is connected to the digital signal processor module and the neural network processor module via a high-speed bus.

11. The system-on-a-chip according to claim 1, characterized in that, The system-on-a-chip also includes a storage module, which is connected to the main processor module, the digital signal processor module and the neural network processor module, and the shared storage area is located in the storage module.

12. The system-on-a-chip according to claim 1, characterized in that, The system-on-a-chip also includes a direct memory access controller for data transfer between the main processor module, the digital signal processor module, and / or the neural network processor module.

13. An electronic device, characterized in that, It includes a device body and a system-on-a-chip disposed on the device body as described in any one of claims 1 to 12.

14. A vehicle, characterized in that, The vehicle includes a system-on-a-chip as claimed in any one of claims 1 to 12, and / or an electronic device as claimed in claim 13.

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