An aging-aware precision reconfigurable logic synthesis method

Abstract

The application discloses an aging-aware precision reconfigurable logic synthesis method and system, and belongs to the technical field of integrated circuit EDA. The application aims to solve the problems of limited optimization space, introduced error from the beginning and lack of aging modeling in the existing aging-aware synthesis. The application constructs an aging standard cell library, iteratively applies constant replacement to the original circuit to generate multiple approximate candidate circuits, and then constructs a precision reconfigurable circuit composed of reconfigurable modules, which dynamically switches between accurate mode and approximate mode. Through aging-aware timing modeling, a power function model of gate delay with running time is established, and the aging continuity during mode switching is processed. The accurate mode life and the approximate mode remaining life are predicted, and the circuit with the highest score is automatically selected according to the score function. The application can improve the circuit life by about 9.5 times with an additional area overhead of about 3.72% under the premise of meeting the error constraint, which significantly enhances the long-term reliability of digital circuits.

Description

Technical Field

[0001] This invention relates to the design of approximate computing circuits, belonging to the technical field of digital integrated circuit design and computer-aided design (EDA). Specifically, it relates to an aging-aware precision reconfigurable logic synthesis method. The circuit output by this method can switch between accurate and approximate modes during operation to mitigate timing violations caused by aging while meeting error constraints. Background Technology

[0002] As complementary metal-oxide-semiconductor (CMOS) process dimensions continue to shrink, transistor aging becomes increasingly severe. Aging effects such as bias temperature instability (BTI) and hot carrier injection (HCI) cause transistor threshold voltages to drift over time, leading to increased logic gate propagation delays. During long-term operation of digital circuits, this gradual delay degradation eventually triggers timing violations, causing circuit malfunction.

[0003] To address aging issues, a class of aging-aware logic synthesis methods has been developed in the prior art. As described in the literature [M. Ebrahimi, F. Oboril, S. Kiamehr, and MB Tahoori, “Agingaware logic synthesis,” in International Conference on Computer-Aided Design, 2013, pp.61–68.], existing aging-aware logic synthesis methods (such as incorporating aging models into process mapping or path optimization processes) typically re-optimize the circuit by predicting delay changes after aging during the synthesis stage, ensuring that it still meets delay constraints within a certain aging period. The characteristics of this type of method are: 1. Optimized only for precise circuits; 2. Limited delay improvement can only be achieved through local structural adjustments or load balancing; 3. Optimization space is limited, especially when the original circuit is already close to optimal, the improvement is relatively small; 4. Unable to provide significant latency reduction capability under severe aging conditions.

[0004] On the other hand, approximate computing techniques have proven effective in overcoming the performance bottlenecks of traditional precise design in recent years. As described in the literature [Z. Zhang, R. Wang, Z. Zhang, R. Huang, C. Meng, W. Qian, and Z. Zhou, “Reliability-enhanced circuit design flow based on approximate logic synthesis,” in Great Lakes Symposium on VLSI, 2020, pp. 71–76.], by allowing the circuit to produce a small, tolerable error in the output, significant improvements in delay, power consumption, or area can be achieved. However, traditional approximate logic synthesis methods have the following problems: 1. Introducing errors from the initial stage of circuit operation; 2. Unable to dynamically adjust accuracy based on aging status; 3. Lack of aging modeling and life assessment mechanisms.

[0005] Therefore, existing technologies lack a design method that can maintain accurate calculations in the early stages, provide significant latency reduction capabilities after aging, and also possess automatic synthesis capabilities.

[0006] In summary, there is an urgent need for a circuit design method that integrates the advantages of aging awareness and approximate computation. This method should possess the following characteristics: maintaining an accurate computation mode in the early stages of circuit operation to ensure output quality; automatically switching to a low-latency approximate mode to extend circuit life when aging causes delays to approach constraint limits; and simultaneously, possessing automated synthesis capabilities to automatically generate optimal precision reconfigurable circuits under given error and delay constraints. To address this need, this invention proposes an aging-aware precision reconfigurable logic synthesis method. Summary of the Invention

[0007] This invention aims to solve the following technical problems: 1. The existing aging sensing integration methods have limited optimization potential; 2. Existing approximate design methods introduce errors from the initial stage; 3. There is a lack of a comprehensive framework that can combine aging modeling and mode switching for life assessment; 4. There is a lack of methods for automatically generating precision-reconfigurable circuits to address aging issues.

[0008] The goal of this invention is to significantly extend circuit life and control hardware area overhead by using a precision reconfigurable structure, while meeting user-given error constraints.

[0009] The technical solution of the present invention is as follows: An aging-sensing precision-reconfigurable logic synthesis method, characterized by comprising the following steps: S1: Construct an aging standard cell library: Perform device-level stress simulation and timing characterization on each standard cell and its input terminals under different input signal probability conditions to obtain a timing library containing delay degradation information; S2: Receive input constraints: Obtain the original combinational logic circuit, output error upper limit, and delay constraints that the circuit must meet provided by the user; S3: Iterative generation of approximate candidate circuits: Iteratively perform local approximation modifications on the original combinational logic circuit to generate multiple approximate candidate circuits that satisfy the upper limit of the output error; S4: Constructing a precision reconfigurable circuit: For each of the approximate candidate circuits, a corresponding precision reconfigurable circuit is constructed by identifying the replaced node and inserting a reconfigurable module; the reconfigurable module consists of an original accurate sub-circuit, an approximate sub-circuit, and a multiplexer controlled by a mode selection signal, used to switch between accurate mode and approximate mode; the approximate sub-circuit uses a constant 0 or 1 to reduce the output arrival time of the corresponding node to 0. S5: Aging-aware timing modeling: Aging-aware timing modeling is performed on the constructed precision reconfigurable circuit, an aging model is established to show the change of delay of each logic gate with running time, and the aging continuity is handled when switching between accurate mode and approximate mode. S6: Predicting Circuit Lifetime: Based on the aging model, the accurate mode lifetime of the precision reconfigurable circuit in accurate mode is calculated using a binary search method. The remaining lifetime in approximation mode is defined as the additional time the circuit continues to operate until the critical path delay reaches the delay constraint again after switching from accurate mode to approximation mode at the end of its lifetime. ; S7: Evaluation and Screening: Incorporating User-Expected Lifespan A score is calculated for each precision reconfigurable circuit, using the following formula: in, The area of ​​the circuit hardware; S8: Optimal Output Circuit: Select the reconfigurable circuit with the highest score as the final output.

[0010] Furthermore, the local approximation modification in step S3 is as follows: the output of a certain logic gate node in the current circuit is replaced with a constant 0 or a constant 1; in each iteration, all candidate local approximation modifications are enumerated, the impact of each candidate modification on the output error is evaluated by random sampling, and the modification with the smallest error increment is selected and applied to the current circuit.

[0011] Furthermore, the low-overhead implementation of the reconfigurable module in step S4 includes: utilizing the characteristic that the approximate sub-circuit is a constant, simplifying the Boolean expression of the reconfigurable module, and performing Boolean matching with the logic gates in the standard cell library; if the matching is successful, the matched logic gate is used directly for implementation, otherwise an additional two-input logic gate is added for implementation; at the same time, for the same reconfigurable module, the Boolean expressions under the two polarities of the mode selection signal are considered separately, and the one with the lowest hardware overhead is selected.

[0012] Furthermore, the specific method for filtering the insertion positions of reconfigurable modules through topology analysis in step S4 is as follows: Exclude all nodes that do not belong to the input of the approximate candidate circuit from the set of nodes to be replaced, and obtain a subset of input nodes; Process each node in the input node subset in reverse topological order: Assume that a reconfigurable module (output constant in approximation mode) is inserted at the node, and recalculate the longest path delay of all nodes in the circuit; if the updated longest path delay of a node is less than λ times the critical path delay of the original approximation circuit, the reconfigurable module is retained, otherwise it is discarded; where λ is a preset threshold, and the recommended value range is 0.5~0.7.

[0013] Furthermore, the aging-sensing time-series modeling described in step S5 includes: Statistically analyze the signal probabilities at the input terminals of each logic gate in both accurate and approximate modes of the precision reconfigurable circuit. Using the aging standard cell library constructed in step S1, the aging delay of each logic gate under a given signal probability is obtained by interpolation; Establish transistor threshold voltage drift The increase in gate delay Δτ with running time T A changing power function model: , ,in These are process-related constants. and This is a coefficient related to factors such as gate type, operating temperature, and voltage. The stress probability is determined by the input signal probability. When switching from accurate mode to approximate mode, an equivalent time point is found on the approximate mode aging curve that is equal to the current transistor threshold voltage drift (equivalent to the same delay increase), so that the aging process evolves continuously.

[0014] Furthermore, the specific method for ensuring aging continuity during mode switching in step S5 is as follows: Suppose that the circuit is operating in accurate mode for time T1, and a certain logic gate has generated an increase in delay. acc (T1); After switching to approximation mode, the aging curve of the gate becomes app (T); Solve for the equivalent time T2, such that app (T2)== acc (T1); After the switch, the aging of the gate continues to increase from point T2 along the approximate mode curve, that is, the total delay increase after running for Δt time after the switch is... app (T2+Δt).

[0015] Furthermore, in step S6, when using the binary search method to solve for lifetime: for the accurate mode lifetime, the lower bound of the search interval is set to 0, and the upper bound is the preset maximum value. The critical path delay at the midpoint is repeatedly calculated and compared with the delay constraint until the interval width is less than the preset precision. The solution for the remaining lifetime of the approximate mode is similar, but an equivalent time conversion needs to be performed at the switching point.

[0016] Furthermore, the local approximation modification only replaces the logic gate output with a constant 0 or a constant 1, without using other logic simplifications or gate-level replacements; the constant approximation ensures that the output arrival time of the replaced node is strictly 0, thereby minimizing the critical path delay.

[0017] Second, the present invention also provides an aging sensing precision reconfigurable logic synthesis system, characterized in that it includes: The aging cell library construction module has its input end connected to the standard cell library and device stress model of the target process, which is used to perform device-level stress simulation and timing characterization under different input signal probability conditions, and outputs the aging standard cell library. The input receiving module is used to receive the user's input of the original combinational logic circuit, the upper limit of the output error, and the delay constraint. Its output is connected to the input of the approximate candidate circuit generation module. An approximate candidate circuit generation module, whose input is connected to the output of the input receiving module, is used to iteratively perform local approximate modifications starting from the original circuit. Each time, the output of a certain logic gate in the circuit is replaced with a constant, generating a series of approximate candidate circuits that meet the upper limit of the output error. Its output outputs each approximate candidate circuit and its corresponding set of replaced nodes. A precision reconfigurable circuit construction module, whose input is connected to the output of the approximate candidate circuit generation module, is used to construct a corresponding precision reconfigurable circuit for each approximate candidate circuit by identifying the replaced node and inserting the reconfigurable module; this module internally includes: - Boolean matching unit, used to implement reconfigurable modules with low overhead by taking advantage of the fact that the approximate sub-circuits are constant; - Topology filtering unit, used to filter the insertion position of reconfigurable modules by analyzing the critical path of the circuit; for each input approximate candidate circuit, the output of this module outputs a precision reconfigurable circuit, and multiple precision reconfigurable circuit candidates are obtained after iteration; The aging-aware timing modeling module has its first input terminal connected to the output terminal of the precision reconfigurable circuit construction module, and its second input terminal connected to the output terminal of the aging unit library construction module. It is used to statistically analyze the input signal probability of each logic gate in accurate mode and approximate mode, establish a power function model of gate delay changing with running time, and handle the aging continuity during mode switching. Its output terminal outputs the aging delay model of each logic gate. The lifetime prediction and scoring module, whose input is connected to the output of the aging-sensing time-series modeling module, is used to calculate the accurate mode lifetime based on the aging model using a binary search method. and approximate mode remaining lifetime And according to the scoring function Each candidate circuit is scored, and the score result of each candidate circuit is output at its output terminal. For the user's expected lifespan, The area of ​​the circuit hardware; The optimal circuit output module, whose input is connected to the output of the lifetime prediction and scoring module, is used to select the highest-scoring precision reconfigurable circuit and output the netlist file of the circuit and its corresponding accurate mode lifetime and approximate mode lifetime.

[0018] Compared with the prior art, the technical advantages of the present invention are: 1) Existing aging-aware logic synthesis methods typically reduce aging-induced latency degradation by adjusting logic mappings or optimizing paths. Their optimization space is limited, making it difficult to ensure circuits meet latency constraints under severe aging conditions. This invention constructs a precision-reconfigurable circuit, enabling the circuit to operate in accurate mode when aging is low, and switch to approximate mode when aging causes critical path latency to exceed latency constraints. This significantly reduces critical path latency and extends circuit lifespan.

[0019] 2) Existing approximate logic synthesis methods typically introduce computational errors from the early stages of circuit operation, causing the system to remain in an approximate computational state throughout its entire lifecycle. This invention, through a precision reconfigurable structure, enables the circuit to maintain accurate computation in the early stages of operation, switching to approximate mode only when aging causes delays to approach delay constraints. This extends the reliable operating time of the circuit while ensuring computational accuracy.

[0020] 3) Compared with existing technologies, experimental results show that the precision reconfigurable circuit generated by this invention can significantly extend circuit life while maintaining low hardware overhead, provided that user-specified error constraints are met. Using multiple standard combinational logic circuits as test objects, experimental results show that the circuit generated by this invention can increase the total circuit life by approximately 9.5 times with an average increase of only about 3.72% in area overhead, thereby significantly improving the long-term reliability of the circuit. Attached Figure Description

[0021] Figure 1 This is a flowchart of the precision reconfigurable circuit design for aging sensing. Figure 2 This is a schematic diagram of implementing a precision reconfigurable circuit based on a given approximation circuit. Figure 3 This is a schematic diagram of a reconfigurable module. Figure 4 This is a diagram illustrating a low-overhead implementation of reconfigurable modules. Figure 5 This is a schematic diagram of the method for filtering the insertion position of reconfigurable modules. Figure 6 This is a schematic diagram of aging delay evolution under mode switching conditions. Detailed Implementation To make the objectives, technical solutions, and advantages of this invention clearer, a precision reconfigurable logic synthesis method for aging sensing provided by this invention will be described in detail below with reference to the accompanying drawings and embodiments. Those skilled in the art should understand that the preferred embodiments described herein are for illustrative purposes only and are not intended to limit the scope of protection of this invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the scope of protection of this invention.

[0022] This invention provides a precision reconfigurable logic synthesis method for transistor aging. Taking the original combinational logic circuit as input, and under user-defined output error limits and delay constraints, this method automatically generates a precision reconfigurable circuit with two operating modes: "accurate mode" and "approximate mode." The circuit initially operates in accurate mode to ensure computational accuracy. When aging causes critical path delays to approach or exceed delay constraints, it switches to approximate mode, significantly reducing critical path delays by introducing a small, tolerable computational error, thereby extending the circuit's effective lifespan. Through aging-aware timing modeling and lifetime prediction, this method automatically selects the optimal design scheme from multiple candidate reconfigurable circuits, balancing hardware overhead and lifetime improvement.

[0023] like Figure 1 As shown, the specific implementation of the present invention includes the following main steps: S1: Construction of the aging cell library. For standard cells under the target process, aging modeling is performed under different input signal probability conditions to generate an aged time series library.

[0024] S2: Input and Initialization. Receives user input regarding the original combinational logic circuit, the maximum allowable output error, and the circuit's delay constraints.

[0025] S3: Approximate candidate circuit generation. By iteratively applying Local Approximate Change (LAC), a series of approximate circuits are generated, each of which meets the user-specified error upper limit.

[0026] S4: Construction of Precision Reconfigurable Circuits. For each approximate candidate circuit, a corresponding precision reconfigurable circuit is constructed by inserting reconfigurable modules (RM) and optimizing the number and implementation of the modules.

[0027] S5: Aging-aware timing modeling. For the constructed precision reconfigurable circuit, an aging model is established to show the change of delay of each logic gate over time, and the aging continuity during the switching between accurate and approximate modes is handled.

[0028] S6: Circuit lifetime prediction. Based on the aging delay model, a binary search method is used to calculate the circuit lifetime in accurate mode and the remaining lifetime in approximate mode.

[0029] S7: Candidate Circuit Evaluation. Based on a unified scoring function, the lifetime and hardware overhead of each candidate circuit are comprehensively evaluated.

[0030] S8: Optimal Result Output. Select the reconfigurable circuit with the highest score as the final output.

[0031] The following is a detailed explanation of each step.

[0032] S1, Construction of the aging unit library.

[0033] S1.1 enumerates different signal probability conditions for each standard unit and its input terminals. Specifically, the signal probability of each input pin is sampled in increments of 0.1 from 0.0 to 1.0, resulting in 11 discrete signal probability values. For logic gates with multiple input pins, it is necessary to consider the combination of signal probabilities for all input pins. Therefore, for a logic gate with multiple input pins... The number of possible probability combinations of input signals for a logic gate with input pins is: There are several types, and each combination corresponds to a different input signal probability condition.

[0034] S1.2 Under each signal probability condition, the threshold voltage drift is obtained through device-level stress simulation.

[0035] S1.3 Based on the obtained threshold voltage drift, the transistor model parameters are corrected to reflect the effect of aging on the electrical characteristics of the device.

[0036] S1.4 Based on the modified transistor model, the standard cells are re-characterized in terms of timing to obtain the corresponding aging standard cell timing library.

[0037] The aging unit library corresponds to the device aging state for a preset operating time, preferably set to the aging result under a 10-year operating time, for subsequent circuit life assessment and timing analysis.

[0038] Step S2: Input and Initialization The user inputs a primitive combinational logic circuit and specifies an upper limit for the allowed output error and the circuit's delay constraints.

[0039] First, input the original combinational logic circuit, the user-specified upper limit of error, and the target delay constraint. Specifically, this embodiment selects the following input circuit: , , , , , , , , , , , The corresponding upper limit of error is set as follows: , , , , , , , , , , , ,in (Error Rate) represents the error rate, while (Mean Squared Error) represents the mean squared error. The input delay constraint is set to the circuit delay after 5 years of accurate circuit aging for each input.

[0040] Step S3: Generation of approximate candidate circuits The original circuit undergoes approximate logic synthesis, iteratively generating multiple approximate candidate circuits. In each round, the scheme compares the current approximate circuit with... Apply a Local Approximate Change (LAC) and generate a new approximate circuit. Before the first round begins, the old approximation circuit is first... The circuit is initialized to an accurate input. In each iteration, a set of possible candidate LACs is first generated, and the impact of each LAC on the output error is evaluated. In each iteration, the LAC with the smallest output error increment is selected from all candidate LACs and applied to the current circuit to obtain a new approximate circuit. When the circuit error exceeds the user-specified error limit, the iteration stops and jumps to step S8; otherwise, it jumps to step S4.

[0041] In this stage, the scheme iteratively introduces local approximate modifications to the original circuit, generating multiple approximate candidate circuits. In each round, the scheme will modify the current approximate circuit... Apply a local approximation modification and generate a new approximate circuit. Preferably, each LAC replaces the output of a logic gate (i.e., a node in a directed acyclic graph) in the circuit with a constant 0 or 1. Specifically, the steps for each round are as follows: (1) The current circuit Each node in the model is considered a potential approximable object.

[0042] (2) For each candidate node, try to replace it with a constant 0 or a constant 1 to form a candidate LAC set.

[0043] (3) Evaluate the impact of each candidate LAC on the circuit output error. Preferably, in this embodiment, a random sampling method is used to evaluate the circuit input error. Specifically, 100,000 sets of input vectors are randomly generated, and the corresponding output error is calculated based on the sampled inputs to approximately characterize the impact of the candidate LAC on the overall circuit output error, thereby avoiding exhaustive enumeration of all possible input combinations.

[0044] (4) Select the LAC with the smallest error increment and apply it to the current circuit to generate a new approximate circuit. .

[0045] The iterative process repeats the above steps until the error of the newly generated approximate circuit exceeds the user-defined error limit.

[0046] Step S4: Construction of Precision Reconfigurable Circuit First, identify the nodes that were replaced during the approximation process due to the application of LAC, and form a set of replacement nodes. Then for each The nodes in the original circuit are used to insert reconfigurable modules (RMs) at corresponding positions, thereby generating a precision reconfigurable circuit with both accurate and approximate operating modes, such as... Figure 2 As shown. Each of the reconfigurable modules corresponds to a single-output sub-circuit, including an original accurate sub-circuit, an approximate sub-circuit, and a selection structure controlled by a mode selection signal, used to switch between accurate and approximate implementations, such as... Figure 3 As shown. In the approximation mode, the approximation sub-circuit uses a constant 0 or 1, thereby reducing the output arrival time of the corresponding node to 0, thus shortening the critical path delay.

[0047] To reduce the hardware overhead of the precision reconfigurable circuit, this invention optimizes the construction of the precision reconfigurable circuit from two aspects: the implementation method of the reconfigurable module and its insertion position. Specifically, this includes: (1) Low-overhead implementation of a single RM Since this scheme only uses constant approximation, one data input of the RM is always constant. Based on this, the Boolean expression of the RM can be simplified, and it can be directly mapped to existing logic gates in the standard cell library via Boolean matching, rather than simply using the direct structure of "original subcircuit + constant + multiplexer (MUX)". Specifically, for each approximation subcircuit and the corresponding constant substitution scheme, we consider two implementation schemes of the RM. The first is completely equivalent to... Figure 3 The structure in the second part is equivalent to the structure in the third part. Figure 3 The MUX structure in the code is a mode-switched version, where a mode selection signal of 1 operates in accurate mode, and a mode selection signal of 0 operates in approximate mode. For each type of RM, a corresponding target Boolean function is constructed and matched with gate functions in the standard cell library. If a match is successful, the matched gate is directly used to implement the RM, such as... Figure 4 As shown in (a). If the match fails (e.g. Figure 4(b) shows that the alternative method of "adding an extra two-input logic gate" is used to implement the corresponding target Boolean function, such as Figure 4 As shown in (c). Ultimately, the one with the lowest hardware overhead is selected from among several possible implementations.

[0048] (2) Reduce the number of RMs inserted at the end. While inserting a reconfigurable node refactoring (RM) can reduce latency on some paths, not all RMs can reduce critical path latency. Therefore, to further reduce hardware overhead, the number of reconfigurable modules inserted can be controlled. To achieve this, the circuit topology is analyzed to determine which node replacements can effectively reduce critical path latency. Specifically, Figure 5 Three scenarios were listed.

[0049] Case 1 correspondence In the replacement node set In the middle, but not the input of the approximate candidate circuit. At this point, when replacing the set of nodes... After other nodes in the process are replaced by RM (e.g. quilt Replacement), should I replace with RM? It will not affect the output signals of other nodes in the circuit, nor will it reduce the circuit delay in approximation mode. Therefore, there is no need to replace it with RM. .

[0050] Case 2 correspondence In the replacement node set In the middle, and is the input of an approximate candidate circuit, but It is not on the critical path of the circuit. Should RM be used as a replacement in this case? This may affect the output signals of other nodes in the circuit, but it will not reduce the circuit delay in approximation mode. In this case, it may be advisable to avoid replacing RM. .

[0051] Case 3 correspondence In the replacement node set In the middle, and is the input of the approximate candidate circuit, at the same time It's still on the critical path of the circuit. However, when replacing the set of nodes... After other nodes in the process are replaced by RM (e.g. quilt (Replacement), the starting point of the critical path (the point where the arrival time AT is 0) is updated to At the output terminal, at this time It no longer affects the latency of the critical path. At this point, it's also possible to consider not replacing RM. .

[0052] Therefore, this scheme first replaces the set of nodes. By excluding nodes that satisfy condition one, we obtain a subset. All nodes in this subset are input nodes of approximate candidate circuits. For nodes belonging to cases two and three, identification is performed as follows: Each node in the circuit is processed sequentially in reverse topology order, and each node is replaced one by one using RM. After replacing a node, the arrival time of its output is set to 0, and the longest path delay of the remaining nodes is updated. If the updated longest path delay of a node is less than the current critical path delay... If the value is doubled, then exclude the node; otherwise, add it to the set of reconfigurable nodes. Preferably, The value is set to 0.7, but this value can be adjusted according to performance requirements. After obtaining the set... Then, two candidate precision reconfigurable circuits can be constructed: 1) replacing RM All nodes constitute a precision reconfigurable circuit. 2) Replace with RM All nodes constitute a precision reconfigurable circuit .because Approximation mode and approximation candidate circuit They are not equivalent, therefore additional verification of the output error in its approximation mode is required to determine whether it exceeds a given error upper limit. If the verification result indicates that the error exceeds the upper limit, then [the appropriate option is selected]. As the precision reconfigurable circuit generated in this iteration; otherwise, This is a precision reconfigurable circuit generated in this iteration.

[0053] Step S5: Aging-sensing time-series modeling First, an aging cell library is constructed based on the standard cell library. By considering the device aging effect under different input signal probabilities, a delay degradation model for each logic cell under different operating times is obtained. The specific steps are as follows: (1) Obtain the input signal probability of each logic gate in the circuit. First, logic simulation and statistical analysis are performed on the circuit under analysis to obtain the signal probabilities at the input terminals of each logic gate. Signal probability characterizes the probability that a particular input pin will take a logic "1" during circuit operation; its magnitude affects the ratio of transistor stress time to recovery time, thus influencing the device's aging rate. For precision reconfigurable circuits, it is necessary to separately statistically analyze: 1) the signal probabilities at the input terminals of each logic gate in accurate mode; and 2) the signal probabilities at the input terminals of each logic gate in approximate mode. This is because the input signal probabilities of some logic gates change after mode switching, corresponding to different aging trajectories.

[0054] (2) Obtain the gate-level aging delay by querying or interpolating the input signal probability. After obtaining the signal probabilities at the input terminals of each logic gate, the delay value of each logic gate at a given aging time is determined using a pre-built aging cell library. Since the aging cell library only represents discrete signal probability points, for any combination of input signal probabilities that occurs in the actual analysis, interpolation needs to be performed between its adjacent represented discrete points to obtain the corresponding gate-level aging delay.

[0055] (3) Establish an aging model for the gate delay in a precision reconfigurable circuit as a function of running time. To extend the aging library from finite-time points to timing analysis under arbitrary runtime, this scheme further establishes a model of gate delay variation over runtime. This scheme adopts a widely used aging degradation model, assuming that when the input signal probability of a logic gate remains constant, its transistor threshold voltage drift... and the increase in gate delay Both can be approximated as running time. The power function, that is: , .in, These are process-related constants. and These are parameters related to specific logic gates, operating temperature, and voltage. The stress probability is determined by the input signal probability.

[0056] Furthermore, for the precision reconfigurable circuit in this scheme, the continuity of the aging state before and after mode switching must also be considered. For some logic gates, the probability of their input signals changes due to mode switching. Therefore, the logic gate may correspond to two different aging curves in accurate mode and approximate mode, called the accurate mode aging curve and the approximate mode aging curve, respectively. Figure 6 As shown. It should be noted that the threshold voltage drift of the device does not change abruptly during mode switching; therefore, the accumulated aging before the switch cannot be cleared but should continue to evolve on the aging curve corresponding to the new mode. Therefore, as... Figure 6 As shown, assuming the circuit is in time Previously, I had been working in accurate mode, and in terms of time... At this point, in accurate mode, a certain gate has accumulated a threshold voltage drift value. After switching to approximate mode, the corresponding moment with the same threshold voltage drift value is found on the approximate mode aging curve of that gate. The subsequent aging process does not start from zero, but from an approximate aging curve. The number of points continues to grow.

[0057] Due to transistor threshold voltage drift and the increase in gate delay Since they exhibit the same time-growth trend, the increase in gate delay can also be spliced ​​using the same method for mode switching. Ultimately, the delay degradation curve of the precision reconfigurable circuit under switching conditions can be considered as a segmented splicing of the accurate mode curve and the approximate mode curve: from 0 to... Follow the accurate aging curve within the time period, Then it turns to the corresponding point in the approximate mode aging curve. It continues to evolve.

[0058] Step S6: Circuit Lifetime Prediction Based on the above aging model, timing analysis is performed on precision reconfigurable circuits to predict their accurate mode lifetime and approximate mode lifetime.

[0059] Specifically, starting from the original circuit input, the arrival times of each node are propagated sequentially according to the topology to obtain the arrival times of each original output. The longest path delay from the original input to the original output is then determined, which is the critical path delay at the current aging time. When the critical path delay first exceeds the delay constraint input by the user, the corresponding runtime is defined as the circuit lifetime. This scheme uses a binary search method to solve for this lifetime point, continuously narrowing the search interval to find the time position where the critical path delay is exactly equal to the delay constraint, thereby efficiently predicting the circuit lifetime.

[0060] For precision reconfigurable circuits, two lifetimes can be defined: 1) Accuracy mode lifetime: refers to the time when the critical path delay first reaches the delay constraint when the circuit is running in accuracy mode, denoted as ;2) Approximate mode lifetime: when the circuit is in After switching to approximate mode, execution continues until the critical path delay reaches the delay constraint again for an additional duration, denoted as . .

[0061] Step S7: Candidate Circuit Scoring Based on pre-defined performance evaluation indicators and combined with aging-sensing timing analysis, the accurate mode lifetime of each candidate circuit is obtained. Approximate mode lifetime and area The performance of the candidate precision reconfigurable circuits generated in this round is evaluated. The optimal solution is ultimately selected from all candidate precision reconfigurable circuits based on a unified evaluation criterion. Specifically, an expected lifespan parameter is introduced. When the approximate mode lifetime exceeds this expected value, the following applies: This serves as an effective approximation of the desired lifetime, thus avoiding over-optimization for lifetimes exceeding actual requirements. Based on this, a performance evaluation metric that comprehensively considers lifetime and hardware overhead is constructed, in the form of: After completion, proceed to the next iteration in step S3.

[0062] Step S8: Output the final result Iterate through all generated precision reconfigurable circuit candidates, calculate their respective scores, and select the circuit with the highest score as the final output. The output includes: the circuit's netlist file (Verilog or BLIF), mode selection signal definition, predicted lifetimes for accurate and approximate modes, hardware overhead, etc.

[0063] To verify the effectiveness of this invention, this embodiment selected several standard combinational logic circuits as test objects, including: C432, C880, C1908 (from the ISCAS85 benchmark set), priority, arbiter, square (from the EPFL benchmark set), and adders and multipliers with different bit widths. The experiment used the ASAP7 predictive 7nm FinFET process, and the aging model was constructed based on 10 years of stress simulation data. Following the specific implementation described above, the method of this invention was run on each circuit, and the performance of the generated precision reconfigurable circuits is shown in Table 1.

[0064] Table 1. Lifetime and overhead of reconfigurable circuits at different precision levels As shown in Table 1, the original accurate circuit reached its delay constraint after 5 years of aging, with a lifetime of 5 years. The accuracy-reconfigurable circuit generated by this invention typically has an accuracy-mode lifetime of less than 5 years (average 3.69 years). This is because the insertion of the reconfigurable module introduces a small amount of additional delay, causing the aging constraint to be reached earlier. However, by switching to approximate mode, the circuit can continue to operate for an average of 43.64 years, with a total lifetime (accurate mode lifetime + approximate mode lifetime) averaging 47.33 years, an improvement of approximately 9.5 times compared to the original circuit's 5 years. The additional area overhead averages only 3.72%, with a minimum of 0.20%, demonstrating the effectiveness of the low-overhead RM design and screening strategy of this invention.

[0065] Furthermore, the precision reconfigurable circuit generated by the sign_mult8 circuit was applied to a DCT / IDCT image processing pipeline. The delay constraint was set to 1.4 times the delay of the original unaged circuit. The output image quality of the original accurate circuit and the precision reconfigurable circuit of this invention was tested before aging and after 10 years of aging, respectively, with peak signal-to-noise ratio (PSNR) as the evaluation index. The results are shown in Table 2.

[0066] Table 2. Comparison of image quality between precision-reconfigurable circuits and accurate circuits in DCT / IDCT applications. Experimental results show that, initially, both circuits can achieve high-quality output images. However, after long-term operation, the original accurate circuit exhibits significant image distortion due to the critical path delay exceeding the delay constraint, resulting in a significant decrease in its peak signal-to-noise ratio (PSNR) (-31.69 dB). In contrast, the precision reconfigurable circuit generated by this invention can switch to approximate mode and continue operating under the same conditions, with only a slight decrease in output image quality (-0.90 dB). Therefore, the precision reconfigurable circuit generated by this invention can maintain stable output quality under aging conditions, exhibiting significantly better performance degradation than the original circuit, thus effectively extending the actual service life of the circuit.

[0067] The age-aware precision reconfigurable logic synthesis method proposed in this invention can be integrated into existing digital integrated circuit EDA tools (such as logic synthesis tools Design Compiler, Genus, etc.) as an optional feature provided to chip designers. Designers only need to provide the original circuit, error constraints, and delay constraints to automatically obtain an optimized precision reconfigurable circuit netlist. This method is particularly suitable for fields with high long-term reliability requirements, such as automotive electronics, aerospace, IoT devices, and chips that need to operate for extended periods in harsh environments. Experiments have shown that this method can achieve nearly a 10-fold increase in effective circuit lifetime with minimal additional area overhead (average 3.72%), while ensuring a smooth transition from early high precision to later fault-tolerant operation.

[0068] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An aging-aware precision reconfigurable logic synthesis method, characterized by, Includes the following steps: S1: Construct an aging standard cell library: Perform device-level stress simulation and timing characterization on each standard cell and its input terminals under different input signal probability conditions to obtain a timing library containing delay degradation information; S2: Receive input constraints: Obtain the original combinational logic circuit, output error upper limit, and delay constraints that the circuit must meet provided by the user; S3: Iterative generation of approximate candidate circuits: Iteratively perform local approximation modifications on the original combinational logic circuit to generate multiple approximate candidate circuits that satisfy the upper limit of the output error; S4: Constructing a precision reconfigurable circuit: For each of the approximate candidate circuits, a corresponding precision reconfigurable circuit is constructed by identifying the replaced node and inserting a reconfigurable module; the reconfigurable module consists of an original accurate sub-circuit, an approximate sub-circuit, and a multiplexer controlled by a mode selection signal, used to switch between accurate mode and approximate mode; the approximate sub-circuit uses a constant 0 or 1 to reduce the output arrival time of the corresponding node to 0. S5: Aging-aware timing modeling: Aging-aware timing modeling is performed on the constructed precision reconfigurable circuit, an aging model is established to show the change of delay of each logic gate with running time, and the aging continuity is handled when switching between accurate mode and approximate mode. S6: predicting the circuit lifetime: based on the aging model, calculate the accurate mode lifetime of the precision reconfigurable circuit in the accurate mode using binary search method ; and the additional time after the circuit switches to the approximate mode at the end of the accurate mode lifetime and continues to run until the critical path delay reaches the delay constraint again, denoted as the approximate mode remaining lifetime ; S7: Evaluation and screening: Introducing user expected lifetime of use A score is calculated for each precision reconfigurable circuit, with the formula as follows: in, The area of ​​the circuit hardware; S8: Optimal Output Circuit: Select the reconfigurable circuit with the highest score as the final output.

2. The precision-reconfigurable logic synthesis method according to claim 1, characterized in that, The local approximation modification in step S3 is as follows: replace the output of a certain logic gate node in the current circuit with a constant 0 or a constant 1; in each iteration, enumerate all candidate local approximation modifications, evaluate the impact of each candidate modification on the output error by random sampling, and select the modification with the smallest error increment to apply to the current circuit.

3. The precision-reconfigurable logic synthesis method according to claim 1, characterized in that, The low-overhead implementation of the reconfigurable module in step S4 includes: utilizing the characteristic that the approximate sub-circuit is a constant, simplifying the Boolean expression of the reconfigurable module, and performing Boolean matching with the logic gates in the standard cell library; if the matching is successful, the matched logic gate is used directly for implementation, otherwise an additional two-input logic gate is added for implementation; at the same time, for the same reconfigurable module, the Boolean expressions under the two polarities of the mode selection signal are considered separately, and the one with the minimum hardware overhead is selected.

4. The precision-reconfigurable logic synthesis method according to claim 1, characterized in that, The specific method for filtering the insertion positions of reconfigurable modules through topology analysis in step S4 is as follows: Exclude all nodes that do not belong to the input of the approximate candidate circuit from the set of nodes to be replaced, and obtain a subset of input nodes; Process each node in the input node subset in reverse topological order: Assume that a reconfigurable module (output constant in approximation mode) is inserted at the node, and recalculate the longest path delay of all nodes in the circuit; if the updated longest path delay of a node is less than λ times the critical path delay of the original approximation circuit, the reconfigurable module is retained, otherwise it is discarded; where λ is a preset threshold, and the recommended value range is 0.5~0.

7.

5. The precision-reconfigurable logic synthesis method according to claim 1, characterized in that, The aging sensing time-series modeling described in step S5 includes: Statistically analyze the signal probabilities at the input terminals of each logic gate in both accurate and approximate modes of the precision reconfigurable circuit. Using the aging standard cell library constructed in step S1, the aging delay of each logic gate under a given signal probability is obtained by interpolation; Establish transistor threshold voltage drift The increase in gate delay Δτ with running time A changing power function model: , ,in These are process-related constants. and This is a coefficient related to factors such as gate type, operating temperature, and voltage. The stress probability is determined by the input signal probability. When switching from accurate mode to approximate mode, an equivalent time point is found on the approximate mode aging curve that is equal to the current transistor threshold voltage drift (equivalent to the same delay increase), so that the aging process evolves continuously.

6. The precision-reconfigurable logic synthesis method according to claim 1, characterized in that, The specific method for ensuring aging continuity during mode switching in step S5 is as follows: Suppose that the circuit is operating in accurate mode for time T1, and a certain logic gate has generated an increase in delay. acc (T1); After switching to approximation mode, the aging curve of the gate becomes app (T); Solve for the equivalent time T2, such that app (T2)== acc (T1); After the switch, the aging of the gate continues to increase from point T2 along the approximate mode curve, that is, the total delay increase after running for Δt time after the switch is... app (T2+Δt).

7. The precision-reconfigurable logic synthesis method according to claim 1, characterized in that, In step S6, when using the binary search method to solve for lifetime: for the accurate mode lifetime, set the lower bound of the search interval to 0 and the upper bound to the preset maximum value, repeatedly calculate the critical path delay at the midpoint and compare it with the delay constraint until the interval width is less than the preset precision; the solution for the remaining lifetime of the approximate mode is similar, but an equivalent time conversion needs to be performed at the switching point.

8. The precision-reconfigurable logic synthesis method according to claim 1, characterized in that, The local approximation modification only replaces the logic gate output with a constant 0 or a constant 1, without using other logic simplifications or gate-level replacements; the constant approximation ensures that the output arrival time of the replaced node is strictly 0, thereby minimizing the critical path delay.

9. A precision-reconfigurable logic synthesis system for aging sensing, characterized in that, include: The aging cell library construction module has its input end connected to the standard cell library and device stress model of the target process, which is used to perform device-level stress simulation and timing characterization under different input signal probability conditions, and outputs the aging standard cell library. The input receiving module is used to receive the user's input of the original combinational logic circuit, the upper limit of the output error, and the delay constraint. Its output is connected to the input of the approximate candidate circuit generation module. An approximate candidate circuit generation module, whose input is connected to the output of the input receiving module, is used to iteratively perform local approximate modifications starting from the original circuit. Each time, the output of a certain logic gate in the circuit is replaced with a constant, generating a series of approximate candidate circuits that meet the upper limit of the output error. Its output outputs each approximate candidate circuit and its corresponding set of replaced nodes. A precision reconfigurable circuit construction module, whose input is connected to the output of the approximate candidate circuit generation module, is used to construct a corresponding precision reconfigurable circuit for each approximate candidate circuit by identifying the replaced node and inserting the reconfigurable module; this module internally includes: - Boolean matching unit, used to implement reconfigurable modules with low overhead by taking advantage of the fact that the approximate sub-circuits are constant; - Topology filtering unit, used to filter the insertion position of reconfigurable modules by analyzing the critical path of the circuit; for each input approximate candidate circuit, the output of this module outputs a precision reconfigurable circuit, and multiple precision reconfigurable circuit candidates are obtained after iteration; The aging-aware timing modeling module has its first input terminal connected to the output terminal of the precision reconfigurable circuit construction module, and its second input terminal connected to the output terminal of the aging unit library construction module. It is used to statistically analyze the input signal probability of each logic gate in accurate mode and approximate mode, establish a power function model of gate delay changing with running time, and handle the aging continuity during mode switching. Its output terminal outputs the aging delay model of each logic gate. The lifetime prediction and scoring module, whose input is connected to the output of the aging-sensing time-series modeling module, is used to calculate the accurate mode lifetime based on the aging model using a binary search method. and approximate mode remaining lifetime And according to the scoring function Each candidate circuit is scored, and the score result of each candidate circuit is output at its output terminal. For the user's expected lifespan, The area of ​​the circuit hardware; The optimal circuit output module, whose input is connected to the output of the lifetime prediction and scoring module, is used to select the highest-scoring precision reconfigurable circuit and output the netlist file of the circuit and its corresponding accurate mode lifetime and approximate mode lifetime.

Images