A multi-layer printed circuit board thermal resistance path intelligent optimization layout and system

The intelligent optimization system for thermal resistance paths on multilayer printed circuit boards solves the problem of thermal resistance path identification and optimization in existing technologies, achieving accurate identification and optimization of thermal resistance paths and improving the controllability and stability of the design.

CN122334167APending Publication Date: 2026-07-03SHENZHEN YINGHAI XINGYE ELECTRONICS CO LTD
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Patent Information

Application Number
CN202610557754.X
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-04-24
Publication Date
2026-07-03

AI Technical Summary

Technical Problem

Existing thermal design solutions for multilayer printed circuit boards struggle to accurately identify and optimize thermal resistance paths, leading to inconsistent relationships between objects and discontinuous heat transfer during the analysis process. These solutions rely heavily on the designer's experience and are difficult to optimize specifically under manufacturing rules.

Method used

A multilayer printed circuit board thermal resistance path intelligent optimization system is adopted, including a baseline thermal map module, a thermal resistance identification module, a path optimization module, and a fine-tuning iteration module. Through unified parameter mapping, thermal solution, and editor operator optimization, it identifies the dominant thermal resistance path, secondary compensation path, and obstruction segment, and achieves targeted optimization and fine calibration.

Benefits of technology

It improves the targeting of thermal resistance identification and the interpretability of layout editing, enhances the controllability of implementation under design rules and the stability of the final layout result, and reduces the complexity and experience dependence of layout adjustment.

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Abstract

This invention discloses an intelligent optimization layout and system for thermal resistance paths in multilayer printed circuit boards (PCBs), relating to the field of PCB design optimization technology. It performs a unified mapping of layer stacking parameters, regional thermal conductivity parameters, target heat source parameters, heat inlet parameters, through-connection parameters, inner layer diffusion parameters, and boundary condition parameters to construct a baseline thermal map and target heat source region. A hierarchical directed graph model is then established to identify dominant thermal resistance paths, secondary compensation paths, and obstruction segments. Candidate layout parameters are generated and filtered based on a set of constraint parameters. Furthermore, a single key parameter is selected to perform interval-shrinking refinement iterations, outputting the final layout parameters. This approach can converge board-level thermal problems into local path optimization problems, improving the specificity of thermal resistance identification, the interpretability of layout adjustments, and the stability of results.
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