A multi-functional memory computing cell based on ferroelectric transistor, array and its fault-tolerant method

Abstract

The present application relates to a kind of multifunctional storage computing unit based on ferroelectric transistor, array and its fault-tolerant method.The unit is composed of two N-type FeFET and two NMOS transistor, by configuring peripheral control signal / circuit can realize three kinds of working mode: memory mode supports the non-volatile storage and read-write operation of data;Memory logic computing mode supports the Boolean logic operation to the storage word;Three-state content addressable memory mode supports high-speed parallel search and "irrelevant" bit matching operation.Further, the present application proposes a kind of anti-radiation reinforced three-state content addressable memory unit.The unit is based on the original multifunctional unit, access single-cycle storage module DICE and four storage transistors, realizes single node flip recovery.The present application integrates storage, computing and search function in single compact unit structure, improves energy efficiency and functional density, and the anti-radiation reinforced unit has good soft error tolerance ability and process robustness.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a multifunctional storage computing unit based on ferroelectric field-effect transistors, as well as an array composed of such unit and a fault-tolerant method. Background Technology

[0002] With the rapid development of the Internet of Things (IoT) and edge computing, the data transfer between the processor and memory in the traditional von Neumann architecture has caused serious "memory wall" and power wall problems. Storage-based computing technology, by embedding computing units inside the memory array and performing data processing in-situ, is a key approach to solving this problem. Content-addressable memory (CAM), with its high-speed parallel search capability, is an important hardware solution for realizing storage-based computing and is widely used in fields such as routing lookup and neural network acceleration.

[0003] Traditional memory computing designs are mostly based on SRAM, but they suffer from problems such as high static power consumption and large area. While designs based on emerging non-volatile memories (such as RRAM and MRAM) have the advantages of high density and low static power consumption, they generally face problems such as high write power consumption, low Ion / Ioff ratio of read current leading to large leakage current, and low sensing margin.

[0004] FeFETs have become ideal devices for building memory computing units due to their excellent characteristics such as compatibility with standard CMOS processes, high on / off current ratio, low leakage current, and non-volatility. FeFETs non-volatilely change their threshold voltage by controlling the polarization direction of the ferroelectric layer through the gate voltage, thereby storing data "0" and "1". However, existing FeFET-based memory computing unit designs are mostly single-function or introduce complex current-mode detection circuits to achieve multiple functions, resulting in a significant increase in power consumption and interface overhead. Furthermore, in radiation environments such as aerospace, FeFET memories are susceptible to single-event upsets, leading to soft errors and reduced system reliability. Summary of the Invention

[0005] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a multifunctional storage computing unit, array and fault-tolerant method based on ferroelectric transistors, the purpose of which is to provide a logic unit with rich computing unit functions and low computing power consumption.

[0006] The present invention is implemented using the following technical solution: a multifunctional memory computing unit based on FeFET, comprising: a first NMOS transistor M1, the drain of which is connected to the first bit line SL1, and the gate of which is connected to the first word line WL1; a first FeFET transistor FeFET1, the source of which is grounded, the drain of which is connected to the source of M1, and the gate of which is connected to SL1; a second NMOS transistor M2, the drain of which is connected to the second bit line SL2, and the gate of which is connected to the second word line WL2; and a second FeFET transistor FeFET2, the source of which is connected to the source of M2, the drain of which is connected to the drain of M2 and connected to SL2, and the gate of which is connected to SL2.

[0007] This invention integrates non-volatile memory and multiple computing functions into a single unit using a structure consisting of two FeFETs and two NMOS transistors. Through the coordinated configuration of peripheral circuits, this unit can dynamically operate in memory mode, in-memory logic computing mode, and tri-state addressable memory mode, achieving efficient reuse of hardware resources and effectively solving the problems of single-function and high hardware overhead in existing units.

[0008] As a further improvement to the above scheme, in the in-memory logic calculation mode, by configuring the potential relationship between WL1, WL2 and SL1, SL2, various Boolean logic operations such as NOT, NAND, NOR, and XOR can be implemented on the pre-charged matching line ML, improving the operational flexibility of the cell. The NOT operation requires M2 and FeFET2 to be turned off, WL1 = 1, and FeFET1 stores the input value according to SL1. When FeFET1 stores 1, ML is connected to ground, and the result is "0". When FeFET1 stores 0, ML is kept at a high level, and the result is "1". The NAND operation turns off M1 and M2 by keeping WL1 and WL2 at a low level and pre-charges the ML node. Since FeFET1 and FeFET2 are connected in series, if either FeFET stores "0", the output ML is kept at a high level. Only when the states of both FeFETs are "1" will the path formed by FeFET1 and FeFET2 pull ML to ground, and the result of the read operation is "0". The NOR operation requires WL1 = SL1 and WL2 = SL2. WL1 (WL2), connected to the gate, controls the left (right) NMOS and FeFET1 (FeFET2) to always store the same value. ML is pre-charged; if either FeFET stores "1", the output ML is pulled to ground. Only when both FeFETs store "0" does ML remain high, resulting in "1". Further, the XOR operation sets... , ML is pre-charged; if the two FeFETs store complementary values, ML remains high; if both FeFETs store "1", the FeFET path pulls ML to ground. If both FeFETs store "0", WL connected to the gate turns on both NMOS transistors, thus directly pulling ML to ground.

[0009] As a further improvement to the above scheme, in the tri-state content-addressable memory mode, by storing two FeFETs in complementary states and using the bit line as the search line to input complementary data, high-speed parallel searching can be achieved by detecting voltage changes on the matching line. In particular, when both FeFETs are stored as "0", the cell is in an "indifferent" state, supporting tri-state matching and expanding the application range of the search function.

[0010] This invention also provides a FeFET-based multifunctional memory computing array, which includes a core array composed of the aforementioned units and peripheral circuits such as word line drivers, bit line buffers, multifunctional sense amplifiers, and encoders. This array has a regular structure, supports row-level parallel operation, and can efficiently realize data storage, logical operations, and content retrieval.

[0011] This invention provides application amplification of the above-mentioned unit and array, and by switching between different modes with control signals, it fully utilizes the multifunctionality of the hardware platform to meet the needs of different application scenarios.

[0012] This invention also provides a radiation-hardened memory computing unit based on FeFET, which, in addition to the aforementioned unit, connects a single-cycle memory module (DICE) and four transfer transistors at node N1. The DICE consists of four cyclically symmetrical two-input inverters. When any sensitive node experiences a voltage jump due to a particle impact, the cross-coupling mechanism of the DICE can pull the remaining nodes back to the correct potential, enabling the unit to self-recover in a single-event upset event and significantly enhancing reliability in a radiation environment. Attached Figure Description

[0013] Figure 1 This is a circuit diagram of the FeFET-based multifunctional storage computing unit according to Embodiment 1 of the present invention.

[0014] Figure 2 This is a schematic diagram of the peripheral circuit of the unit in the in-memory logic calculation mode in Embodiment 1 of the present invention.

[0015] Figure 3 This is a schematic diagram of the operation of the unit in the three-state content addressable storage mode in Embodiment 1 of the present invention.

[0016] Figure 4 This is a schematic diagram of the structure of the FeFET-based multifunctional storage and computing array according to Embodiment 2 of the present invention.

[0017] Figure 5 This is a circuit diagram of the radiation-hardened storage computing unit of Embodiment 3 of the present invention.

[0018] Figure 6 This is a timing simulation result diagram of the unit in memory mode in Embodiment 1 of the present invention.

[0019] Figure 7 This is a timing simulation result diagram of the unit in the in-memory logic computation mode in Embodiment 1 of the present invention.

[0020] Figure 8 This is a timing simulation result diagram of the unit in Content Addressable Memory mode in Embodiment 1 of the present invention.

[0021] Figure 9 This is a timing simulation result diagram of the radiation hardening unit of Embodiment 3 of the present invention under fault injection. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described below with reference to the accompanying drawings and six specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0023] Example 1

[0024] Please see Figure 1 This embodiment provides a multifunctional memory computing unit based on FeFET. The unit includes N-type FeFET transistors FeFET1 and FeFET2, and NMOS transistors M1 and M2.

[0025] The specific connection method is as follows: M1 and FeFET2 are connected in parallel, with their drains serving as the output terminals of the cell. The gate of M1 is connected to the first word line WL1, and the gate of FeFET2 is connected to SL1. M2 and FeFET1 are connected in parallel, with their drains connected to the sources of M1 and FeFET1, respectively. The sources of both are grounded. The gate of M2 is connected to the second word line WL2. The gate of FeFET2 is connected to SL2. The core of this cell lies in utilizing the ferroelectric polarization of the FeFET to non-volatilely store data and using an NMOS transistor to control access to the FeFET.

[0026] The multifunctional unit in this embodiment can realize read / write mode, in-memory logic calculation mode, and content-addressable memory mode.

[0027] In read / write mode, read operations are performed using a pre-charged SA (an inverter in this example). All read and write operations are controlled by two access transistors and their corresponding lines (SL1, SL2, WL1, and WL2).

[0028] The process of writing data "1" or "0" to FeFET1: To avoid interference, both WL1 and WL2 are kept at a low level. A corresponding write voltage (±Vw) is applied through SL1 to switch FeFET1 to the target state. Simultaneously, SL2 is used to shield FeFET2, preventing it from being affected. The process of writing data "1" or "0" to FeFET2: To avoid interference, WL1 is kept at a low level, and WL2 is kept at a high level to ensure that the gate-source voltage VGS of FeFET2 is equal to the voltage value on SL2. A corresponding write voltage (±Vw) is applied through SL2, thereby achieving write control of FeFET2.

[0029] In this embodiment, applying voltages of different magnitudes for the same duration to the gate of the FeFET can change the magnitude of the FeFET threshold voltage, which reflects the storage state of the FeFET. When a voltage -Vw is applied to the FeFET gate, the FeFET is in the high threshold voltage (HVT), which is storage state 0. When a voltage Vw is applied to the FeFET gate, the FeFET is in the low threshold voltage (LVT), which is storage state 1.

[0030] When reading FeFET1, SL1, SL2, and WL2 are low. The read operation is completed in two steps. First, WL1 is ensured to be low, and ML is pre-charged to Vr. Then, WL1 switches to high. At this time, if the storage state of FeFET1 is "1", the voltage of ML will be connected to ground through the path of M1 and FeFET1; if the storage state of FeFET1 is "0", the voltage of ML will remain at Vr. Finally, the voltage of FeFET1 is determined by detecting the voltage of ML. When reading FeFET2, SL1, SL2, and WL2 are low. First, WL2 is ensured to be low, and ML is pre-charged to Vr. Then, WL2 switches to high. At this time, if the storage state of FeFET2 is "1", the voltage of ML will be connected to ground through the path of M2 and FeFET2; if the storage state of FeFET2 is "0", the voltage of ML will remain at Vr. Data can be read by detecting the voltage of ML. The simulation waveform of the FeFET-based multi-functional cell in read / write mode is as follows. Figure 6 As shown.

[0031] In the in-memory logic computation mode, five logic operations can be performed by configuring the potential relationship between WL1, WL2 and SL1, SL2, and all of these logic operations obtain the results through ML.

[0032] Please see Figure 2 This memory architecture supports direct bit-by-bit logic operations on words A and B in two active rows, enabling Boolean logic operations between two memory words. Read operations and Boolean logic are implemented using a voltage-based detection scheme. By comprehensively utilizing the results of NOR and NAND operations, and with the aid of additional logic gates, this structure further implements XOR and other logic functions, as well as addition operations. Simulation waveforms of logic operations performed in the FeFET-based multifunctional cell are shown below. Figure 7 As shown.

[0033] In the NOT gate operation, M2 and FeFET2 must be turned off, WL1 = 1, and FeFET1 stores the input value according to SL1. When FeFET1 stores 1, ML is grounded, and the result is "0"; when FeFET1 stores 0, ML remains high, and the result is "1". The NAND operation turns off the two NMOS by keeping WL1 and WL2 low and precharges the ML node. At this time, since FeFET1 and FeFET2 are connected in series, if either FeFET stores "0", the output ML remains high. Only when both FeFETs are in the state of "1" will the path formed by FeFET1 and FeFET2 pull ML to ground, and the result of the read operation is "0". The NOR operation requires WL1 = SL1 and WL2 = SL2. WL1 (WL2) connected to the gate controls the left (right) NMOS and FeFET1 (FeFET2) to always store the same value, and WL2 connected to the gate controls the right NMOS and FeFET2 to always store the same value. ML is pre-charged; if either FeFET stores a "1", the output ML is pulled to ground. Only when both FeFETs store "0" does ML remain high, resulting in a "1". Further, the XOR operation sets... , ML is pre-charged; if the two FeFETs store complementary values, ML remains high; if both FeFETs store "1", the FeFET path pulls ML to ground. If both FeFETs store "0", WL connected to the gate turns on both NMOS transistors, thus directly pulling ML to ground.

[0034] In the implementation of a three-state content-addressable memory mode, FeFET1 and FeFET2 have stored a pair of complementary states (denoted as S' and S') before performing the matching operation. Complementary input signals Y and Y' are connected respectively. The ML node is precharged to the reference voltage Vr. By detecting the voltage on ML, it can be determined whether the storage state S matches the input Y.

[0035] Please see Figure 3If both S and Y are logic "1", only the upper-layer NMOS and FeFET2 are turned on, while the lower-layer NMOS and FeFET1 are turned off, preventing a path to ground. Since both S and Y are logic "1", a path to ground cannot be formed, and the ML voltage remains constant, indicating a match. Conversely, if S and Y are opposite, one transistor on each side will be turned on at any given time, forming a ground path and causing the ML voltage to drop rapidly, indicating a mismatch. Furthermore, in the "irrelevant" mode of tri-state content-addressable memory, both S and S' are set to "0". In this mode, regardless of the input value of Y, the cell outputs a matching result, supporting fuzzy lookups and returning addresses with partially identical data. This mechanism significantly improves the efficiency and applicability of the matching operation. The simulation waveforms of matching and mismatch in tri-state content-addressable memory mode performed in a FeFET-based multi-functional cell are shown below. Figure 8 As shown.

[0036] Example 2

[0037] Please see Figure 4 This embodiment provides a FeFET-based multifunctional memory computing array. The array consists of multiple FeFET-based multifunctional cells arranged in M ​​rows × N columns as described in Embodiment 1, including a core cell array, word line drivers, write and search line buffers, a multifunctional sense amplifier, and an output encoder. Match lines ML and word lines WL1 and WL2 are arranged horizontally, while bit lines SL1 and SL2 are arranged vertically. The common output of each row of cells is connected to one ML, and the end of each ML is connected to a sensitive amplifier.

[0038] During operation, the search line is driven by the input buffer, and the signal is transmitted vertically to each unit. Each matching line is connected to a sensitive amplifier, which detects the voltage state of the matching line and outputs the match / mismatch result to the encoder. Finally, the encoder generates a "hit" signal based on the matching status and outputs the address information corresponding to the matched entry.

[0039] Example 3

[0040] This embodiment provides a radiation-hardened memory computing unit (FeRH-TCAM) based on FeFET. Building upon the unit circuit of Embodiment 1, it connects a single-cycle memory module (DICE) and four transfer transistors at node N1 (the connection point between FeFET1 and M1). The DICE module has four cyclically symmetrical sensitive nodes (N1-N4) and possesses self-recovery capability. During a search operation, if a sensitive node (such as N1) experiences a single-event flip due to a radiation particle impact, the DICE's cross-coupling feedback mechanism quickly pulls the remaining nodes back to the correct potential, thereby suppressing error propagation. Please refer to [link to relevant documentation]. Figure 5 (a).

[0041] Figure 5 (b) illustrates a single-row FeRH-TCAM cell. The cell enables row access via a shared word line and includes bit lines and complementary bit lines for write and read access. A match line is connected to a comparator that evaluates its voltage level against a reference voltage Vref. If the match line voltage is higher than Vref at the sampling time of the comparator output, a match signal is issued; otherwise, the comparator issues a mismatch signal.

[0042] Figure 9 Simulation results of the radiation-hardened unit (FeRH-TCAM) under fault injection are presented. Even when a single node is disturbed, the voltage on the matching line remains in the correct logic state, greatly improving the reliability of the circuit in a radiated environment.

[0043] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A ferroelectric transistor (FeFET) based multi-functional memory computing unit, array and its fault-tolerant method, characterized in that: It includes two N-type ferroelectric transistors and two NMOS transistors; the first part consists of a first NMOS transistor M1 and a second ferroelectric transistor FeFET2 connected in parallel, with the drain connected to the drain of M1 and connected to the matching line ML as the output terminal, and the sources of both connected to the second part; the second part consists of a second NMOS transistor M2 and a first ferroelectric transistor FeFET1 connected in parallel, with the sources of both connected to the first part, and the drain connected to the drain of M2 and grounded. FeFET1 and FeFET2 are used for non-volatile data storage; by controlling the voltage of the first bit line SL1, the second bit line SL2, the first word line WL1 and the second word line WL2, the unit can switch between memory mode, in-memory logic calculation mode and tri-state content addressable memory mode.

2. The FeFET-based multifunctional memory computing unit of claim 1, wherein, In memory mode, WL1 and WL2 control the corresponding access transistors to achieve independent writing and reading of FeFET1 and FeFET2.

3. The FeFET-based multifunctional memory computing unit of claim 1, wherein, In the in-memory logic computation mode, by configuring the potential relationship between WL1, WL2 and SL1, SL2, the cell can realize Boolean logic operation results including NOT, NAND, NOR, and XOR on the matching line ML after pre-charging. The values ​​stored in FeFET1 and FeFET2 serve as logic input terminals, and the logic function can be reconfigured through different voltage combinations.

4. The FeFET-based multifunctional storage and computing unit according to claim 1, characterized in that, In tri-state content-addressable memory mode, FeFET1 and FeFET2 store a pair of complementary state data, and SL1 and SL2 serve as search lines to input complementary search data. By pre-charging ML and detecting its voltage change, it is determined whether the stored data matches the search data. If the value stored in FeFET2 matches the search bit of SL (correspondingly, the value stored in FeFET1 matches...), then... If the values ​​on both FeFETs are "0", the matching line cannot discharge. When both FeFETs are stored as "0", the cell is in an "irrelevant" state. Otherwise, the matching line discharge is enabled.

5. A multi-functional memory computing array based on FeFET, characterized in that, It includes: A core array is formed by arranging multiple multi-row, multi-column multi-functional storage and computing units as described in any one of claims 1 to 4; Multiple character lines WL1 and WL2 are arranged along the row direction to connect the corresponding row units; Multiple bit lines SL1 and SL2 are arranged along the column direction and connect the cells of the corresponding column; Multiple matching lines ML are arranged along the row direction, and the common output terminal of each row unit is connected to one ML; The peripheral circuitry includes word line drivers, bit line buffers, multi-function sense amplifiers connected to each ML, and encoders connected to the output of the sense amplifiers.

6. The FeFET-based multifunctional storage and computing array according to claim 5, characterized in that, The multi-functional sense amplifier is used to detect the voltage of ML in read / write mode to read data; to convert the analog voltage of ML into the result of logical operation in in-memory logic calculation mode; and to compare the voltage of ML with the reference voltage in tri-state content-addressable memory mode and output a match / mismatch signal.

7. A FeFET-based multi-functional unit for radiation-hardening, characterized by: The device includes the unit as described in claim 1, a single-cycle memory module DICE, and four transmission transistors; the single-cycle memory module consists of four two-input inverters, including a first inverter INV1, a second inverter INV2, a third inverter INV3, and a fourth inverter INV4; the four transmission transistors include a first transmission transistor M11, a second transmission transistor M12, a third transmission transistor M13, and a fourth transmission transistor M14; the gates of the four transmission transistors all serve as switches for reading and writing data in the single-cycle memory module, the drains are connected to the data controlled by the search line, and the sources are respectively connected to the storage nodes of the memory module.

8. A single-node flip-hardened FeFET multifunctional cell based on an inverter according to claim 7, characterized in that: The signal output terminal of the first inverter INV1 is connected to the input terminal M6 of the second inverter INV2 and the input terminal M9 of the fourth inverter INV4, respectively. The signal output terminal of the second inverter INV2 is connected to the input terminal M8 of the third inverter INV3 and the input terminal M3 of the first inverter INV1, respectively. The signal output terminal of the third inverter INV3 is connected to the input terminal M10 of the fourth inverter INV4 and the input terminal M5 of the second inverter INV2, respectively. The signal output terminal of the fourth inverter INV4 is connected to the input terminal M4 of the first inverter INV1 and the input terminal M7 of the third inverter INV3, respectively.

9. A single-node flip-hardened FeFET multifunctional cell based on an inverter according to claim 8, characterized in that: The source of the first transmission transistor M11 is connected to the storage node N1 of the DICE, the gate is connected to the word line WL, and the drain is connected to the search line NSL. The source of the second transmission transistor M12 is connected to the storage node N2 of the DICE, the gate is connected to the word line WL, and the drain is connected to the search line SL. The source of the third transmission transistor M13 is connected to the storage node N3 of the DICE, the gate is connected to the word line WL, and the drain is connected to the search line NSL. The source of the fourth transmission transistor M14 is connected to the storage node N4 of the DICE, the gate is connected to the word line WL, and the drain is connected to the search line SL.

10. The inverter-based single-node flipping hardened FeFET multifunctional cell of claim 8, wherein: The DICE internally forms a large loop, and the signal flow of the nodes in the large loop is N1→N2→N3→N4→N1. The value of the previous node is positively fed back to the value of the next node, thereby maintaining the value of the entire unit.

11. The FeFET-based radiation-hardened multi-functional unit of claim 9, wherein, When a sensitive node such as N1 experiences a voltage jump due to a particle impact, the DICE structure connected to it forms four redundant storage nodes through a cross-coupling mechanism. When any node flips due to radiation, since the other three nodes still maintain the correct values, the disturbed node can be quickly restored to the correct potential through the cross-coupling feedback path, so that the voltage on ML can be restored to the correct state after the disturbance, thereby tolerating single-event upset events.

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