Processor instructions for secure pointer arithmetic

Abstract

An apparatus includes processor circuitry having an execution pipeline configured to execute instructions within an instruction stream, the instruction stream including a first instance of an instruction executable to compute an address for accessing a data array. The first instance of the instruction may specify a set of operands, the set of operands including a pointer to a base address of the data array, an index into the data array, and a size of a data element within the data array. In response to receiving the first instance of the instruction, the execution pipeline may be configured to perform an arithmetic operation including multiplication of the index and the size to generate a result for the address. In response to the arithmetic operation generating an overflow condition, the execution pipeline may be further configured to perform a first correction action preventing access to the data array.

Description

Technical Field

[0001] The embodiments described herein relate to computer systems including System-on-Chip (SOC) and multi-die packages. More specifically, the disclosed embodiments relate to methods for performing arithmetic when generating pointers to securely access memory locations. Background Technology

[0002] Computer systems (such as System-on-a-Chip (SoC)) typically include one or more processors that serve as the system's central processing unit (CPU), as well as various other components such as memory controllers and peripheral components. Memory is frequently used in SoCs to store data structures that can be used by one or more applications. In some cases, corruption of data structures in memory can lead to incorrect operation by applications reading from those data structures. Incorrect operation can then provide different applications with the opportunity to gain control and / or access to prohibited parts of the computer system. Therefore, memory system attacks are a specific type of attack that hackers can exploit to attempt to gain control of a computer system. Attached Figure Description

[0003] The following detailed embodiments are described with reference to the accompanying drawings, which will now be briefly described.

[0004] Figure 1 A block diagram illustrating an implementation of a system that includes an execution pipeline that supports pointer arithmetic operations is shown.

[0005] Figure 2 It shows the results at two time points. Figure 1 A block diagram of the implementation scheme for the system's memory circuit.

[0006] Figure 3 A block diagram depicts an implementation scheme for another system that includes an execution pipeline that supports canonical pointers.

[0007] Figure 4 A flowchart illustrating an implementation of a method for executing specific pointer arithmetic instructions is provided.

[0008] Figure 5 A flowchart is shown of an implementation of a method for generating a corrective action after a specific pointer arithmetic instruction causes an overflow condition.

[0009] Figure 6 Various implementation schemes of systems including coupled integrated circuits are illustrated.

[0010] Figure 7 A block diagram of an example computer-readable medium according to some implementation schemes is depicted.

[0011] Although the embodiments described in this disclosure may be subject to various modifications and alternatives, specific embodiments are shown by way of example in the accompanying drawings and will be described in detail herein. However, it should be understood that the drawings and the detailed description thereof are not intended to limit the embodiments to the specific forms disclosed, but rather are intended to cover all modifications, equivalents, and alternatives falling within the substance and scope of the appended claims. Detailed Implementation

[0012] As described, a hacker can attempt to gain access to a computer system using a memory attack. One particular type of memory attack involves pointer arithmetic. Applications typically use pointers to access multiple consecutive entries in a data array. If each array entry has the same size, the program can read or write a series of entries by setting the pointer to the base address of the array and repeatedly incrementing (or decrementing) the pointer by the entry size. A single entry anywhere in the array can be accessed by multiplying the array index value by the entry size and adding the result of the multiplication to the base address of the array. Therefore, a hacker could attempt to corrupt the data array by feeding in an excessively large index value, which would cause an overflow condition when multiplied by the size. This overflow condition could cause the multiplication operation to produce a value that, when added to the base address, does not correspond to the expected boundaries of the individual entries within the data array.

[0013] As used in this article, an "overflow condition" occurs when two or more numbers are used in an arithmetic operation and the result of the operation includes a value that contains more data bits than the result register. For example, a 64-bit register can hold an unsigned integer with a maximum value of 18,446,744,073,709,551,615 or a signed integer with a maximum value of 9,223,372,036,854,775,807. Therefore, index values ​​that are close to but do not exceed these maximum values ​​can generate an overflow condition even when used with a small array entry size.

[0014] When such an overflow condition occurs, the truncated result can be placed in the result register, where the result is not aligned with a multiple of the array entry size. Adding this misaligned value to the base pointer can then cause the array pointer to become misaligned with the array entry. A read access can then jump from the bottom of the first entry to the top of the second entry, resulting in the retrieval of corrupted data. Similarly, a write access could overwrite the bottom of the first entry and the top of the second entry, thereby corrupting both entries. In either case, subsequent use of the corrupted data can lead to unintended operations by the application and subsequently by the computer system, thus providing a hacker with an opportunity to gain access to and / or control of some or all operations of the computer system.

[0015] Hackers can introduce specific values ​​by using malicious software (often referred to as "malware") embedded within seemingly harmless applications such as games or utilities. When the "infected" application is launched, the malware is also launched and may remain active in the background even after the infected application terminates. Malware can attempt memory attacks, for example, via program calls to one or more application programming interfaces (APIs) provided by the computer system's operating system and / or by other software executing on the computer system. One or more variables passed to the API may be known or suspected to be related to array index values ​​or array entry sizes.

[0016] The disclosed embodiments address systems and methods for mitigating the effectiveness of such pointer arithmetic memory attacks. For example, the proposed embodiments include using specific instructions that specify a set of operands for generating pointer values. An execution pipeline configured to execute the specific instructions performs an arithmetic operation on two of the specified operands. In response to an overflow condition caused by the arithmetic operation, the execution pipeline causes a correction action, including preventing the result from being used as a pointer in a data array.

[0017] Figure 1 A block diagram illustrating an implementation of a system, such as a system-on-a-chip (SoC), is shown. As illustrated, system 100 includes processor circuitry 101 coupled to memory circuitry 170. Processor circuitry 101 includes an execution pipeline 110 and register circuitry 140. Furthermore, the execution pipeline 110 includes an instruction buffer 120 and arithmetic logic circuitry 130. System 100 may be, wholly or partially, a computing system such as a desktop or laptop computer, a smartphone, a tablet computer, or a wearable smart device. In some implementations, system 100 is a single IC, such as a system-on-a-chip, while in other implementations, system 100 may include multiple dies co-packaged as a single chip.

[0018] As shown, memory circuitry 170 can be implemented using any suitable type of memory cell, including volatile memory, non-volatile memory, and combinations thereof. Memory circuitry 170 may include one or more memory management controllers and may include memory circuitry such as static random access memory (SRAM), dynamic random access memory (DRAM), and / or non-volatile memory (such as flash memory). In some embodiments, memory circuitry 170 may include interfaces for accessing individual DRAM and / or flash memory devices. As an example, memory circuitry 170 may include SRAM, a first memory controller circuit for accessing DRAM, and a second memory controller for accessing flash memory. Program instructions and various types of data files may be stored in flash memory for long-term storage (such as when system 100 is powered off). During the boot process, an operating system and one or more applications may be started, including copying at least some of the instructions and related information into DRAM and / or SRAM for faster access by processor circuitry 101.

[0019] As illustrated, data array 175 is a one-dimensional array comprising multiple entries located at addresses 150a to 150e (collectively referred to as 150). In some embodiments, data array 175 may be defined as a multi-dimensional array that uses two or more index values ​​to identify specific entries in the array. For example, a two-dimensional array may include row and column indices, while a three-dimensional array may include row, column, and depth indices. Memory circuits typically use linear addressing schemes for addressing, where the range of locations can be, for example, from address zero to address X-1, where X is the total number of words included in the memory circuit. Therefore, converting two or more indices to an address involves multiplying the indices together to obtain a single index, and then multiplying the resulting index by the size of a single array element.

[0020] As illustrated, processor circuitry 101 may include one or more processor cores, each processor core including a corresponding execution pipeline, such as execution pipeline 110. Processor circuitry 101 may be configured to implement any suitable instruction set architecture (ISA), such as, for example, ARM. ™ PowerPC ® Blackfin ® Or x86 ISA or a combination thereof. As shown, processor circuitry 101 is further configured to implement at least one additional instruction, including specific instructions that can be executed to compute addresses for accessing data arrays in computer memory, such as data array 175 stored in memory circuitry 170. Using the specific instructions, processor circuitry 101 can generate read requests and write requests for addresses in memory circuitry 170.

[0021] As shown, execution pipeline 110 can be configured to execute instructions within an instruction stream. Instruction buffer 120 is configured to hold instruction streams, such as instruction instances 125a through 125e (collectively referred to as 125). Instruction instance 125 can be any suitable combination of instructions from a supported ISA and includes at least one instance of a particular instruction. For example, instruction instance 125a is depicted as the first instance of a particular instruction. Thus, instruction instance 125a is capable of execution to compute an address for accessing a data array 175 in memory circuitry 170. Instruction instance 125a specifies a set of operands that includes a pointer value (pointer 142) to the base address of the data array, a first scalar value (index 144) corresponding to an index in the data array, and a second scalar value (size 146) corresponding to the size of a data element within the data array. As shown, this set of operands is stored in register circuitry 140, which can be implemented as SRAM, latch circuitry, or any other suitable type of data storage circuitry. To specify a particular operand, instruction instance 125a may be defined as encoding an identifier for a register containing the specific operand. In other embodiments, register circuitry 140 may include a pointer to a location in memory circuitry 170 or other memory circuitry storing the value of the specified operand. Furthermore, instruction instance 125a may include a specified operand combined with the opcode of instruction instance 125a.

[0022] In response to receiving instruction instance 125a, execution pipeline 110 can be configured to perform an arithmetic operation including multiplication of index 144 and size 146 to generate a multiplication result 135 for an address to be accessed in data array 175. In some embodiments, result 135 may be stored in a register circuit of register circuit 140, such as by replacing any of pointer 142, index 144, or size 146. In other embodiments, arithmetic logic circuit 130 may store result 135 in different registers within register circuit 140. In various embodiments, result 135 may be directly passed to a load-memory unit or other execution unit in execution pipeline 110.

[0023] Execution pipeline 110 may use arithmetic logic circuitry 130 to perform one or more arithmetic operations using a set of operands, including multiplying index 144 by size 146. Arithmetic logic circuitry 130 may be, for example, an arithmetic logic unit configured to perform various integer arithmetic operations. In some embodiments, arithmetic logic circuitry 130 may be included within a larger execution unit in execution pipeline 110, such as a load-memory unit configured to generate memory transactions for accessing memory circuitry 170 and / or other memory circuitry in system 100.

[0024] Instruction instance 125a can be any suitable type of instruction that includes an arithmetic operation involving two or more operands in a set of operands, the result of which can be used as a pointer to a memory location. In some embodiments, instruction instance 125a can be a multiply-add instruction, wherein the arithmetic operation includes adding the multiplication result 135 to pointer 142. In other embodiments, instruction instance 125a can be a multiply-subtract instruction, wherein the arithmetic operation includes subtracting the multiplication result 135 from pointer 142. In yet another embodiment, instruction instance 125a can be a load or store instruction that includes performing an arithmetic operation involving two or more operands in a set of operands to determine a pointer to a memory location.

[0025] In response to an overflow condition generated by an arithmetic operation, execution pipeline 110 may be further configured to perform a first correction action that prevents access to data array 175. For example, arithmetic logic circuitry 130 may include a result register capable of storing a specific number of bits (e.g., 64 bits). If the result of multiplying index 144 by size 146 is greater than 64 bits, an overflow condition occurs, and the most significant bit beyond the 64th bit of the result is truncated, resulting in result 135 containing only 64 least significant bits. In response to the occurrence of the overflow condition, arithmetic logic circuitry 130 asserts an overflow signal 137, thereby indicating that the multiplication result has overflowed.

[0026] In some implementations, the first corrective action may include generating an exception that prevents an instance of an instruction from completing. For example, an assertion of overflow signal 137 may cause exception handling circuitry in processor circuitry 101 to suspend processing of the remaining instruction instance 125 (including further processing of instruction instance 125a) and instead fetch and process the instruction associated with the exception. This exception handling procedure may be configured to fetch instructions from different predetermined locations based on the source of the exception signal. Thus, overflow signal 137 may trigger the fetching of a specific set of instructions, or may invoke a series of events that ultimately lead to the fetching of a specific set of instructions.

[0027] In other embodiments, the first corrective action may include setting an indication of an overflow condition, such as an overflow signal 137. Subsequent instruction instances in instruction instance 125 may then poll the overflow signal 137 and, if asserted, cause execution pipeline e110 to skip one or more subsequent instructions that would otherwise cause access to data array 175. Thus, the assertion of overflow signal 137 allows bypassing access to data array 175, thereby preventing potential misaligned access. Other corrective actions are contemplated, including those described below. Figure 3 The example described.

[0028] Instructions that flag arithmetic overflows (such as instruction example 125a) can be used to mitigate memory attacks that rely on overflow conditions to generate pointers to data arrays that are misaligned with array entries. By detecting and flagging such overflow conditions, the use of misaligned pointers can be preempted.

[0029] It should be noted that Figure 1 The system 100 shown is for illustrative purposes only. Figure 1 The illustrations have been simplified to highlight the features relevant to this disclosure. Various embodiments may include different configurations of circuit elements. For example, a single execution pipeline is shown. In other embodiments, any suitable number of execution pipeline circuits may be included. Furthermore, execution pipeline 110 may include elements other than instruction buffer 120 and arithmetic logic circuitry 130. Processor circuitry 101 may also include additional elements such as instruction and data caches, translation back buffers, fetch prediction circuitry, etc. In various embodiments, the circuitry of system 100 (such as execution pipeline 110 and register circuitry 140) may be implemented using any suitable combination of sequential and combinational logic circuitry. Additionally, registers and / or memory circuitry (such as SRAM) may be used in these circuits to temporarily store information (such as instructions, data, address values, etc.).

[0030] Figure 1 The use of instructions is described to identify overflow conditions that occur after arithmetic operations involving operands of an instruction. As disclosed above, using such instructions can help prevent attacks on the computer system's memory. Figure 2 This illustrates how to perform such a memory attack without utilizing the published instructions. (Move to...) Figure 2 This shows the results at two time points (before and after the memory attack). Figure 1 The system's memory circuit.

[0031] At time t0, as shown, data array 175 has been written to memory circuitry 170. In various embodiments, processor circuitry 101, different processing circuits in system 100, or combinations thereof, can perform one or more memory transactions to store data array 175 in memory circuitry 170. As depicted, data array 175 includes entries 280a to 280n (collectively referred to as 280), each entry having an associated index value and offset value. The index value may correspond to a sequence of a corresponding entry in entry 280. The offset value may correspond to an address offset from base address 250 (e.g., a first address of data array 175). For example, first entry 280a has index 0 and offset 0, thereby indicating that the address of entry 280a starts from base address 250. Entry 280b has index 1 and offset 168, indicating that the first address of entry 280b is located at base address 250 plus offset 168. Note that for each subsequent entry 280, the index is incremented by one, and the offset is incremented by 168, thus indicating that the size of each entry in entry 280 is 168. Therefore, the starting address of a particular entry can be calculated by multiplying the index of the particular entry by the size 168 and adding the result to the base address 250.

[0032] Figure 1 The execution pipeline 110 can execute instances of different instructions in the ISA, which are capable of calculating the address for accessing the data array 175 in the memory circuitry 170 of system 100. Figure 1 Similar to instruction example 125a, this different instruction may also specify a set of operands, which includes an index value and a size value. In some embodiments, a base pointer value may be included in the operand set. As illustrated, execution of the different instruction example involves performing a specific arithmetic operation that includes the multiplication of the index value and the size value to produce a multiplication result against an address. Unlike instruction example 125a, execution of the different instruction does not cause a first correction action to be performed in response to an overflow condition generated by the arithmetic operation.

[0033] Therefore, a hacker could potentially write malware code that calls APIs that take index values ​​as input. The malware might not use valid index values ​​from 0 to n, but instead use very large index values ​​that cause an overflow when multiplied by a size value. As shown in the diagram, the index value "109802048057794951" is used in the first API call. When multiplied by the size value 168 and truncated to a 64-bit value, the multiplication result produces an offset value of 152. When added to base address 250, this generates an address pointer that falls between the starting addresses of entries 280a and 280b, and is therefore misaligned with entry 280.

[0034] As shown in the figure, this malicious code can continue to increment excessively large index values, thereby generating a series of attack entries 282a to 282n. If the API uses these misaligned attack entries 282a to 282n to store values ​​in data array 175, the original entries 280a to 280n may be corrupted. Subsequent access to data array 175 by a legitimate program executing in system 100 can use a correctly generated aligned address pointer to read a corrupted entry in entry 280, which may lead to unintended behavior of system 100. This unintended behavior allows the malware to gain access to memory locations it should not be allowed to access, and / or enables the malware to control system 100.

[0035] It should be noted that Figure 2 The implementation scheme is an example of how a memory attack can be performed. As previously described, for clarity, Figure 2 The components included are limited. The values ​​used in the illustrated example are for demonstrating the example attack. It is conceivable to use other values ​​to generate attack entries 282a through 282n.

[0036] Go to Figure 3 This describes another system comprising memory circuitry and processor circuitry, the processor circuitry being configured to execute instructions that detect overflow conditions after performing arithmetic operations. Figure 1 Similar to system 100, system 300 includes processor circuitry 301 and memory circuitry 370. The components of system 300 may correspond to the descriptions of components in system 100 with similar naming and numbering, except as described below.

[0037] As illustrated, processor circuitry 301 may be configured to receive a first instance of a specific instruction (e.g., instruction instance 325a) capable of executing to determine a pointer to one of addresses 350a to 350e included in data structure 375 within memory circuitry 370. Instruction instance 325a may specify a set of operands including a base address value (pointer 342), an index value (index 344), and a size value (size 346). In response to the execution of instruction instance 325a, processor circuitry 301 (e.g., using arithmetic logic circuitry 330) may be further configured to perform an arithmetic operation including multiplication of index 344 and size 346 to generate a multiplication result for the pointer. An overflow condition (such as those mentioned above) is generated in response to the arithmetic operation. Figure 2 As described, processor circuitry 301 may be further configured to perform a first correction action that prevents access to data structure 375.

[0038] As shown in the figure, processor circuitry 301 can be further configured to utilize a canonical format for pointers. This canonical format may include a specific number of bits, where a first proper subset of the specified number of bits is used to indicate that a second proper subset of the specified number of bits, excluding the first proper subset, corresponds to the pointer value. For example, the pointer value may use a 64-bit format, where four bits (e.g., the four most significant bits) are used as a pointer label. This pointer label may be a specific value (e.g., "0000", "1111", or "1010") to indicate that the remaining 60 bits are intended to be used as a valid address pointer. Values ​​used as pointers with a valid label value are considered "canonical" pointers. If a value that does not have a valid label value in the four most significant bits is used as a pointer, that value is considered a "non-canonical" pointer and can be processed differently from a canonical pointer.

[0039] To enable the first correction action, processor circuitry 301 may be further configured to generate a result pointer value with a decanted format (e.g., decanted pointer 335) as a result of instruction instance 325a. Processor circuitry 301 may also be configured to execute a subsequent instance of an instruction within the instruction stream (e.g., instruction instance 325b). Instruction instance 325b may specify the result pointer value (decanted pointer 335) as an operand. In response to the result pointer value having a decanted format, processor circuitry 301 may be further configured to enable a second correction action that prevents access to a data structure. To enable the second correction action, processor circuitry 301 may be further configured to generate an exception that prevents instruction instance 325b from completing.

[0040] For example, the generated exception may guide processor circuitry 301 to retrieve a specific exception service routine, which can be executed to determine the source of the operands used to generate the non-canonical pointer value. In some cases, instruction instance 325a may be included in an API that is available for invocation by an active application. The specific exception service routine may use these operands to identify a given application that is invoking this API. Various actions may be taken to prevent further execution of the identified application, such as idling the application and / or deleting the application.

[0041] In some implementations, instruction instance 325a may be a store instruction that causes an arithmetic operation to be performed. In other implementations, instruction instance 325a may be a load instruction that causes an arithmetic operation to be performed. In such implementations, a decanted pointer may be generated and used in the same instruction, wherein an attempt to use the decanted pointer results in an exception, thereby preventing the store or load instruction from completing an access to memory.

[0042] It should be noted that Figure 3 The system described is merely an example. Figure 1 similar, Figure 3Simplified to highlight features relevant to this disclosure. Various embodiments may include different configurations of circuit elements. For example, a single execution pipeline is shown. In other embodiments, any suitable number of execution pipeline circuits may be included. Furthermore, execution pipeline 310 may include elements other than instruction buffer 320, arithmetic logic circuitry 330, and load-store circuitry 360. Processor circuitry 101 may also include additional elements such as instruction and data caches, translation lookup buffers, fetch prediction circuitry, etc. In various embodiments, the circuitry of system 300 (such as execution pipeline 310 and register circuitry 340) may be implemented using any suitable combination of sequential and combinational logic circuitry. Additionally, registers and / or memory circuitry (such as SRAM) may be used in these circuits to temporarily store information (such as instructions, data, address values, etc.).

[0043] In summary, various embodiments of the device may include processor circuitry including execution pipeline circuitry configured to execute instructions within an instruction stream, the instruction stream including a first instance of an instruction capable of calculating an address for accessing a data array in computer memory. The first instance of the instruction may specify a set of operands including a pointer value to a base address of the data array, a first scalar value corresponding to an index in the data array, and a second scalar value corresponding to the size of a data element within the data array. In response to receiving the first instance of the instruction, the execution pipeline circuitry may be configured to perform an arithmetic operation including multiplication of the index and size to generate a multiplication result for the address. In response to the arithmetic operation generating an overflow condition, the execution pipeline circuitry may be further configured to perform a first correction action that prevents access to the data array.

[0044] In another example, to specify a set of operands, an instruction can be defined as encoding one or more identifiers of the corresponding registers containing some of the operands in the set. In yet another example, a data array can be defined as a multidimensional array.

[0045] In the example, the execution pipeline circuitry can be further configured to assert an overflow signal in response to an overflow condition. The processor circuitry can be further configured to generate a specific exception that prevents the completion of an instruction instance. In another example, to prevent instruction completion, the processor circuitry can be further configured to: suspend further processing of instructions within the instruction stream; and fetch and process the instruction associated with the specific exception.

[0046] The above text is about Figures 1 to 3 The described circuits and techniques can be used in various ways to execute specific instructions. The following text combines... Figure 4 and Figure 5Two methods are described and associated with the execution of instructions capable of detecting overflow conditions. In some embodiments, the operation of the disclosed methods can be performed using instructions included in a non-transitory computer-readable memory having program instructions executable by processor circuitry in the system to enable reference... Figure 4 and Figure 5 The described operation.

[0047] Now move to Figure 4 A flowchart illustrating an implementation of a method for executing instructions capable of detecting overflow conditions by processor circuitry is shown. Method 400 can be executed by a system (such as...) Figures 1 to 3 The following text uses systems 100 and 300 to execute. Figure 1 System 100 is used as an example to describe method 400. Figure 1 References to elements in the text are included as unrestricted examples.

[0048] Method 400 begins at block 410 with the following operation: the execution pipeline of the processor circuitry (e.g., processor circuitry 101) of the computer system having an ISA executes an instance of an instruction in the ISA (e.g., instruction instance 125a) that is executable to compute an address for accessing a data array 175 in the memory circuitry 170 of system 100. Figure 1 As shown, instruction instance 125a is within the instruction stream (e.g., instruction instance 125 in instruction buffer 120) and specifies an operand set including a pointer value (pointer 142) to the base address of the data array, a first scalar value (index 144) corresponding to an index in the data array, and a second scalar value (146) corresponding to the size of a data element within the size of the data array.

[0049] As illustrated, execution of instruction instance 125a at block 415 of method 400 includes performing an arithmetic operation at block 420, comprising multiplying index 144 and size 146, to produce a multiplication result against an address. For example, in some embodiments, instruction instance 125a may be a multiply-add instruction, wherein the arithmetic operation comprises adding the result of multiplying index 144 and size 146 to pointer 142. In other embodiments, instruction instance 125a may be a multiply-subtract instruction, wherein the arithmetic operation comprises subtracting the result of multiplying index 144 and size 146 from pointer 142.

[0050] Execution of instruction instance 125a in method 400 also includes, at block 430, generating an overflow condition in response to an arithmetic operation to cause a first correction action that prevents access to data array 175. In some embodiments, the first correction action includes generating an exception that prevents instruction instance 125a from completing. In some cases, the overflow condition may indicate an overflow of the multiplication result. In other cases, the overflow condition may indicate an overflow caused by performing an arithmetic operation using the multiplication result (e.g., by adding the result to pointer 142).

[0051] In some implementations, instances of different instructions in the ISA may also be executable to compute addresses for accessing specific data arrays in the memory of a computer system. This different instruction may also specify the same set of operands as instruction instance 125a, including pointer 142, index 144, and size 146. This instance of executing the different instruction may include performing a specific arithmetic operation involving multiplication of index 144 and size 146 to produce a multiplication result for an address. Unlike instruction instance 125a, instances of executing the different instruction do not cause a first correction action in response to an overflow condition generated by the arithmetic operation. For example, the different instruction may be a conventional multiply-add (or multiply-subtract) instruction, such as those included in certain ISAs. Therefore, the disclosed instructions may be additional instructions added to such ISAs to enhance the ability to identify and mitigate hacking attempts.

[0052] It should be noted that Figure 4 The method includes blocks 410 through 430. Method 400 may end at block 430, or some or all of the blocks of the method may be repeated. For example, method 400 may be repeated in response to receiving another instance of an instruction. Method 400 may be executed concurrently with different instances of method 400. For example, processor circuitry 101 may include multiple execution pipelines, each capable of executing a corresponding instance of the disclosed instructions in an overlapped manner.

[0053] Turn now Figure 5 A flowchart illustrating an implementation of a method for executing instructions capable of detecting canonical and decanted pointers by processor circuitry is provided. Similar to method 400, method 500 can be implemented by a system (such as...) Figures 1 to 3 The following text uses systems 100 and 300 to execute. Figure 3 System 300 is used as an example to describe method 500. Figure 3 References to elements in are included as non-restrictive examples. Method 500 may correspond to box 430 of method 400. Thus, method 500 may begin with the following operation: the execution pipeline 310 has already performed an arithmetic operation in box 420, including multiplication of index 344 and size 346.

[0054] At box 510, method 500 begins with the following operation: Pipeline 310 performs a first correction action for the result of instruction instance 325a, generating a result pointer value with a non-canonical format. (See above regarding...) Figure 3 The disclosed canonical format may include a specific number of bits, where a first portion of the bits is used to indicate that a second, non-overlapping portion of the bits corresponds to a valid pointer value. For example, a given address pointer value may include 64 bits, with eight bits corresponding to the first portion and the remaining 56 bits corresponding to the second portion. A specific value for the first portion (e.g., 0b01010101 or 0b11110000) can be used to indicate that the remaining 56 bits are a valid pointer value. If the first portion does not have a specific value, the resulting pointer value is uncanonical.

[0055] Method 500 continues at block 520 as follows: Execution pipeline 310, in response to a result pointer value with a non-canonical format being supplied as an operand to a subsequent instruction instance 325b within instruction instance 325, performs a second correction action that prevents access to data structure 375. For example, instruction instance 325a could be an instance of a multiply-accumulate instruction whose result is used by instruction instance 325b (or 325c, or 325d, etc.) as an address pointer to data structure 375. Attempts to use the non-canonical pointer value can trigger the second correction action described next at block 530.

[0056] At block 530, method 500 continues by executing pipeline 310 to generate an exception for the second correction action, which prevents instruction instance 325b from completing. In some implementations, for example, the generated exception may be reserved for use in response to an attempt to use a non-canonical pointer. The generated exception may guide processor circuitry 301 to retrieve a specific exception service routine, which is capable of execution to prevent further execution of the program thread associated with the operand that caused the generation of the non-canonical address pointer. For example, an antivirus and / or anti-malware program may be activated to determine whether the associated program thread contains features of a known type of virus / malware.

[0057] It should be noted that Figure 5 The method includes blocks 510 to 530. Method 500 may end in block 530, or some or all of the operations may be repeated. For example, method 500 may be repeated in response to another instance of an instruction that results in a non-canonical pointer value. Similar to method 400, method 500 may be executed concurrently with different instances of methods 400 and / or 500.

[0058] Figures 1 to 5Circuits and methods for use in systems such as System-on-a-Chip (SoCs) are illustrated, including an execution pipeline capable of executing instructions that detect overflow conditions during pointer arithmetic. Any implementation of the disclosed systems can be included in one or more computer systems of various types, such as desktop computers, laptop computers, smartphones, tablets, and wearable devices. In some implementations, the circuitry described above can be implemented on a System-on-a-Chip (SoC) or other types of integrated circuits, including multi-die packages. Figure 6 A block diagram illustrating an embodiment of system 600 is shown. In some embodiments, system 600 may include any of the disclosed embodiments of the system disclosed herein, such as Figures 1 to 3 The systems shown are 100 and 300.

[0059] In the illustrated embodiments, system 600 includes at least one instance of a system-on-a-chip (SOC) 606, which may include various types of processor circuitry (such as a central processing unit (CPU), graphics processing unit (GPU), or others), communication architectures, and interfaces to memory and input / output devices. SOC 606 may correspond to instances of the processor circuitry and / or systems disclosed herein. In various embodiments, SOC 606 is coupled to external memory circuitry 602, peripheral devices 604, and a power supply 608.

[0060] A power supply 608 is also provided, which supplies power voltage to the SOC 606 and one or more power voltages to the external memory circuitry 602 and / or peripheral devices 604. In various embodiments, the power supply 608 represents a battery (e.g., a rechargeable battery in a smartphone, laptop, tablet, or other device). In some embodiments, more than one instance of the SOC 606 is included (and more than one external memory circuitry 602 is also included).

[0061] External memory circuitry 602 can be any type of memory, such as Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Dual Data Rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, and / or low-power versions of SDRAM, such as LPDDR2), RAMBUS DRAM (RDRAM), Static RAM (SRAM), etc. In some embodiments, external memory circuitry 602 may include non-volatile memory, such as flash memory, ferroelectric random access memory (FRAM), or magnetoresistive RAM (MRAM). One or more memory devices may be coupled onto a circuit board to form a memory module, such as a Single In-line Memory Module (SIMM), a Dual In-line Memory Module (DIMM), etc. Alternatively, these devices may be mounted with a System-on-a-Chip (SoC) or integrated circuit in a chip-stacked configuration, a package-stacked configuration, or a multi-chip module configuration.

[0062] Depending on the type of system 600, peripheral device 604 may include any desired circuitry. For example, in one embodiment, peripheral device 604 may include devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, GPS, etc. In some embodiments, peripheral device 604 may also include additional storage devices, including RAM storage devices, solid-state storage devices, or disk storage devices. Peripheral device 604 may include user interface devices such as displays, including touch displays or multi-touch displays, keyboards or other input devices, microphones, speakers, etc.

[0063] As illustrated, system 600 is shown to have applications in a wide range of fields. For example, system 600 can be used as part of a chip, circuit, component, etc., in a desktop computer 610, laptop computer 620, tablet computer 630, cellular or mobile phone 640, or television 650 (or a set-top box coupled to a television). Smartwatches and health monitoring devices 660 are also illustrated. In some embodiments, a smartwatch may include various general computing-related functions. For example, a smartwatch may provide access to email, mobile phone services, user calendars, etc. In various embodiments, a health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functionality. In various embodiments, the aforementioned smartwatch may or may not include some or any health monitoring-related functions. Other wearable devices 660 are also envisioned, such as devices worn around the neck, devices attached to hats or other helmets, devices that can be implanted in the human body, glasses designed to provide augmented and / or virtual reality experiences, etc.

[0064] System 600 can be further used as part of a cloud-based service 670. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, system 600 can be used in one or more devices in home 680 in addition to those previously mentioned. For example, home appliances can monitor and detect noteworthy situations. Various devices in the home (e.g., refrigerators, cooling systems, etc.) can monitor the status of the devices and provide alerts to the homeowner (or, for example, a repair service) upon detecting a specific event. Alternatively, a thermostat can monitor the temperature in the home and can automatically adjust the heating / cooling system based on the homeowner's history of responses to various situations. Figure 6 The document also illustrates the application of system 600 to various modes of transportation 690. For example, system 600 can be used for control and / or entertainment systems of airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, and small motorcycles (for rental or private use). In various cases, system 600 can be used to provide automated guidance (e.g., autonomous vehicles) and general system control.

[0065] It should be noted that the various potential applications of System 600 can include a wide range of performance, cost, and power consumption requirements. Therefore, scalable solutions that enable the use of one or more integrated circuits to provide a suitable combination of performance, cost, and power consumption can be beneficial. These, and many other implementations, are possible and envisioned. It should be noted that... Figure 6 The devices and applications illustrated are merely illustrative and not intended to be limiting. Other devices are possible and envisioned.

[0066] Such as about Figure 6 As disclosed, system 600 may include one or more integrated circuits, which are included within a personal computer, smartphone, tablet computer, or other type of computing device. (The following is...) Figure 7 The document presents the process of using design information to design and produce integrated circuits.

[0067] Figure 7 This is a block diagram illustrating an example of a non-transitory computer-readable storage medium for storing circuit design information according to some implementation schemes. Figure 7 The implementation scheme can be used in the process of designing and manufacturing integrated circuits, such as one or more instances of systems 100 and 300 (or portions thereof) described above. In the illustrated implementation scheme, semiconductor manufacturing system 720 is configured to process design information 715 stored on a non-transitory computer-readable storage medium 710 and manufacture integrated circuit 730 based on the design information 715.

[0068] The non-transitory computer-readable storage medium 710 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 710 may be an installation medium, such as a CD-ROM, floppy disk, or magnetic tape device; computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory, such as flash memory; magnetic media, such as hard disk drives or optical storage devices; registers, or other similar types of memory elements, etc. The non-transitory computer-readable storage medium 710 may also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 710 may include two or more memory media that may reside in different locations (e.g., different computer systems connected via a network).

[0069] Design information 715 can be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 715 can be used by semiconductor manufacturing system 720 to manufacture at least a portion of integrated circuit 730. For example, the format of design information 715 can be recognized by at least one semiconductor manufacturing system such as semiconductor manufacturing system 720. In some embodiments, design information 715 may include a netlist specifying elements of a cell library and their connectivity. One or more cell libraries used during the logic synthesis of circuits included in integrated circuit 730 may also be included in design information 715. Such cell libraries may include information such as device or transistor-level netlists indicating cells included in the cell library, mask design data, and characterization data.

[0070] In various implementations, integrated circuit 730 may include one or more custom macrocells, such as memory, analog or mixed-signal circuitry, etc. In such cases, design information 715 may include information associated with the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor-level netlists. As used herein, mask design data may be formatted according to a Graphical Data System (GDSII) or any other suitable format.

[0071] The semiconductor manufacturing system 720 may include any of the various suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or by using ultraviolet treatment to modify the dielectric constant), etc. The semiconductor manufacturing system 720 may also be configured to perform various tests on the manufactured circuits to ensure proper operation.

[0072] In various embodiments, integrated circuit 730 is configured to operate according to a circuit design specified by design information 715, which may include performing any of the functionalities described herein. For example, integrated circuit 730 may include any of the various elements shown or described herein. Additionally, integrated circuit 730 may be configured to perform various functions described herein in conjunction with other components.

[0073] As used herein, a phrase in the form of “design information specifying the design of a circuit configured to…” does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated action or will include the specified components.

[0074] This disclosure includes references to “implementation” or groups of “implementation” (e.g., “some implementations” or “various implementations”). An implementation is a different specific implementation or instance of the disclosed concepts. References to “implementation,” “an implementation,” “a particular implementation,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0075] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with one embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors outside this disclosure, it is hereby expressed that any potential advantages described herein should not be construed as a limitation of the claims that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the types of improvements available to the designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0076] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any statement to the contrary in this disclosure. Therefore, this application is intended to allow for claims covering the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art to the advantage of this disclosure.

[0077] For example, features in this application can be combined in any suitable manner. Therefore, new claims may be made for any such combination of features during the filing of this application (or an application claiming priority thereto). Specifically, referring to the appended claims, features of dependent claims may be combined with features of other dependent claims, including claims dependent on other independent claims, where appropriate. Similarly, features from the respective independent claims may be combined where appropriate.

[0078] Thus, although the appended dependent claims may be drafted such that each dependent claim depends from a single other claim, additional dependencies are contemplated. Any combination of dependent features consistent with the present disclosure is contemplated, and such combinations may be claimed in this application or another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0079] In appropriate circumstances, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims in another format or statutory type (e.g., method).

[0080] Since the present disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the following paragraphs, and the definitions provided throughout the present disclosure, will be used to determine how claims drafted based on the present disclosure are to be interpreted.

[0081] References to items in the singular form (i.e., a noun or noun phrase preceded by "a," "an," or "the") are intended to mean "one or more" unless the context clearly dictates otherwise. Thus, without accompanying context, a reference to an "item" in a claim does not exclude additional instances of that item. "Multiple" items means a collection of two or more of the items.

[0082] The word "may" is used herein in an enabling sense (i.e., having the potential to, being able to), rather than in a mandatory sense (i.e., must).

[0083] The terms "comprising" and "including" and their forms are open-ended and mean "including but not limited to."

[0084] When the term "or" is used in the present disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context otherwise provides. Thus, the statement "x or y" is equivalent to "x or y, or both" and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make clear that "or" is used in an exclusive sense.

[0085] The expressions “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0086] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0087] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors might influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors along with other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0088] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether these factors are used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor as well as other unspecified factors. Consider the phrase “responding to B and executing A.” This phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be jointly executed in response to B and C. This phrase is also intended to cover implementation schemes where A is executed solely in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding to.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0089] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or protected by the claims as being “configured” to perform one or more tasks or operations. This expression—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a tangible thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be considered “configured” to perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as being “configured” to perform a task refers to tangible things such as devices, circuits, systems with processor units, and memory storing program instructions executable to perform the task. This phrase is not used herein to refer to intangible things.

[0090] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated.

[0091] The term "configured as" is not intended to mean "able to be configured as." For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA can be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0092] For the purposes of this U.S. patent application based on this disclosure, the statement in the claims that a structure is “configured” to perform one or more tasks is expressly intended not to invoke 35 USC § 112(f) for that claim element. If an applicant wishes to invoke part 112(f) during the filing of a U.S. patent application based on this disclosure, it will use the “component for [performing a function]” structure to state the elements of the claims.

[0093] Different “circuits” may be described in this disclosure. These circuits, or “circuits,” constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, depending on the circumstances. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits.

[0094] Therefore, the circuits / units / components and other elements illustrated in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoding unit” can be described as having the function of executing “the opcode of a processing instruction and routing that instruction to one or more of a plurality of functional units,” meaning that the decoding unit is “configured” to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0095] In various implementations, as discussed in the preceding paragraphs, circuits, cells, and other elements can be defined by the functions or operations they are configured to perform. The arrangement of these circuits / cells / components relative to each other and the manner in which they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill in the art, by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, the HDL description is a way of translating the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), register-passing language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit can include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a field-programmable gate array (FPGA) and implemented within the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often leads to scenarios where circuit or logic designers never specify a particular set of structures for the low-level implementations that goes beyond a description of what the circuits are configured to do, because that process is performed at different stages of the circuit implementation process.

[0096] The fact that a circuit can be implemented to the same specifications using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0097] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

Claims

1. An apparatus, the apparatus comprising: A processor circuit, the processor circuit including an execution pipeline circuit configured to execute instructions within an instruction stream, the instruction stream including a first instance of instructions executable to compute an address for accessing a data array in computer memory, the first instance of instructions specifying a set of operands, the set of operands including a pointer value to a base address of the data array, a first scalar value corresponding to an index in the data array, and a second scalar value corresponding to the size of a data element in the data array, wherein, in response to receiving the first instance of the instructions, the execution pipeline circuit is configured to: Perform an arithmetic operation including multiplication of the index and the size to generate a multiplication result for the address; and In response to the arithmetic operation generating an overflow condition, a first correction action is performed, which prevents access to the data array.

2. The apparatus of claim 1, wherein, in order to specify the set of operands, the instruction is defined as encoding one or more identifiers of the corresponding registers containing some of the operands in the set of operands.

3. The apparatus of claim 1, wherein the data array is defined as a multidimensional array.

4. The apparatus of claim 1, wherein the execution pipeline circuit is configured as follows: In response to the overflow condition, assert the overflow signal; and The processor circuit is configured as follows: A specific exception is generated, which prevents the first instance of the instruction from completing.

5. The apparatus of claim 4, wherein, in order to prevent the first instance of the instruction from completing, the processor circuitry is further configured to: Pause further processing of the instructions within the instruction stream; and Obtain and process instructions associated with the specific exception.

6. A method, the method comprising: An instance of an instruction in the ISA is executed by the execution pipeline of a processor circuit of a computer system having an instruction set architecture (ISA). The instance of the instruction is executable to compute an address for accessing a data array in the memory of the computer system. The instruction is within an instruction stream and specifies a set of operands, the set of operands including a pointer value to the base address of the data array, a first scalar value corresponding to an index in the data array, and a second scalar value corresponding to the size of a data element within the data array. Execution of the instance of the instruction includes: Perform an arithmetic operation including multiplication of the index and the size to generate a multiplication result for the address; and The arithmetic operation generates an overflow condition to cause a first correction action, which prevents access to the data array.

7. The method of claim 6, wherein the first correction action includes generating an exception, the exception preventing the instance of the instruction from completing.

8. The method of claim 6, wherein the overflow condition indicates an overflow of the multiplication result.

9. The method of claim 6, wherein the overflow condition indicates an overflow caused by performing the arithmetic operation using the multiplication result.

10. The method of claim 6, wherein the first correction action includes generating a result pointer value with a non-canonical format as a result of the instruction, the method further comprising: In response to the result pointer value having the non-canonical format being supplied as an operand to a subsequent instance of an instruction within the instruction stream, a second correction action is performed, which prevents access to the data array.

11. The method of claim 10, wherein the second correction action includes generating an exception, the exception preventing the subsequent instance of the instruction from completing.

12. The method of claim 6, wherein the instruction is a multiply-add instruction, and wherein the arithmetic operation includes adding the multiplication result to the pointer value.

13. The method of claim 6, wherein the instruction is a multiplication / subtraction instruction, and wherein the arithmetic operation includes subtracting the multiplication result from the pointer value.

14. The method according to claim 6, further comprising: Executing instances of different instructions in the ISA, the instances of which are executable to compute the address for accessing the data array, the different instructions further specifying operands including the set of operands, wherein execution of the instances of the different instructions includes: Perform a specific arithmetic operation that includes the multiplication of the index and the size to generate a multiplication result for the address, wherein the execution does not cause the first correction action in response to the arithmetic operation generating an overflow condition.

15. A system comprising: Memory circuits; Processor circuitry, the processor circuitry being configured to: A first instance of a specific instruction is received, the first instance of the specific instruction being executable to determine a pointer to a data structure in the memory circuit, wherein the first instance of the specific instruction specifies a set of operands, the set of operands including a base address value, an index value, and a size value; In response to the execution of the first instance, an arithmetic operation including the multiplication of the index value and the size value is performed to generate a multiplication result for the pointer; as well as In response to the arithmetic operation generating an overflow condition, a first correction action is performed, which prevents access to the data structure.

16. The system of claim 15, wherein the processor circuitry is further configured to use a canonical format for the pointer, wherein the canonical format includes a specific number of bits, wherein a first proper subset of the specific number of bits is used to indicate that a second proper subset of the specific number of bits, other than the first proper subset, corresponds to the pointer value.

17. The system of claim 16, wherein, in order to perform the correction operation, the processor circuitry is further configured to: As a result of the specific instruction, a result pointer value with a non-canonical format is generated; Execute subsequent instances of instructions within the instruction stream, wherein the subsequent instances of instructions specify the result pointer value as an operand; and In response to the result pointer value having the non-canonical format, a second correction action is performed, which prevents access to the data structure.

18. The system of claim 17, wherein, in order to perform the second correction action, the processor circuitry is further configured to generate an exception, the exception preventing the subsequent instance of the instruction from completing.

19. The system of claim 15, wherein the specific instruction is a stored instruction that causes the arithmetic operation to be performed.

20. The system of claim 15, wherein the specific instruction is a load instruction that causes the arithmetic operation to be performed.

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